coreboot-gerrit February 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/intel/meteorlake: Update soc_intel_meteorlake_config structure
by Kapil Porwal (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Tarun Tuli, Sridhar Siricilla. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72871 ) Change subject: soc/intel/meteorlake: Update soc_intel_meteorlake_config structure ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40ec3775b827ab6e1ebd4778c6c8e13eac1944e5 Gerrit-Change-Number: 72871 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Tue, 07 Feb 2023 11:12:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: device: Add Kconfig options for D3COLD_SUPPORT and NO_S0IX_SUPPORT
by Lean Sheng Tan (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Sean Rhodes, Tarun Tuli, Subrata Banik. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72799 ) Change subject: device: Add Kconfig options for D3COLD_SUPPORT and NO_S0IX_SUPPORT ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04abc7efe2db06ae6daba9e09835441b62ee44f4 Gerrit-Change-Number: 72799 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Tue, 07 Feb 2023 11:11:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/tigerlake/acpi: Unify the way D3Cold is enabled
by Lean Sheng Tan (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Sean Rhodes, Tarun Tuli, Subrata Banik. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72798 ) Change subject: soc/intel/tigerlake/acpi: Unify the way D3Cold is enabled ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6eaba99e5483053a91ca20df2b7788edac5d65b2 Gerrit-Change-Number: 72798 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Tue, 07 Feb 2023 11:10:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Remove unused S0IX variable
by Lean Sheng Tan (Code Review) 07 Feb '23

07 Feb '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72797 ) Change subject: soc/intel/alderlake: Remove unused S0IX variable ...................................................................... soc/intel/alderlake: Remove unused S0IX variable Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I85fc5dabf10c6df7f11fd1defe8a39afc9f95325 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72797 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/acpi/tcss.asl 1 file changed, 15 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl index 9edaf77..9ef6637 100644 --- a/src/soc/intel/alderlake/acpi/tcss.asl +++ b/src/soc/intel/alderlake/acpi/tcss.asl @@ -42,12 +42,6 @@ Scope (\_SB) { -#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) - Name (S0IX, 0) -#else - Name (S0IX, 1) -#endif - /* Device base address */ Method (BASE, 1) { -- To view, visit https://review.coreboot.org/c/coreboot/+/72797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85fc5dabf10c6df7f11fd1defe8a39afc9f95325 Gerrit-Change-Number: 72797 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/prodrive/hermes: Add SATA hotplug EEPROM setting
by Justin van Son (Code Review) 07 Feb '23

07 Feb '23

Justin van Son has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72712 ) Change subject: mb/prodrive/hermes: Add SATA hotplug EEPROM setting ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Why is it not needed? Customer requested this, but they changed their mind later -- To view, visit https://review.coreboot.org/c/coreboot/+/72712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7dcd12049bdf7c2d200530acd8a6da5df726203 Gerrit-Change-Number: 72712 Gerrit-PatchSet: 2 Gerrit-Owner: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 07 Feb 2023 11:07:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/data_fabric_helper: normalize addresses in debug print
by Felix Held (Code Review) 07 Feb '23

07 Feb '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72739 ) Change subject: soc/amd/common/data_fabric_helper: normalize addresses in debug print ...................................................................... soc/amd/common/data_fabric_helper: normalize addresses in debug print Instead of just printing the register contents, normalize the contents of the base and limit registers to actual MMIO addresses and then print those. This will hopefully avoid some confusion caused by the shifted addresses. Output on Mandolin before the patch: === Data Fabric MMIO configuration registers === Addresses are shifted to the right by 16 bits. idx control base limit 0 93 fc00 febf 1 93 1000000 ffffffff 2 93 d000 f7ff 3 1093 fed0 fedf 4 90 0 0 5 90 0 0 6 90 0 0 7 90 0 0 Output on Mandolin after the patch: === Data Fabric MMIO configuration registers === idx control base limit 0 93 fc000000 febfffff 1 93 10000000000 ffffffffffff 2 93 d0000000 f7ffffff 3 1093 fed00000 fedfffff 4 90 0 ffff 5 90 0 ffff 6 90 0 ffff 7 90 0 ffff Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I62eeb88ddac6a7a421fccc8e433523459117976a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72739 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/common/block/data_fabric/data_fabric_helper.c 1 file changed, 59 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c index 412daae..b64edcd 100644 --- a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c +++ b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c @@ -47,16 +47,23 @@ void data_fabric_print_mmio_conf(void) { + uint32_t control; + uint64_t base, limit; printk(BIOS_SPEW, "=== Data Fabric MMIO configuration registers ===\n" - "Addresses are shifted to the right by 16 bits.\n" - "idx control base limit\n"); + "idx control base limit\n"); for (unsigned int i = 0; i < NUM_NB_MMIO_REGS; i++) { - printk(BIOS_SPEW, " %2u %8x %8x %8x\n", - i, - data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)), - data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)), - data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i))); + control = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); + /* Base and limit address registers don't contain the lower address bits, but + are shifted by D18F0_MMIO_SHIFT bits */ + base = (uint64_t)data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)) + << D18F0_MMIO_SHIFT; + limit = (uint64_t)data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i)) + << D18F0_MMIO_SHIFT; + /* Lower D18F0_MMIO_SHIFT address limit bits are all 1 */ + limit += (1 << D18F0_MMIO_SHIFT) - 1; + printk(BIOS_SPEW, " %2u %8x %16llx %16llx\n", + i, control, base, limit); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/72739 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62eeb88ddac6a7a421fccc8e433523459117976a Gerrit-Change-Number: 72739 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/common/data_fabric_helper: normalize addresses in debug print
by Felix Held (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Arthur Heymans. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72739 ) Change subject: soc/amd/common/data_fabric_helper: normalize addresses in debug print ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: i'm planning to add partial decoding of the control register in a follow-up; that should hopefully make it a bit clearer what is used and what isn't -- To view, visit https://review.coreboot.org/c/coreboot/+/72739 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62eeb88ddac6a7a421fccc8e433523459117976a Gerrit-Change-Number: 72739 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 07 Feb 2023 11:01:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Enable WWAN ACPI
by Harsha B R (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Jamie Ryu, Sridhar Siricilla, Usha P. Harsha B R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72779 ) Change subject: mb/intel/mtlrvp: Enable WWAN ACPI ...................................................................... Patch Set 7: (1 comment) File src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb: https://review.coreboot.org/c/coreboot/+/72779/comment/405b403c_b3612e67 PS7, Line 102: PCIE_RP_LTR > what about PCI error reporting? Thanks Sridhar. Here is the CL addressing this change - CB:72874 -- To view, visit https://review.coreboot.org/c/coreboot/+/72779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I870cc0782fb989f1bdbe369a4a12630a62729d8e Gerrit-Change-Number: 72779 Gerrit-PatchSet: 7 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Tue, 07 Feb 2023 11:00:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Enable PCIE Advanced Error Reporting
by Harsha B R (Code Review) 07 Feb '23

07 Feb '23

Harsha B R has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72874 ) Change subject: mb/intel/mtlrvp: Enable PCIE Advanced Error Reporting ...................................................................... mb/intel/mtlrvp: Enable PCIE Advanced Error Reporting This patch enables PCI Express Advanced Error Reporting Capability for WWAN, WLAN, and SSD root ports. On enabling PCIE_RP_AER, PCIE device will automatically report (if any error) about the error nature to the corresponding PCIe root port. BUG=b:224325352 BRANCH=None TEST=Build and boot mtlrvp to ChromeOS. Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: Iab8619818e2219b41287b895513eb04b0464401e --- M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb 1 file changed, 23 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/72874/1 diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index ddb80026..01a02f1 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -99,7 +99,7 @@ register "pcie_rp[PCIE_RP(7)]" = "{ .clk_src = 1, .clk_req = 1, - .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, }" end # WWAN device ref pcie_rp8 on @@ -107,7 +107,7 @@ register "pcie_rp[PCIE_RP(8)]" = "{ .clk_src = 5, .clk_req = 5, - .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, }" end # WLAN device ref pcie_rp10 on @@ -115,7 +115,7 @@ register "pcie_rp[PCIE_RP(10)]" = "{ .clk_src = 8, .clk_req = 8, - .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, }" end # PCIE10 SSD Gen4 device ref pcie_rp11 on @@ -123,7 +123,7 @@ register "pcie_rp[PCIE_RP(11)]" = "{ .clk_src = 7, .clk_req = 7, - .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, }" end # PCIE11 SSD Gen4 device ref xhci on end -- To view, visit https://review.coreboot.org/c/coreboot/+/72874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab8619818e2219b41287b895513eb04b0464401e Gerrit-Change-Number: 72874 Gerrit-PatchSet: 1 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: src: Move POST_BOOTBLOCK_CAR to common postcodes and use it
by Elyes Haouas (Code Review) 07 Feb '23

07 Feb '23

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71596 ) Change subject: src: Move POST_BOOTBLOCK_CAR to common postcodes and use it ...................................................................... src: Move POST_BOOTBLOCK_CAR to common postcodes and use it This moves the definition for POST_BOOTBLOCK_CAR from the intel-specific postcodes into the common postcode list, and uses it for the cache-as-RAM init as needed. Because POST_BOOTBLOCK_CAR was set to 0x20 in some spots and 0x21 in most of the others, the values were consolidated into 0x21. This will change the value on some platforms. Any conflicts should get sorted out later in the conversion process. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I8527334e679a23006b77a5645f919aea76dd4926 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71596 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/commonlib/include/commonlib/console/post_codes.h M src/cpu/qemu-x86/cache_as_ram_bootblock.S M src/drivers/intel/fsp1_1/cache_as_ram.S M src/include/cpu/intel/post_codes.h M src/soc/intel/common/block/include/intelblocks/post_codes.h 5 files changed, 31 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/src/commonlib/include/commonlib/console/post_codes.h b/src/commonlib/include/commonlib/console/post_codes.h index ef296bd..a8a8d95 100644 --- a/src/commonlib/include/commonlib/console/post_codes.h +++ b/src/commonlib/include/commonlib/console/post_codes.h @@ -72,6 +72,12 @@ #define POST_ENTRY_C_START 0x13 /** + * \brief Entry into bootblock cache-as-RAM code + * + */ +#define POST_BOOTBLOCK_CAR 0x21 + +/** * \brief Entry into pci_scan_bus * * Entered pci_scan_bus() diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index f828d6f..617da53 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -15,7 +15,7 @@ bootblock_pre_c_entry: cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_CAR) /* * Nothing to do here on qemu, RAM works just fine without any * initialization. @@ -103,7 +103,6 @@ #endif before_c_entry: - post_code(0x29) call bootblock_c_entry_bist /* Never returns */ .Lhlt: diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index 6a19b87..571feb4 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -34,7 +34,7 @@ movd %eax, %mm1 cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_CAR) /* Cache the rom and update the microcode */ cache_rom: @@ -181,8 +181,6 @@ pushl %eax /* tsc[31:0] */ before_romstage: - post_code(0x2a) - /* Call bootblock_c_entry(uint64_t base_timestamp) */ call bootblock_c_entry diff --git a/src/include/cpu/intel/post_codes.h b/src/include/cpu/intel/post_codes.h index 3db0aeb..6c1ca79 100644 --- a/src/include/cpu/intel/post_codes.h +++ b/src/include/cpu/intel/post_codes.h @@ -3,7 +3,6 @@ #ifndef CPU_INTEL_CAR_POST_CODES_H #define CPU_INTEL_CAR_POST_CODES_H -#define POST_BOOTBLOCK_CAR 0x20 #define POST_SOC_SET_DEF_MTRR_TYPE 0x21 #define POST_SOC_CLEAR_FIXED_MTRRS 0x22 // Intentional Duplicate #define POST_SOC_DETERMINE_CPU_ADDR_BITS 0x22 diff --git a/src/soc/intel/common/block/include/intelblocks/post_codes.h b/src/soc/intel/common/block/include/intelblocks/post_codes.h index d7c0ef1..7c78ef8 100644 --- a/src/soc/intel/common/block/include/intelblocks/post_codes.h +++ b/src/soc/intel/common/block/include/intelblocks/post_codes.h @@ -16,9 +16,6 @@ #define POST_SOC_CAR_INIT_DONE 0x29 #define POST_SOC_BEFORE_CARSTAGE 0x2a -/* common/block/cpu/car/cache_as_ram_fsp.S */ -#define POST_BOOTBLOCK_CAR 0x21 - /* common/block/cse/cse.c */ #define POST_CODE_ZERO 0x00 #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/71596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8527334e679a23006b77a5645f919aea76dd4926 Gerrit-Change-Number: 71596 Gerrit-PatchSet: 4 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit February 2023