coreboot-gerrit February 2023

coreboot-gerrit@coreboot.org

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5082 discussions

[S] Change in coreboot[master]: mb/google/skyrim/var/markarth: Override SPI flash bus speed
by Chao Gui (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Frank Wu, John Su, Jason Nien, Jon Murphy, Eric Lai, Martin Roth, Karthik Ramasubramanian. Chao Gui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72870 ) Change subject: mb/google/skyrim/var/markarth: Override SPI flash bus speed ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/72870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id46201351780bb5bc05422ff36dad6972285690e Gerrit-Change-Number: 72870 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chao Gui <chaogui(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 07 Feb 2023 13:55:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya: Create constitution variant
by Felix Held (Code Review) 07 Feb '23

07 Feb '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72730 ) Change subject: mb/google/brya: Create constitution variant ...................................................................... mb/google/brya: Create constitution variant Create the constitution variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:267539938 TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_CONSTITUTION Change-Id: Idb6089561d3aa5aac4448f9d46347c731f027e9c Signed-off-by: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72730 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/constitution/include/variant/ec.h A src/mainboard/google/brya/variants/constitution/include/variant/gpio.h A src/mainboard/google/brya/variants/constitution/overridetree.cb 5 files changed, 51 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index dad9821..c947ce8 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -155,6 +155,7 @@ default 0x1 if BOARD_GOOGLE_MARASOV default 0x1 if BOARD_GOOGLE_GAELIN default 0x1 if BOARD_GOOGLE_OMNIGUL + default 0x1 if BOARD_GOOGLE_CONSTITUTION config DRIVER_TPM_I2C_ADDR hex @@ -225,6 +226,7 @@ default "Gladios" if BOARD_GOOGLE_GLADIOS default "Marasov" if BOARD_GOOGLE_MARASOV default "Omnigul" if BOARD_GOOGLE_OMNIGUL + default "Constitution" if BOARD_GOOGLE_CONSTITUTION config VARIANT_DIR default "brya0" if BOARD_GOOGLE_BRYA0 @@ -267,6 +269,7 @@ default "gladios" if BOARD_GOOGLE_GLADIOS default "marasov" if BOARD_GOOGLE_MARASOV default "omnigul" if BOARD_GOOGLE_OMNIGUL + default "constitution" if BOARD_GOOGLE_CONSTITUTION config VBOOT select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 087837f..4b99708 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -332,3 +332,7 @@ select SOC_INTEL_RAPTORLAKE select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS select DRIVERS_INTEL_ISH + +config BOARD_GOOGLE_CONSTITUTION + bool "-> Constitution" + select BOARD_GOOGLE_BASEBOARD_BRASK diff --git a/src/mainboard/google/brya/variants/constitution/include/variant/ec.h b/src/mainboard/google/brya/variants/constitution/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/constitution/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/constitution/include/variant/gpio.h b/src/mainboard/google/brya/variants/constitution/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/constitution/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/constitution/overridetree.cb b/src/mainboard/google/brya/variants/constitution/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/constitution/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/72730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb6089561d3aa5aac4448f9d46347c731f027e9c Gerrit-Change-Number: 72730 Gerrit-PatchSet: 6 Gerrit-Owner: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Matthew Ziegelbaum <ziegs(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Pablo Ceballos <pceballos(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/common/data_fabric: print decoded control register contents
by Felix Held (Code Review) 07 Feb '23

07 Feb '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72880 ) Change subject: soc/amd/common/data_fabric: print decoded control register contents ...................................................................... soc/amd/common/data_fabric: print decoded control register contents Since all SoCs define the df_mmio_control union for the bits used in the code, data_fabric_print_mmio_conf can take advantage of that and also print a decoded version of those bits. Output on Mandolin before the patch: === Data Fabric MMIO configuration registers === idx control base limit 0 93 fc000000 febfffff 1 93 10000000000 ffffffffffff 2 93 d0000000 f7ffffff 3 1093 fed00000 fedfffff 4 90 0 ffff 5 90 0 ffff 6 90 0 ffff 7 90 0 ffff Output on Mandolin with the patch: === Data Fabric MMIO configuration registers === idx base limit control R W NP F-ID 0 fc000000 febfffff 93 x x 9 1 10000000000 ffffffffffff 93 x x 9 2 d0000000 f7ffffff 93 x x 9 3 fed00000 fedfffff 1093 x x x 9 4 0 ffff 90 9 5 0 ffff 90 9 6 0 ffff 90 9 7 0 ffff 90 9 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I06e1d3a3e9abd664f59f2bb852394e7f723f2b30 --- M src/soc/amd/common/block/data_fabric/data_fabric_helper.c 1 file changed, 49 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/72880/1 diff --git a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c index fe983ac..fb4b26c 100644 --- a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c +++ b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c @@ -47,13 +47,13 @@ void data_fabric_print_mmio_conf(void) { - uint32_t control; + union df_mmio_control control; uint64_t base, limit; printk(BIOS_SPEW, "=== Data Fabric MMIO configuration registers ===\n" - "idx control base limit\n"); + "idx base limit control R W NP F-ID\n"); for (unsigned int i = 0; i < DF_MMIO_REG_SET_COUNT; i++) { - control = data_fabric_broadcast_read32(0, DF_MMIO_CONTROL(i)); + control.raw = data_fabric_broadcast_read32(0, DF_MMIO_CONTROL(i)); /* Base and limit address registers don't contain the lower address bits, but are shifted by D18F0_MMIO_SHIFT bits */ base = (uint64_t)data_fabric_broadcast_read32(0, DF_MMIO_BASE(i)) @@ -62,8 +62,12 @@ << D18F0_MMIO_SHIFT; /* Lower D18F0_MMIO_SHIFT address limit bits are all 1 */ limit += (1 << D18F0_MMIO_SHIFT) - 1; - printk(BIOS_SPEW, " %2u %8x %16llx %16llx\n", - i, control, base, limit); + printk(BIOS_SPEW, " %2u %16llx %16llx %8x %s %s %s %4x\n", + i, base, limit, control.raw, + control.re ? "x" : " ", + control.we ? "x" : " ", + control.np ? "x" : " ", + control.fabric_id); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/72880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06e1d3a3e9abd664f59f2bb852394e7f723f2b30 Gerrit-Change-Number: 72880 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/mendocino/data_fabric: add Rembrandt DF_MMIO_REG_SET_SIZE
by Felix Held (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Jason Glenesk, Raul Rangel, ritul guru, Matt DeVillier, Fred Reitberger. Hello Jason Glenesk, Raul Rangel, ritul guru, Matt DeVillier, Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72879 to look at the new patch set (#2). Change subject: soc/amd/mendocino/data_fabric: add Rembrandt DF_MMIO_REG_SET_SIZE ...................................................................... soc/amd/mendocino/data_fabric: add Rembrandt DF_MMIO_REG_SET_SIZE In contrast to Mendocino and all other AMD SoCs in the coreboot tree, Rembrandt, on which Mendocino is based on, has a DF_MMIO_REG_SET_SIZE of 3 instead of 4, so the next data fabric MMIO register is 3 DWORDs after the last one instead of the 4 DWORDs on the other SoCs. This was checked against PPR #56558 Rev 3.04. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I454ad5d182f0040db93c9b3a83941333392c6061 --- M src/soc/amd/mendocino/include/soc/data_fabric.h 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/72879/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I454ad5d182f0040db93c9b3a83941333392c6061 Gerrit-Change-Number: 72879 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: acpi/acpigen.h: Fix EVENT_OP value
by Angel Pons (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Elyes Haouas, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72805 ) Change subject: acpi/acpigen.h: Fix EVENT_OP value ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c531e95f4fc741926bc883d869816f534ff3b7f Gerrit-Change-Number: 72805 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 07 Feb 2023 13:11:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: DEMO: Load MP2 fw by default
by Fred Reitberger (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Bao Zheng, Jason Glenesk, Martin L Roth, Marshall Dawson, Matt DeVillier, Zheng Bao, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71920 ) Change subject: DEMO: Load MP2 fw by default ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > Based on my test, it has to load the MP2 FW to boot on simulator. […] On Birman hardware, I was able to revert this patch and comment out the PSP_MP2FW0_FILE and PSP_MP2CFG_FILE lines in fw.cfg and still boot to x86 release. -- To view, visit https://review.coreboot.org/c/coreboot/+/71920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc779a7e0e12deb44b64b480ae9ca10d1ed0dbcb Gerrit-Change-Number: 71920 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 07 Feb 2023 13:08:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/mendocino/data_fabric: add Rembrandt DF_MMIO_REG_SET_SIZE
by Felix Held (Code Review) 07 Feb '23

07 Feb '23

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[S] Change in coreboot[master]: soc/amd/*/data_fabric: introduce and use DF_MMIO_REG_SET_SIZE
by Felix Held (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72878 ) Change subject: soc/amd/*/data_fabric: introduce and use DF_MMIO_REG_SET_SIZE ...................................................................... soc/amd/*/data_fabric: introduce and use DF_MMIO_REG_SET_SIZE To be able to handle a special case, add a per-SoC define for DF_MMIO_REG_SET_SIZE instead of having this hard-coded as 4 in the DF_MMIO_* macros. To avoid some duplication, also introduce the DF_MMIO_REG_OFFSET macro. TEST=Output from data_fabric_print_mmio_conf doesn't change on Mandolin. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I67420a2973c8ef9a7f0ce19ddc0013de69731689 --- M src/soc/amd/cezanne/include/soc/data_fabric.h M src/soc/amd/common/block/include/amdblocks/data_fabric.h M src/soc/amd/glinda/include/soc/data_fabric.h M src/soc/amd/mendocino/include/soc/data_fabric.h M src/soc/amd/phoenix/include/soc/data_fabric.h M src/soc/amd/picasso/include/soc/data_fabric.h 6 files changed, 27 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/72878/1 diff --git a/src/soc/amd/cezanne/include/soc/data_fabric.h b/src/soc/amd/cezanne/include/soc/data_fabric.h index 8e5c278..3b1f588 100644 --- a/src/soc/amd/cezanne/include/soc/data_fabric.h +++ b/src/soc/amd/cezanne/include/soc/data_fabric.h @@ -11,6 +11,7 @@ #define D18F0_MMIO_SHIFT 16 #define D18F0_MMIO_CTRL0 0x208 +#define DF_MMIO_REG_SET_SIZE 4 #define DF_MMIO_REG_SET_COUNT 8 #define DF_FICAA_BIOS 0x5C diff --git a/src/soc/amd/common/block/include/amdblocks/data_fabric.h b/src/soc/amd/common/block/include/amdblocks/data_fabric.h index dd4b079..c224a11 100644 --- a/src/soc/amd/common/block/include/amdblocks/data_fabric.h +++ b/src/soc/amd/common/block/include/amdblocks/data_fabric.h @@ -11,10 +11,12 @@ #define BROADCAST_FABRIC_ID 0xff +#define DF_MMIO_REG_OFFSET(instance) ((instance) * DF_MMIO_REG_SET_SIZE * sizeof(uint32_t)) + /* The number of data fabric MMIO registers is SoC-specific */ -#define DF_MMIO_BASE(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_BASE0) -#define DF_MMIO_LIMIT(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_LIMIT0) -#define DF_MMIO_CONTROL(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_CTRL0) +#define DF_MMIO_BASE(reg) (D18F0_MMIO_BASE0 + DF_MMIO_REG_OFFSET(reg)) +#define DF_MMIO_LIMIT(reg) (D18F0_MMIO_LIMIT0 + DF_MMIO_REG_OFFSET(reg)) +#define DF_MMIO_CONTROL(reg) (D18F0_MMIO_CTRL0 + DF_MMIO_REG_OFFSET(reg)) uint32_t data_fabric_read32(uint8_t function, uint16_t reg, uint8_t instance_id); void data_fabric_write32(uint8_t function, uint16_t reg, uint8_t instance_id, uint32_t data); diff --git a/src/soc/amd/glinda/include/soc/data_fabric.h b/src/soc/amd/glinda/include/soc/data_fabric.h index 5a1e77c..c0482ee 100644 --- a/src/soc/amd/glinda/include/soc/data_fabric.h +++ b/src/soc/amd/glinda/include/soc/data_fabric.h @@ -11,6 +11,7 @@ #define D18F0_MMIO_SHIFT 16 #define D18F0_MMIO_CTRL0 0xD88 +#define DF_MMIO_REG_SET_SIZE 4 #define DF_MMIO_REG_SET_COUNT 8 #define DF_FICAA_BIOS 0x8C diff --git a/src/soc/amd/mendocino/include/soc/data_fabric.h b/src/soc/amd/mendocino/include/soc/data_fabric.h index fc36b81..ad0fb37 100644 --- a/src/soc/amd/mendocino/include/soc/data_fabric.h +++ b/src/soc/amd/mendocino/include/soc/data_fabric.h @@ -11,6 +11,7 @@ #define D18F0_MMIO_SHIFT 16 #define D18F0_MMIO_CTRL0 0x208 +#define DF_MMIO_REG_SET_SIZE 4 #define DF_MMIO_REG_SET_COUNT 8 #define DF_FICAA_BIOS 0x5C diff --git a/src/soc/amd/phoenix/include/soc/data_fabric.h b/src/soc/amd/phoenix/include/soc/data_fabric.h index a983d54..77083b0 100644 --- a/src/soc/amd/phoenix/include/soc/data_fabric.h +++ b/src/soc/amd/phoenix/include/soc/data_fabric.h @@ -11,6 +11,7 @@ #define D18F0_MMIO_SHIFT 16 #define D18F0_MMIO_CTRL0 0xD88 +#define DF_MMIO_REG_SET_SIZE 4 #define DF_MMIO_REG_SET_COUNT 8 #define DF_FICAA_BIOS 0x8C diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h index 8a5725d..4446371 100644 --- a/src/soc/amd/picasso/include/soc/data_fabric.h +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -11,6 +11,7 @@ #define D18F0_MMIO_SHIFT 16 #define D18F0_MMIO_CTRL0 0x208 +#define DF_MMIO_REG_SET_SIZE 4 #define DF_MMIO_REG_SET_COUNT 8 #define DF_FICAA_BIOS 0x5C -- To view, visit https://review.coreboot.org/c/coreboot/+/72878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67420a2973c8ef9a7f0ce19ddc0013de69731689 Gerrit-Change-Number: 72878 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/amd/common/data_fabric: replace NB with DF prefix for DF registers
by Felix Held (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72877 ) Change subject: soc/amd/common/data_fabric: replace NB with DF prefix for DF registers ...................................................................... soc/amd/common/data_fabric: replace NB with DF prefix for DF registers Since the MMIO decode range registers in the data fabric are part of the data fabric and not of the northbridge, replace the NB prefix with a DF prefix to make this a bit clearer. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ife5e4581752825e9224b50252955d485a067af74 --- M src/soc/amd/common/block/data_fabric/data_fabric_helper.c M src/soc/amd/common/block/include/amdblocks/data_fabric.h 2 files changed, 36 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/72877/1 diff --git a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c index f3548fc..fe983ac 100644 --- a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c +++ b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c @@ -53,12 +53,12 @@ "=== Data Fabric MMIO configuration registers ===\n" "idx control base limit\n"); for (unsigned int i = 0; i < DF_MMIO_REG_SET_COUNT; i++) { - control = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); + control = data_fabric_broadcast_read32(0, DF_MMIO_CONTROL(i)); /* Base and limit address registers don't contain the lower address bits, but are shifted by D18F0_MMIO_SHIFT bits */ - base = (uint64_t)data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)) + base = (uint64_t)data_fabric_broadcast_read32(0, DF_MMIO_BASE(i)) << D18F0_MMIO_SHIFT; - limit = (uint64_t)data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i)) + limit = (uint64_t)data_fabric_broadcast_read32(0, DF_MMIO_LIMIT(i)) << D18F0_MMIO_SHIFT; /* Lower D18F0_MMIO_SHIFT address limit bits are all 1 */ limit += (1 << D18F0_MMIO_SHIFT) - 1; @@ -70,15 +70,15 @@ void data_fabric_disable_mmio_reg(unsigned int reg) { union df_mmio_control ctrl = { .fabric_id = IOMS0_FABRIC_ID }; - data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl.raw); - data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), 0); - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), 0); + data_fabric_broadcast_write32(0, DF_MMIO_CONTROL(reg), ctrl.raw); + data_fabric_broadcast_write32(0, DF_MMIO_BASE(reg), 0); + data_fabric_broadcast_write32(0, DF_MMIO_LIMIT(reg), 0); } static bool is_mmio_reg_disabled(unsigned int reg) { union df_mmio_control ctrl; - ctrl.raw = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(reg)); + ctrl.raw = data_fabric_broadcast_read32(0, DF_MMIO_CONTROL(reg)); return !(ctrl.we || ctrl.re); } @@ -124,12 +124,12 @@ for (i = 0; i < DF_MMIO_REG_SET_COUNT; i++) { /* Adjust all registers that overlap */ - ctrl.raw = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); + ctrl.raw = data_fabric_broadcast_read32(0, DF_MMIO_CONTROL(i)); if (!(ctrl.we || ctrl.re)) continue; /* not enabled */ - base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)); - limit = data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i)); + base = data_fabric_broadcast_read32(0, DF_MMIO_BASE(i)); + limit = data_fabric_broadcast_read32(0, DF_MMIO_LIMIT(i)); if (base > np_top || limit < np_bot) continue; /* no overlap at all */ @@ -141,7 +141,7 @@ if (base < np_bot && limit > np_top) { /* Split the configured region */ - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); + data_fabric_broadcast_write32(0, DF_MMIO_LIMIT(i), np_bot - 1); reg = data_fabric_find_unused_mmio_reg(); if (reg < 0) { /* Although a pair could be freed later, this condition is @@ -150,17 +150,17 @@ printk(BIOS_ERR, "Not enough NB MMIO routing registers\n"); continue; } - data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1); - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), limit); - data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl.raw); + data_fabric_broadcast_write32(0, DF_MMIO_BASE(reg), np_top + 1); + data_fabric_broadcast_write32(0, DF_MMIO_LIMIT(reg), limit); + data_fabric_broadcast_write32(0, DF_MMIO_CONTROL(reg), ctrl.raw); continue; } /* If still here, adjust only the base or limit */ if (base <= np_bot) - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); + data_fabric_broadcast_write32(0, DF_MMIO_LIMIT(i), np_bot - 1); else - data_fabric_broadcast_write32(0, NB_MMIO_BASE(i), np_top + 1); + data_fabric_broadcast_write32(0, DF_MMIO_BASE(i), np_top + 1); } reg = data_fabric_find_unused_mmio_reg(); @@ -171,9 +171,9 @@ union df_mmio_control np_ctrl = { .fabric_id = IOMS0_FABRIC_ID, .np = 1, .we = 1, .re = 1 }; - data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot); - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top); - data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), np_ctrl.raw); + data_fabric_broadcast_write32(0, DF_MMIO_BASE(reg), np_bot); + data_fabric_broadcast_write32(0, DF_MMIO_LIMIT(reg), np_top); + data_fabric_broadcast_write32(0, DF_MMIO_CONTROL(reg), np_ctrl.raw); data_fabric_print_mmio_conf(); } diff --git a/src/soc/amd/common/block/include/amdblocks/data_fabric.h b/src/soc/amd/common/block/include/amdblocks/data_fabric.h index 4f8dcd4..dd4b079 100644 --- a/src/soc/amd/common/block/include/amdblocks/data_fabric.h +++ b/src/soc/amd/common/block/include/amdblocks/data_fabric.h @@ -12,9 +12,9 @@ #define BROADCAST_FABRIC_ID 0xff /* The number of data fabric MMIO registers is SoC-specific */ -#define NB_MMIO_BASE(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_BASE0) -#define NB_MMIO_LIMIT(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_LIMIT0) -#define NB_MMIO_CONTROL(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_CTRL0) +#define DF_MMIO_BASE(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_BASE0) +#define DF_MMIO_LIMIT(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_LIMIT0) +#define DF_MMIO_CONTROL(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_CTRL0) uint32_t data_fabric_read32(uint8_t function, uint16_t reg, uint8_t instance_id); void data_fabric_write32(uint8_t function, uint16_t reg, uint8_t instance_id, uint32_t data); -- To view, visit https://review.coreboot.org/c/coreboot/+/72877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife5e4581752825e9224b50252955d485a067af74 Gerrit-Change-Number: 72877 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/*/data_fabric: rename define for MMIO decode register set count
by Felix Held (Code Review) 07 Feb '23

07 Feb '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72876 ) Change subject: soc/amd/*/data_fabric: rename define for MMIO decode register set count ...................................................................... soc/amd/*/data_fabric: rename define for MMIO decode register set count This should make it a bit clearer that those registers are in the data fabric configuration registers. Also move those defines right after the register definition those are related to. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ic107bd217f4af0a9ddfbe41aafd3c882aa968e22 --- M src/soc/amd/cezanne/include/soc/data_fabric.h M src/soc/amd/common/block/data_fabric/data_fabric_helper.c M src/soc/amd/glinda/include/soc/data_fabric.h M src/soc/amd/mendocino/include/soc/data_fabric.h M src/soc/amd/phoenix/include/soc/data_fabric.h M src/soc/amd/picasso/include/soc/data_fabric.h 6 files changed, 27 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/72876/1 diff --git a/src/soc/amd/cezanne/include/soc/data_fabric.h b/src/soc/amd/cezanne/include/soc/data_fabric.h index a1f8b70..8e5c278 100644 --- a/src/soc/amd/cezanne/include/soc/data_fabric.h +++ b/src/soc/amd/cezanne/include/soc/data_fabric.h @@ -11,14 +11,14 @@ #define D18F0_MMIO_SHIFT 16 #define D18F0_MMIO_CTRL0 0x208 +#define DF_MMIO_REG_SET_COUNT 8 + #define DF_FICAA_BIOS 0x5C #define DF_FICAD_LO 0x98 #define DF_FICAD_HI 0x9C #define IOMS0_FABRIC_ID 10 -#define NUM_NB_MMIO_REGS 8 - union df_mmio_control { struct { uint32_t re : 1; /* [ 0.. 0] */ diff --git a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c index b64edcd..f3548fc 100644 --- a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c +++ b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c @@ -52,7 +52,7 @@ printk(BIOS_SPEW, "=== Data Fabric MMIO configuration registers ===\n" "idx control base limit\n"); - for (unsigned int i = 0; i < NUM_NB_MMIO_REGS; i++) { + for (unsigned int i = 0; i < DF_MMIO_REG_SET_COUNT; i++) { control = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); /* Base and limit address registers don't contain the lower address bits, but are shifted by D18F0_MMIO_SHIFT bits */ @@ -84,7 +84,7 @@ int data_fabric_find_unused_mmio_reg(void) { - for (unsigned int i = 0; i < NUM_NB_MMIO_REGS; i++) { + for (unsigned int i = 0; i < DF_MMIO_REG_SET_COUNT; i++) { if (is_mmio_reg_disabled(i)) return i; } @@ -122,7 +122,7 @@ data_fabric_print_mmio_conf(); - for (i = 0; i < NUM_NB_MMIO_REGS; i++) { + for (i = 0; i < DF_MMIO_REG_SET_COUNT; i++) { /* Adjust all registers that overlap */ ctrl.raw = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); if (!(ctrl.we || ctrl.re)) diff --git a/src/soc/amd/glinda/include/soc/data_fabric.h b/src/soc/amd/glinda/include/soc/data_fabric.h index 7be4b15..5a1e77c 100644 --- a/src/soc/amd/glinda/include/soc/data_fabric.h +++ b/src/soc/amd/glinda/include/soc/data_fabric.h @@ -11,14 +11,14 @@ #define D18F0_MMIO_SHIFT 16 #define D18F0_MMIO_CTRL0 0xD88 +#define DF_MMIO_REG_SET_COUNT 8 + #define DF_FICAA_BIOS 0x8C #define DF_FICAD_LO 0xB8 #define DF_FICAD_HI 0xBC #define IOMS0_FABRIC_ID 15 -#define NUM_NB_MMIO_REGS 8 - union df_mmio_control { struct { uint32_t re : 1; /* [ 0.. 0] */ diff --git a/src/soc/amd/mendocino/include/soc/data_fabric.h b/src/soc/amd/mendocino/include/soc/data_fabric.h index ae5f267..fc36b81 100644 --- a/src/soc/amd/mendocino/include/soc/data_fabric.h +++ b/src/soc/amd/mendocino/include/soc/data_fabric.h @@ -11,14 +11,14 @@ #define D18F0_MMIO_SHIFT 16 #define D18F0_MMIO_CTRL0 0x208 +#define DF_MMIO_REG_SET_COUNT 8 + #define DF_FICAA_BIOS 0x5C #define DF_FICAD_LO 0x98 #define DF_FICAD_HI 0x9C #define IOMS0_FABRIC_ID 9 -#define NUM_NB_MMIO_REGS 8 - union df_mmio_control { struct { uint32_t re : 1; /* [ 0.. 0] */ diff --git a/src/soc/amd/phoenix/include/soc/data_fabric.h b/src/soc/amd/phoenix/include/soc/data_fabric.h index cdd9b1a..a983d54 100644 --- a/src/soc/amd/phoenix/include/soc/data_fabric.h +++ b/src/soc/amd/phoenix/include/soc/data_fabric.h @@ -11,14 +11,14 @@ #define D18F0_MMIO_SHIFT 16 #define D18F0_MMIO_CTRL0 0xD88 +#define DF_MMIO_REG_SET_COUNT 8 + #define DF_FICAA_BIOS 0x8C #define DF_FICAD_LO 0xB8 #define DF_FICAD_HI 0xBC #define IOMS0_FABRIC_ID 14 -#define NUM_NB_MMIO_REGS 8 - union df_mmio_control { struct { uint32_t re : 1; /* [ 0.. 0] */ diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h index dc77fee..8a5725d 100644 --- a/src/soc/amd/picasso/include/soc/data_fabric.h +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -11,14 +11,14 @@ #define D18F0_MMIO_SHIFT 16 #define D18F0_MMIO_CTRL0 0x208 +#define DF_MMIO_REG_SET_COUNT 8 + #define DF_FICAA_BIOS 0x5C #define DF_FICAD_LO 0x98 #define DF_FICAD_HI 0x9C #define IOMS0_FABRIC_ID 9 -#define NUM_NB_MMIO_REGS 8 - union df_mmio_control { struct { uint32_t re : 1; /* [ 0.. 0] */ -- To view, visit https://review.coreboot.org/c/coreboot/+/72876 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic107bd217f4af0a9ddfbe41aafd3c882aa968e22 Gerrit-Change-Number: 72876 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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