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Change subject: soc/amd/phoenix/cpu: use CPUID_ALL_STEPPINGS_MASK
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Patch Set 1: Code-Review+2
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Change subject: soc/amd/mendocino/cpu: use CPUID_ALL_STEPPINGS_MASK
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Change subject: soc/amd/cezanne: use CPUID_ALL_STEPPINGS_MASK to support all steppings
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Change subject: soc/amd/picasso/cpu: use CPUID_ALL_STEPPINGS_MASK
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Change subject: nb/intel/haswell/pcie.c: Make UBSAN shut up
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/72806/comment/f1c277ab_e04d7236
PS1, Line 7: nb/intel/haswell/pcie.c: Make UBSAN shut up
> Maybe: […]
Reluctant to use "fix" because this doesn't really fix much (behaviour remains unaffected)
https://review.coreboot.org/c/coreboot/+/72806/comment/a7710117_38784d63
PS1, Line 17:
> It’d be great if you added: […]
Done
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Hello Felix Singer, Nico Huber, Paul Menzel, Arthur Heymans,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/72806
to look at the new patch set (#3).
Change subject: nb/intel/haswell/pcie.c: Make UBSAN shut up
......................................................................
nb/intel/haswell/pcie.c: Make UBSAN shut up
UBSAN complains about "shift out of bounds", likely because integer
literals are signed by default and the result of the operation will
shift into the sign bit, yielding a negative value. However, as the
negative value is then casted to an unsigned type, it works anyway.
To make UBSAN happy, make sure the two troublesome integer literals
are unsigned so that there's no sign bit to shift into.
Tested on out-of-tree Asrock Z97 Extreme6, UBSAN now dies elsewhere.
Link: https://ticket.coreboot.org/issues/449
Change-Id: Iaf8710a5ae4e05d9f41f40f9e3617e155027800c
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/northbridge/intel/haswell/pcie.c
1 file changed, 23 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/72806/3
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Change subject: nb/intel/haswell/pcie.c: Make UBSAN shut up
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/72806/comment/09512455_c8e19671
PS1, Line 14: integer literals are unsigned so that the shift doesn't overflow.
> Ah, thanks for the explanation! Tried to rewrite the commit message factoring in this information, t […]
LGTM
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Change subject: arch/x86/cpu: introduce and use device_match_mask
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Patch Set 2: Code-Review+1
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Change subject: nb/intel/haswell/pcie.c: Make UBSAN shut up
......................................................................
Patch Set 1: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/72806/comment/7198dfc2_c65147c9
PS1, Line 7: nb/intel/haswell/pcie.c: Make UBSAN shut up
Maybe:
> nb/intel/haswell/pcie: Use unsigned integers to fix shift OOB
https://review.coreboot.org/c/coreboot/+/72806/comment/09c21840_b9506768
PS1, Line 17:
It’d be great if you added:
Link: https://ticket.coreboot.org/issues/449
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Change subject: nb/intel/haswell/pcie.c: Make UBSAN shut up
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/72806/comment/8deb87ec_8dbc691a
PS1, Line 10: and
: the result of the operation
> drop
Oops, thanks for spotting this
https://review.coreboot.org/c/coreboot/+/72806/comment/3d15b3c0_1985f794
PS1, Line 14: integer literals are unsigned so that the shift doesn't overflow.
> IIRC, the undefined part is shifting into the sign bit. Technically, […]
Ah, thanks for the explanation! Tried to rewrite the commit message factoring in this information, thoughts?
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