coreboot-gerrit February 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: nb/intel/haswell/pcie.c: Make UBSAN shut up
by Angel Pons (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Felix Singer, Angel Pons, Arthur Heymans. Hello Felix Singer, Nico Huber, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72806 to look at the new patch set (#2). Change subject: nb/intel/haswell/pcie.c: Make UBSAN shut up ...................................................................... nb/intel/haswell/pcie.c: Make UBSAN shut up UBSAN complains about "shift out of bounds", likely because integer literals are signed by default and the result of the operation will shift into the sign bit, yielding a negative value. However, as the negative value is then casted to an unsigned type, it works anyway. To make UBSAN happy, make sure the two troublesome integer literals are unsigned so that there's no sign bit to shift into. Tested on out-of-tree Asrock Z97 Extreme6, UBSAN now dies elsewhere. Change-Id: Iaf8710a5ae4e05d9f41f40f9e3617e155027800c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/pcie.c 1 file changed, 21 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/72806/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf8710a5ae4e05d9f41f40f9e3617e155027800c Gerrit-Change-Number: 72806 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: nb/intel/haswell/pcie.c: Make UBSAN shut up
by Nico Huber (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Felix Singer, Angel Pons, Arthur Heymans. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72806 ) Change subject: nb/intel/haswell/pcie.c: Make UBSAN shut up ...................................................................... Patch Set 1: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/72806/comment/206303c4_cd34acf4 PS1, Line 10: and : the result of the operation drop https://review.coreboot.org/c/coreboot/+/72806/comment/f1fe93ad_0adfd3a3 PS1, Line 14: integer literals are unsigned so that the shift doesn't overflow. IIRC, the undefined part is shifting into the sign bit. Technically, it's not specified in C that the MSB is the sign bit. It's just that all architectures and compilers happen to use a 2's complement representation. -- To view, visit https://review.coreboot.org/c/coreboot/+/72806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf8710a5ae4e05d9f41f40f9e3617e155027800c Gerrit-Change-Number: 72806 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 07 Feb 2023 14:44:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: ec/dell: Add support for the SMSC MEC5035
by Angel Pons (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Nicholas Chin, Felix Held, Elyes Haouas. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59703 ) Change subject: ec/dell: Add support for the SMSC MEC5035 ...................................................................... Patch Set 8: Code-Review+1 (1 comment) File src/ec/dell/mec5035/mec5035.c: https://review.coreboot.org/c/coreboot/+/59703/comment/81af08b1_10f09f3d PS8, Line 75: int Is this type correct? -- To view, visit https://review.coreboot.org/c/coreboot/+/59703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia420cd51e9a64be5eee4af2c0d113618575522b0 Gerrit-Change-Number: 59703 Gerrit-PatchSet: 8 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 07 Feb 2023 14:38:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: arch/x86/cpu: introduce and use device_match_mask
by Felix Held (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Jeff Daly, Sean Rhodes, Matt DeVillier, Jonathan Zhang, Johnny Lin, Christian Walter, Vanessa Eusebio, Arthur Heymans, Fred Reitberger, Tim Chu. Hello build bot (Jenkins), Jeff Daly, Raul Rangel, Jonathan Zhang, Matt DeVillier, Arthur Heymans, Jason Glenesk, Sean Rhodes, Johnny Lin, Christian Walter, Vanessa Eusebio, Fred Reitberger, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72847 to look at the new patch set (#2). Change subject: arch/x86/cpu: introduce and use device_match_mask ...................................................................... arch/x86/cpu: introduce and use device_match_mask Instead of always doing exact matches between the CPUID read in identify_cpu and the device entries of the CPU device ID table, offer the possibility to use a bit mask in the CPUID matching. This allows covering all steppings of a CPU family/model with one entry and avoids that case of a missing new stepping causing the CPUs not being properly initialized. Some of the CPU device ID tables can now be deduplicated using the CPUID_ALL_STEPPINGS_MASK define, but that's outside of the scope of this patch. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I0540b514ca42591c0d3468307a82b5612585f614 --- M src/arch/x86/cpu.c M src/arch/x86/include/arch/cpu.h M src/cpu/amd/pi/00730F01/model_16_init.c M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_106cx/model_106cx_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/model_65x/model_65x_init.c M src/cpu/intel/model_67x/model_67x_init.c M src/cpu/intel/model_68x/model_68x_init.c M src/cpu/intel/model_6bx/model_6bx_init.c M src/cpu/intel/model_6ex/model_6ex_init.c M src/cpu/intel/model_6fx/model_6fx_init.c M src/cpu/intel/model_6xx/model_6xx_init.c M src/cpu/intel/model_f2x/model_f2x_init.c M src/cpu/intel/model_f3x/model_f3x_init.c M src/cpu/intel/model_f4x/model_f4x_init.c M src/cpu/qemu-x86/qemu.c M src/soc/amd/cezanne/cpu.c M src/soc/amd/glinda/cpu.c M src/soc/amd/mendocino/cpu.c M src/soc/amd/phoenix/cpu.c M src/soc/amd/picasso/cpu.c M src/soc/amd/stoneyridge/cpu.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/skx/cpu.c 32 files changed, 244 insertions(+), 202 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/72847/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0540b514ca42591c0d3468307a82b5612585f614 Gerrit-Change-Number: 72847 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: arch/x86/include/cpu: retype device field in cpu_device_id
by Felix Held (Code Review) 07 Feb '23

07 Feb '23

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72846 to look at the new patch set (#2). Change subject: arch/x86/include/cpu: retype device field in cpu_device_id ...................................................................... arch/x86/include/cpu: retype device field in cpu_device_id Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ic54f73dcd3496a5ad85291b9b9586bc740b734d5 --- M src/arch/x86/include/arch/cpu.h 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/72846/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic54f73dcd3496a5ad85291b9b9586bc740b734d5 Gerrit-Change-Number: 72846 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[4.19_branch]: nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw
by Angel Pons (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Bill XIE. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72763 ) Change subject: nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.19_branch Gerrit-Change-Id: I83e735707cd9ff30aa339443593239cd7e3e4656 Gerrit-Change-Number: 72763 Gerrit-PatchSet: 4 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Comment-Date: Tue, 07 Feb 2023 14:29:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/haswell/pcie.c: Make UBSAN shut up
by Angel Pons (Code Review) 07 Feb '23

07 Feb '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72806 ) Change subject: nb/intel/haswell/pcie.c: Make UBSAN shut up ...................................................................... nb/intel/haswell/pcie.c: Make UBSAN shut up UBSAN complains about "shift out of bounds", likely because integer literals are signed by default, and the result of the operation and the result of the operation would be a negative value (although the negative value is then casted to an unsigned type, which results in the expected value anyway). To make UBSAN happy, make sure that two integer literals are unsigned so that the shift doesn't overflow. Tested on out-of-tree Asrock Z97 Extreme6, UBSAN now dies elsewhere. Change-Id: Iaf8710a5ae4e05d9f41f40f9e3617e155027800c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/pcie.c 1 file changed, 21 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/72806/1 diff --git a/src/northbridge/intel/haswell/pcie.c b/src/northbridge/intel/haswell/pcie.c index e8d146b..7fe57e9 100644 --- a/src/northbridge/intel/haswell/pcie.c +++ b/src/northbridge/intel/haswell/pcie.c @@ -82,7 +82,7 @@ uint32_t slotcap = pci_read_config32(dev, PEG_SLOTCAP); /* Physical slot number (zero for ports connected to onboard devices) */ - slotcap &= ~(0x1fff << 19); + slotcap &= ~(0x1fffU << 19); if (slot_implemented) { uint16_t slot_number = peg_cfg->phys_slot_number & 0x1fff; if (slot_number == 0) { @@ -124,7 +124,7 @@ /* Select -3.5 dB de-emphasis */ pci_or_config32(dev, PEG_LCTL2, 1 << 6); - pci_or_config32(dev, PEG_L0SLAT, 1 << 31); + pci_or_config32(dev, PEG_L0SLAT, 1U << 31); pci_update_config32(dev, 0x250, ~(7 << 20), 2 << 20); -- To view, visit https://review.coreboot.org/c/coreboot/+/72806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf8710a5ae4e05d9f41f40f9e3617e155027800c Gerrit-Change-Number: 72806 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/xeon_sp/chip_common.c: check SOC_INTEL_PCIE_64BIT_ALLOC
by Johnny Lin (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Jonathan Zhang, David Hendricks, Christian Walter, Arthur Heymans, Elyes Haouas, Tim Chu. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72441 ) Change subject: soc/intel/xeon_sp/chip_common.c: check SOC_INTEL_PCIE_64BIT_ALLOC ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/xeon_sp/chip_common.c: https://review.coreboot.org/c/coreboot/+/72441/comment/d63ee06c_03bfd127 PS6, Line 410: #if > why "#if"? […] line 414 PlatformData.Pci64BitResourceAllocation may not be defined by platforms selecting SOC_INTEL_PCIE_64BIT_ALLOC, by using C will see build error: src/soc/intel/xeon_sp/chip_common.c:414:33: error: 'PLATFORM_DATA' has no member named 'Pci64BitResourceAllocation' 414 | return hob->PlatformData.Pci64BitResourceAllocation; So C preprocessor is needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/72441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic33967255baf4675cd72e0db32ef3fb7f5658296 Gerrit-Change-Number: 72441 Gerrit-PatchSet: 6 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 07 Feb 2023 14:11:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix/include/cpu: rename CPUID define to match CPU model
by Fred Reitberger (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72843 ) Change subject: soc/amd/phoenix/include/cpu: rename CPUID define to match CPU model ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7500130d5470fdd824980b81746f3a0f6d277d4 Gerrit-Change-Number: 72843 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 07 Feb 2023 14:11:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: acpi/acpigen.h: Fix EVENT_OP value
by Felix Held (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Elyes Haouas. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72805 ) Change subject: acpi/acpigen.h: Fix EVENT_OP value ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c531e95f4fc741926bc883d869816f534ff3b7f Gerrit-Change-Number: 72805 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 07 Feb 2023 14:01:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit February 2023