coreboot-gerrit December 2023

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[L] Change in coreboot[main]: acpi: Add PPTT support
by Lean Sheng Tan (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Angel Pons, Cliff Huang, David Milosevic, Lance Zhao, Martin L Roth, Maximilian Brune, Nico Huber, Patrick Rudolph, Tim Wawrzynczak. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78071?usp=email ) Change subject: acpi: Add PPTT support ...................................................................... Patch Set 23: (1 comment) Patchset: PS23: give +2 as Nico also reviewed and approved it. -- To view, visit https://review.coreboot.org/c/coreboot/+/78071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Gerrit-Change-Number: 78071 Gerrit-PatchSet: 23 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Fri, 01 Dec 2023 18:28:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: acpi: Add PPTT support
by Lean Sheng Tan (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Angel Pons, Cliff Huang, David Milosevic, Lance Zhao, Martin L Roth, Maximilian Brune, Nico Huber, Patrick Rudolph, Tim Wawrzynczak. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78071?usp=email ) Change subject: acpi: Add PPTT support ...................................................................... Patch Set 23: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Gerrit-Change-Number: 78071 Gerrit-PatchSet: 23 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Fri, 01 Dec 2023 18:28:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: acpi: Add PPTT support
by Arthur Heymans (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Angel Pons, Cliff Huang, David Milosevic, Lance Zhao, Martin L Roth, Maximilian Brune, Nico Huber, Patrick Rudolph, Tim Wawrzynczak. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78071?usp=email ) Change subject: acpi: Add PPTT support ...................................................................... Patch Set 23: Code-Review+2 (1 comment) File src/acpi/acpi_pptt.c: https://review.coreboot.org/c/coreboot/+/78071/comment/afe38fa7_b2ce477a : PS21, Line 148: cpu_node->resources[cpu_node->n_resources++] = new_pptt_cache(current, it->cache, cache_list); > Considered doing that. Not sure anymore why exactly, but I decided against it. I think the current solution is fine. You'd need to loop through the topology twice to achieve that. Once to get all the cache references, then a second time to generate CPU entries. This is fine. -- To view, visit https://review.coreboot.org/c/coreboot/+/78071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Gerrit-Change-Number: 78071 Gerrit-PatchSet: 23 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Fri, 01 Dec 2023 18:11:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/emulation/qemu-sbsa: Generate PPTT ACPI table
by Arthur Heymans (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: David Milosevic. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79108?usp=email ) Change subject: mb/emulation/qemu-sbsa: Generate PPTT ACPI table ...................................................................... Patch Set 3: (4 comments) File src/mainboard/emulation/qemu-sbsa/pptt.c: https://review.coreboot.org/c/coreboot/+/79108/comment/9ed4e0f4_5022cd3f : PS3, Line 16: struct static for all of these caches, resources & topology. Also move these inside the acpi_get_pptt_topology function. A global scope is not needed when static is used as that ensures the lifetime. https://review.coreboot.org/c/coreboot/+/79108/comment/34280a6b_100264f5 : PS3, Line 17: remove all the newlines when declaring structs. https://review.coreboot.org/c/coreboot/+/79108/comment/dbf3733a_98f4ad82 : PS3, Line 65: /* : * 'write-policy' and 'allocation type' currently : * unsupported. As a nice example for real hardware, it would be good to set a meaningful value, rather than leave it 0? https://review.coreboot.org/c/coreboot/+/79108/comment/689eb75b_7d9924d3 : PS3, Line 130: *it = malloc(sizeof(struct pptt_topology)) There have been quite a few patches finetuning the heap. As you don't give that heap back to the OS and and it needs to be sufficiently large anyway can you just statically allocate a buffer large enough for CONFIG_MAX_CPUS? That avoids this runtime check too. The following code snippet works btw: struct device *cur = dev_find_path(NULL, DEVICE_PATH_GICC_V3); struct device *next = NULL; static struct pptt_topology entries[CONFIG_MAX_CPUS] = {}; root_topology.child = entries; for (int i = 0; i < CONFIG_MAX_CPUS; i++) { if (!cur) { break; } struct pptt_topology *entry = &entries[i]; entry->processor_id = i; entry->flags.raw = CORE_FLAGS; entry->resources = &core_resources; next = dev_find_path(cur, DEVICE_PATH_GICC_V3); if (next) entry->sibling = &entries[i + 1]; cur = next; } return &root_topology; -- To view, visit https://review.coreboot.org/c/coreboot/+/79108?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabeb138c1257488bcb364fe7b522f02c041745e2 Gerrit-Change-Number: 79108 Gerrit-PatchSet: 3 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Fri, 01 Dec 2023 18:05:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: inteltool: improve support for Elkhart Lake
by Alexander Couzens (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Pratikkumar V Prajapati. Alexander Couzens has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75214?usp=email ) Change subject: inteltool: improve support for Elkhart Lake ...................................................................... Patch Set 5: (2 comments) File util/inteltool/inteltool.h: https://review.coreboot.org/c/coreboot/+/75214/comment/b3520d55_f03c714a : PS5, Line 338: #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_1 0x4514 replace this by coreboot's own version of it. https://review.coreboot.org/c/coreboot/+/75214/comment/8e45a56b_254931c8 : PS5, Line 487: #define PCI_DEVICE_ID_INTEL_EHL_GT1_2 0x4551 same -- To view, visit https://review.coreboot.org/c/coreboot/+/75214?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida852f3c991cdd036d9c282f9cabceb23c765e25 Gerrit-Change-Number: 75214 Gerrit-PatchSet: 5 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Fri, 01 Dec 2023 17:50:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: superio/smsc: Add support for the SCH555x series
by Felix Held (Code Review) 01 Dec '23

01 Dec '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64359?usp=email ) Change subject: superio/smsc: Add support for the SCH555x series ...................................................................... superio/smsc: Add support for the SCH555x series Used by the OptiPlex 3020/7020/9020: - EMI and Runtime registers work - UART1 works (including IRQs) - PS/2 keyboard and mouse untested Signed-off-by: Mate Kukri <kukri.mate(a)gmail.com> Change-Id: I9323198f1139cd0c3dd37f977ae7693b721654f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64359 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/superio/smsc/Makefile.inc A src/superio/smsc/sch555x/Kconfig A src/superio/smsc/sch555x/Makefile.inc A src/superio/smsc/sch555x/bootblock.c A src/superio/smsc/sch555x/emi.c A src/superio/smsc/sch555x/ramstage.c A src/superio/smsc/sch555x/sch555x.h 7 files changed, 329 insertions(+), 0 deletions(-) Approvals: Martin L Roth: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index 86cf9c5..b5e79ba 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -13,3 +13,4 @@ subdirs-y += smscsuperio subdirs-y += sio1036 subdirs-y += sch5545 +subdirs-y += sch555x diff --git a/src/superio/smsc/sch555x/Kconfig b/src/superio/smsc/sch555x/Kconfig new file mode 100644 index 0000000..6375857 --- /dev/null +++ b/src/superio/smsc/sch555x/Kconfig @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config SUPERIO_SMSC_SCH555x + bool diff --git a/src/superio/smsc/sch555x/Makefile.inc b/src/superio/smsc/sch555x/Makefile.inc new file mode 100644 index 0000000..047fb5c --- /dev/null +++ b/src/superio/smsc/sch555x/Makefile.inc @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-$(CONFIG_SUPERIO_SMSC_SCH555x) += emi.c bootblock.c +ramstage-$(CONFIG_SUPERIO_SMSC_SCH555x) += ramstage.c diff --git a/src/superio/smsc/sch555x/bootblock.c b/src/superio/smsc/sch555x/bootblock.c new file mode 100644 index 0000000..bae6e64 --- /dev/null +++ b/src/superio/smsc/sch555x/bootblock.c @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/io.h> +#include <device/pnp_ops.h> +#include "sch555x.h" + +static void pnp_enter_conf_state(pnp_devfn_t dev) +{ + unsigned int port = dev >> 8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(pnp_devfn_t dev) +{ + unsigned int port = dev >> 8; + outb(0xaa, port); +} + +static void pnp_write_config32(pnp_devfn_t dev, uint8_t offset, uint32_t value) +{ + pnp_write_config(dev, offset, value & 0xff); + pnp_write_config(dev, offset + 1, (value >> 8) & 0xff); + pnp_write_config(dev, offset + 2, (value >> 16) & 0xff); + pnp_write_config(dev, offset + 3, (value >> 24) & 0xff); +} + +/* + * Do just enough init so that the motherboard specific magic EMI + * sequences can be sent before sch555x_enable_serial is called + */ +void sch555x_early_init(pnp_devfn_t global_dev) +{ + pnp_enter_conf_state(global_dev); + + // Enable IRQs + pnp_set_logical_device(global_dev); + pnp_write_config(global_dev, SCH555x_DEVICE_MODE, 0x04); + + // Map EMI and runtime registers + pnp_devfn_t lpci_dev = PNP_DEV(global_dev >> 8, SCH555x_LDN_LPCI); + + pnp_set_logical_device(lpci_dev); + pnp_write_config32(lpci_dev, SCH555x_LPCI_EMI_BAR, + (SCH555x_EMI_IOBASE << 16) | 0x800f); + pnp_write_config32(lpci_dev, SCH555x_LPCI_RUNTIME_BAR, + (SCH555x_RUNTIME_IOBASE << 16) | 0x8a3f); + + pnp_exit_conf_state(global_dev); +} + +void sch555x_enable_serial(pnp_devfn_t uart_dev, uint16_t serial_iobase) +{ + pnp_enter_conf_state(uart_dev); + + // Set LPCI BAR register to map UART into I/O space + pnp_devfn_t lpci_dev = PNP_DEV(uart_dev >> 8, SCH555x_LDN_LPCI); + + pnp_set_logical_device(lpci_dev); + u8 uart_bar = (uart_dev & 0xff) == SCH555x_LDN_UART1 + ? SCH555x_LPCI_UART1_BAR + : SCH555x_LPCI_UART2_BAR; + pnp_write_config32(lpci_dev, uart_bar, serial_iobase << 16 | 0x8707); + + // Set up the UART's configuration registers + pnp_set_logical_device(uart_dev); + pnp_set_enable(uart_dev, 1); // Activate + pnp_write_config(uart_dev, 0x0f, 0x02); // Config select + + pnp_exit_conf_state(uart_dev); +} diff --git a/src/superio/smsc/sch555x/emi.c b/src/superio/smsc/sch555x/emi.c new file mode 100644 index 0000000..7b3b204 --- /dev/null +++ b/src/superio/smsc/sch555x/emi.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/io.h> +#include <device/pnp_ops.h> +#include "sch555x.h" + +uint8_t sch555x_emi_read8(uint16_t addr) +{ + outw(addr | 0x8000, SCH555x_EMI_IOBASE + 2); + return inb(SCH555x_EMI_IOBASE + 4); +} + +uint16_t sch555x_emi_read16(uint16_t addr) +{ + outw(addr | 0x8001, SCH555x_EMI_IOBASE + 2); + return inw(SCH555x_EMI_IOBASE + 4); +} + +uint32_t sch555x_emi_read32(uint16_t addr) +{ + outw(addr | 0x8002, SCH555x_EMI_IOBASE + 2); + return inl(SCH555x_EMI_IOBASE + 4); +} + +void sch555x_emi_write8(uint16_t addr, uint8_t val) +{ + outw(addr | 0x8000, SCH555x_EMI_IOBASE + 2); + outb(val, SCH555x_EMI_IOBASE + 4); +} + +void sch555x_emi_write16(uint16_t addr, uint16_t val) +{ + outw(addr | 0x8001, SCH555x_EMI_IOBASE + 2); + outw(val, SCH555x_EMI_IOBASE + 4); +} + +void sch555x_emi_write32(uint16_t addr, uint32_t val) +{ + outw(addr | 0x8002, SCH555x_EMI_IOBASE + 2); + outl(val, SCH555x_EMI_IOBASE + 4); +} diff --git a/src/superio/smsc/sch555x/ramstage.c b/src/superio/smsc/sch555x/ramstage.c new file mode 100644 index 0000000..2245001 --- /dev/null +++ b/src/superio/smsc/sch555x/ramstage.c @@ -0,0 +1,141 @@ +;;/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <superio/conf_mode.h> +#include "sch555x.h" + +static void sch555x_init(struct device *dev) +{ + if (dev->enabled && dev->path.pnp.device == SCH555x_LDN_8042) + pc_keyboard_init(NO_AUX_DEVICE); +} + +static uint8_t sch555x_ldn_to_bar(uint8_t ldn) +{ + switch (ldn) { + case SCH555x_LDN_LPCI: + return SCH555x_LPCI_LPCI_BAR; + case SCH555x_LDN_EMI: + return SCH555x_LPCI_EMI_BAR; + case SCH555x_LDN_UART1: + return SCH555x_LPCI_UART1_BAR; + case SCH555x_LDN_UART2: + return SCH555x_LPCI_UART2_BAR; + case SCH555x_LDN_RUNTIME: + return SCH555x_LPCI_RUNTIME_BAR; + case SCH555x_LDN_8042: + return SCH555x_LPCI_8042_BAR; + case SCH555x_LDN_FDC: + return SCH555x_LPCI_FDC_BAR; + case SCH555x_LDN_PP: + return SCH555x_LPCI_PP_BAR; + default: + return 0; + } +} + +/* + * IO BARs don't live in normal LDN configuration space but in the LPC interface. + * Thus we ignore the index and choose what BAR to set just based on the LDN. + */ +static void sch555x_set_iobase(struct device *lpci, struct device *dev, + uint8_t index, uint16_t iobase) +{ + const uint8_t bar = sch555x_ldn_to_bar(dev->path.pnp.device); + if (bar) { + pnp_set_logical_device(lpci); + pnp_unset_and_set_config(lpci, bar + 1, 0, 1 << 7); + pnp_write_config(lpci, bar + 2, iobase & 0xff); + pnp_write_config(lpci, bar + 3, (iobase >> 8) & 0xff); + } +} + +/* + * IRQs don't live in normal LDN configuration space but in the LPC interface. + * + * The following fake offsets are used: + * 0x70 => First IRQ + * 0x72 => Second IRQ + */ +static void sch555x_set_irq(struct device *lpci, struct device *dev, + uint8_t index, uint8_t irq) +{ + if (index >= PNP_IDX_MSC0) { + pnp_set_logical_device(dev); + pnp_write_config(dev, index, irq); + return; + } + + pnp_set_logical_device(lpci); + switch (index) { + case 0x70: + pnp_write_config(lpci, SCH555x_LPCI_IRQ(irq), dev->path.pnp.device); + break; + case 0x72: + pnp_write_config(lpci, SCH555x_LPCI_IRQ(irq), dev->path.pnp.device | 0x80); + break; + } +} + +/* + * DMA channels don't live in normal LDN configuration space but in the LPC interface. + */ +static void sch555x_set_drq(struct device *lpci, struct device *dev, + uint8_t index, uint8_t drq) +{ + pnp_set_logical_device(lpci); + pnp_write_config(lpci, SCH555x_LPCI_DMA(drq), dev->path.pnp.device | 0x80); +} + +static void sch555x_set_resources(struct device *dev) +{ + struct device *lpci = dev_find_slot_pnp(dev->path.pnp.port, SCH555x_LDN_LPCI); + if (!lpci) { + printk(BIOS_ERR, "SCH555x LPC interface not present in device tree!\n"); + return; + } + + pnp_enter_conf_mode(dev); + for (struct resource *res = dev->resource_list; res; res = res->next) { + if (res->flags & IORESOURCE_IO) + sch555x_set_iobase(lpci, dev, res->index, res->base); + else if (res->flags & IORESOURCE_DRQ) + sch555x_set_drq(lpci, dev, res->index, res->base); + else if (res->flags & IORESOURCE_IRQ) + sch555x_set_irq(lpci, dev, res->index, res->base); + } + pnp_exit_conf_mode(dev); +} + +static void sch555x_enable_dev(struct device *dev) +{ + static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = sch555x_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = sch555x_init, + .ops_pnp_mode = &pnp_conf_mode_55_aa, + }; + + static struct pnp_info pnp_dev_info[] = { + { NULL, SCH555x_LDN_EMI, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x0ff0 }, + { NULL, SCH555x_LDN_8042, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x0fff }, + { NULL, SCH555x_LDN_UART1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8 }, + { NULL, SCH555x_LDN_UART2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8 }, + { NULL, SCH555x_LDN_LPCI, PNP_IO0, 0x0ffe }, + { NULL, SCH555x_LDN_RUNTIME, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x0fc0 }, + { NULL, SCH555x_LDN_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, }, + { NULL, SCH555x_LDN_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8 }, + }; + + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_smsc_sch555x_ops = { + CHIP_NAME("SMSC SCH555x Super I/O") + .enable_dev = sch555x_enable_dev, +}; diff --git a/src/superio/smsc/sch555x/sch555x.h b/src/superio/smsc/sch555x/sch555x.h new file mode 100644 index 0000000..4af95ec --- /dev/null +++ b/src/superio/smsc/sch555x/sch555x.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SUPERIO_SCH555x_H +#define SUPERIO_SCH555x_H + +#include <types.h> + +// Global registers +#define SCH555x_DEVICE_ID 0x20 +#define SCH555x_DEVICE_REV 0x21 +#define SCH555x_DEVICE_MODE 0x24 + +// Logical device numbers +#define SCH555x_LDN_EMI 0x00 +#define SCH555x_LDN_8042 0x01 +#define SCH555x_LDN_UART1 0x07 +#define SCH555x_LDN_UART2 0x08 +#define SCH555x_LDN_RUNTIME 0x0a +#define SCH555x_LDN_FDC 0x0b +#define SCH555x_LDN_LPCI 0x0c +#define SCH555x_LDN_PP 0x11 +#define SCH555x_LDN_GLOBAL 0x3f + +// LPC interface registers +#define SCH555x_LPCI_IRQ(i) (0x40 + (i)) +// DMA channel register is 2 bytes, we care about the second byte +#define SCH555x_LPCI_DMA(i) (0x50 + (i) * 2 + 1) +// BAR offset (inside LPCI) for each LDN +#define SCH555x_LPCI_LPCI_BAR 0x60 +#define SCH555x_LPCI_EMI_BAR 0x64 +#define SCH555x_LPCI_UART1_BAR 0x68 +#define SCH555x_LPCI_UART2_BAR 0x6c +#define SCH555x_LPCI_RUNTIME_BAR 0x70 +#define SCH555x_LPCI_8042_BAR 0x78 +#define SCH555x_LPCI_FDC_BAR 0x7c +#define SCH555x_LPCI_PP_BAR 0x80 + +// Runtime registers (in I/O space) +#define SCH555x_RUNTIME_PME_STS 0x00 +#define SCH555x_RUNTIME_PME_EN 0x01 +#define SCH555x_RUNTIME_PME_EN1 0x05 +#define SCH555x_RUNTIME_LED 0x25 +// NOTE: not in the SCH5627P datasheet but Dell's firmware writes to it +#define SCH555x_RUNTIME_UNK1 0x35 + +// Needed in the bootblock, thus we map them at a fixed address +#define SCH555x_EMI_IOBASE 0xa00 +#define SCH555x_RUNTIME_IOBASE 0xa40 + +/* + * EMI access + */ + +uint8_t sch555x_emi_read8(uint16_t addr); +uint16_t sch555x_emi_read16(uint16_t addr); +uint32_t sch555x_emi_read32(uint16_t addr); +void sch555x_emi_write8(uint16_t addr, uint8_t val); +void sch555x_emi_write16(uint16_t addr, uint16_t val); +void sch555x_emi_write32(uint16_t addr, uint32_t val); + +/* + * Bootblock entry points + */ + +void sch555x_early_init(pnp_devfn_t global_dev); +void sch555x_enable_serial(pnp_devfn_t uart_dev, uint16_t serial_iobase); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/64359?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9323198f1139cd0c3dd37f977ae7693b721654f4 Gerrit-Change-Number: 64359 Gerrit-PatchSet: 5 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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[XL] Change in coreboot[main]: mb/emulation: Add SIMICS QSP support
by Leon Groß (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Paul Menzel. Leon Groß has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77905?usp=email ) Change subject: mb/emulation: Add SIMICS QSP support ...................................................................... Patch Set 16: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/77905/comment/0777eca8_134015fa : PS9, Line 20: > Intel provides some documentation as part of the Slim Bootloader project: https://slimbootloader. […] Now I see what kind of documentation you are interested in. I provided some documentation for downloading Simics and booting a coreboot build. -- To view, visit https://review.coreboot.org/c/coreboot/+/77905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I175b20bb4746608e4d868aa96492fc06c149bd36 Gerrit-Change-Number: 77905 Gerrit-PatchSet: 16 Gerrit-Owner: Leon Groß <leon.gross(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 01 Dec 2023 17:29:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Leon Groß <leon.gross(a)9elements.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: vc/amd/psp: Remove unknown section flags
by Zebreus (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79366?usp=email to look at the new patch set (#2). Change subject: vc/amd/psp: Remove unknown section flags ...................................................................... vc/amd/psp: Remove unknown section flags The `d` flag used in .section is unknown in LLVM/clang 17 and fails the build. It is also not documented in the ARM compiler manual. The GNU assembler supports the `d` flag but it also seems to compile without. I am not sure what the flag is supposed to do and if it is okay to remove it. ARM compiler manual: https://developer.arm.com/documentation/101754/0621/armclang-Reference/armc… GNU compiler manual: https://sourceware.org/binutils/docs/as/Section.html Change-Id: Ie3735b72349b0cfdd27364a39bcdda390af7bfa5 Signed-off-by: Lennart Eichhorn <lennarteichhorn(a)googlemail.com> --- M src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_end.S M src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_end.S M src/vendorcode/amd/fsp/mendocino/bl_uapp/bl_uapp_end.S M src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_end.S 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/79366/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79366?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie3735b72349b0cfdd27364a39bcdda390af7bfa5 Gerrit-Change-Number: 79366 Gerrit-PatchSet: 2 Gerrit-Owner: Zebreus <lennarteichhorn(a)googlemail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[main]: mb/emulation: Add SIMICS QSP support
by Leon Groß (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Lean Sheng Tan, Leon Groß, Nico Huber, Patrick Rudolph, Paul Menzel. Hello Angel Pons, Arthur Heymans, Benjamin Doron, Christian Walter, Lean Sheng Tan, Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77905?usp=email to look at the new patch set (#16). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/emulation: Add SIMICS QSP support ...................................................................... mb/emulation: Add SIMICS QSP support SIMICS Quick Start Platform (QSP) is weird. It doesn't implement a single X58 register besides DEVID/VENID. Likely because those are never used by an OS. Not so good for firmware development. ICH10 seems to be more properly implemented. Working: - Boots to EDK2 payload (payloads/external/edk2) - TSEG works, ASEG is broken - Graphics init works Signed-off-by: Leon Gross <leon.gross(a)9elements.com> Change-Id: I175b20bb4746608e4d868aa96492fc06c149bd36 --- A Documentation/mainboard/emulation/simics-qsp.md M src/cpu/qemu-x86/Kconfig A src/mainboard/emulation/simics-qsp/Kconfig A src/mainboard/emulation/simics-qsp/Kconfig.name A src/mainboard/emulation/simics-qsp/Makefile.inc A src/mainboard/emulation/simics-qsp/acpi.h A src/mainboard/emulation/simics-qsp/acpi_tables.c A src/mainboard/emulation/simics-qsp/board_info.txt A src/mainboard/emulation/simics-qsp/bootblock.c A src/mainboard/emulation/simics-qsp/cmos.default A src/mainboard/emulation/simics-qsp/cmos.layout A src/mainboard/emulation/simics-qsp/cpu.c A src/mainboard/emulation/simics-qsp/devicetree.cb A src/mainboard/emulation/simics-qsp/dsdt.asl A src/mainboard/emulation/simics-qsp/exit_car.S A src/mainboard/emulation/simics-qsp/hda_verb.c A src/mainboard/emulation/simics-qsp/mainboard.c A src/mainboard/emulation/simics-qsp/memmap.c A src/mainboard/emulation/simics-qsp/memory.h A src/mainboard/emulation/simics-qsp/northbridge.c A src/mainboard/emulation/simics-qsp/romstage.c A src/mainboard/emulation/simics-qsp/simics.h A src/mainboard/emulation/simics-qsp/vboot-rwa-16M.fmd A src/mainboard/emulation/simics-qsp/vboot-rwab-16M.fmd M src/southbridge/intel/i82801jx/Kconfig 25 files changed, 1,285 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/77905/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/77905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I175b20bb4746608e4d868aa96492fc06c149bd36 Gerrit-Change-Number: 77905 Gerrit-PatchSet: 16 Gerrit-Owner: Leon Groß <leon.gross(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Leon Groß <leon.gross(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: vc/amd/psp: Remove unknown section flags
by Zebreus (Code Review) 01 Dec '23

01 Dec '23

Zebreus has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79366?usp=email ) Change subject: vc/amd/psp: Remove unknown section flags ...................................................................... vc/amd/psp: Remove unknown section flags The `d` flag used in .section is unknown in LLVM/clang 17 and fails the build. It is also not documented in the ARM compiler manual. The GNU assembler supports the `d` flag but it also seems to compile without. I am not sure what the flag is supposed to do and if it is okay to remove it. ARM compiler manual: https://developer.arm.com/documentation/101754/0621/armclang-Reference/armc… GNU compiler manual: https://sourceware.org/binutils/docs/as/Section.html Change-Id: Ie3735b72349b0cfdd27364a39bcdda390af7bfa5 Signed-off-by: Lennart Eichhorn <lennarteichhorn(a)googlemail.com> --- M src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_end.S M src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_end.S M src/vendorcode/amd/fsp/mendocino/bl_uapp/bl_uapp_end.S M src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_end.S 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/79366/1 diff --git a/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_end.S b/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_end.S index 40ea411..db6556c 100644 --- a/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_end.S +++ b/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_end.S @@ -29,7 +29,7 @@ .arm .global LastBytes -.section PSP_FOOTER_DATA, "ad", %note +.section PSP_FOOTER_DATA, "a", %note .balign 64 // Note: this is used for determining the size of the binary. It is 64 byte aligned and 64 byte diff --git a/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_end.S b/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_end.S index 40ea411..db6556c 100644 --- a/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_end.S +++ b/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_end.S @@ -29,7 +29,7 @@ .arm .global LastBytes -.section PSP_FOOTER_DATA, "ad", %note +.section PSP_FOOTER_DATA, "a", %note .balign 64 // Note: this is used for determining the size of the binary. It is 64 byte aligned and 64 byte diff --git a/src/vendorcode/amd/fsp/mendocino/bl_uapp/bl_uapp_end.S b/src/vendorcode/amd/fsp/mendocino/bl_uapp/bl_uapp_end.S index 40ea411..db6556c 100644 --- a/src/vendorcode/amd/fsp/mendocino/bl_uapp/bl_uapp_end.S +++ b/src/vendorcode/amd/fsp/mendocino/bl_uapp/bl_uapp_end.S @@ -29,7 +29,7 @@ .arm .global LastBytes -.section PSP_FOOTER_DATA, "ad", %note +.section PSP_FOOTER_DATA, "a", %note .balign 64 // Note: this is used for determining the size of the binary. It is 64 byte aligned and 64 byte diff --git a/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_end.S b/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_end.S index 40ea411..db6556c 100644 --- a/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_end.S +++ b/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_end.S @@ -29,7 +29,7 @@ .arm .global LastBytes -.section PSP_FOOTER_DATA, "ad", %note +.section PSP_FOOTER_DATA, "a", %note .balign 64 // Note: this is used for determining the size of the binary. It is 64 byte aligned and 64 byte -- To view, visit https://review.coreboot.org/c/coreboot/+/79366?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie3735b72349b0cfdd27364a39bcdda390af7bfa5 Gerrit-Change-Number: 79366 Gerrit-PatchSet: 1 Gerrit-Owner: Zebreus <lennarteichhorn(a)googlemail.com> Gerrit-MessageType: newchange

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