coreboot-gerrit December 2023

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[XS] Change in coreboot[main]: acpi/acpi: update ACPI_DBG2_PORT_SERIAL_16550 subtype
by Felix Held (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Cliff Huang, Lance Zhao, Matt DeVillier, Raul Rangel, Tim Wawrzynczak. Hello Cliff Huang, Lance Zhao, Matt DeVillier, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79219?usp=email to look at the new patch set (#4). Change subject: acpi/acpi: update ACPI_DBG2_PORT_SERIAL_16550 subtype ...................................................................... acpi/acpi: update ACPI_DBG2_PORT_SERIAL_16550 subtype The Microsoft Debug Port Table 2 (DBG2) specification says that the serial port subtype 0x00 should only be used for I/O-mapped 16550 compatible UARTs. The subtype 0x12 is a superset of that, and supports specifying MMIO vs IO and the register access size via the generic address structure. Rename the subtype 0x00 definition to ACPI_DBG2_PORT_SERIAL_16550_IO_ONLY and add the subtype 0x12 definition as new ACPI_DBG2_PORT_SERIAL_16550, so that the acpi_write_dbg2_uart function will write the correct subtype for the generic 16550 UART. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I816bb22e6f76e661c8b8e39a2a4cb83b0085acb5 --- M src/include/acpi/acpi.h 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/79219/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/79219?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I816bb22e6f76e661c8b8e39a2a4cb83b0085acb5 Gerrit-Change-Number: 79219 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: Update amd_blobs submodule to upstream main branch
by Jason Glenesk (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Matt DeVillier. Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79365?usp=email ) Change subject: Update amd_blobs submodule to upstream main branch ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79365?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifd2ca49a472c516c69c9f43ed4dc3faefd8729d8 Gerrit-Change-Number: 79365 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 01 Dec 2023 15:43:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/brox: Fix memory config
by Nick Vaccaro (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Karthik Ramasubramanian, Shelley Chen. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79355?usp=email ) Change subject: mb/google/brox: Fix memory config ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brox/variants/baseboard/brox/gpio.c: https://review.coreboot.org/c/coreboot/+/79355/comment/906431d9_16e5e9d6 : PS3, Line 404: const struct pad_config *__weak variant_romstage_gpio_table(size_t *num) : { > I am afraid the weak override here will be overridden by the table here - https://review.coreboot. […] This table and weak declaration should remain here, but Karthik is correct that this will get overridden by the definition in variants/brox/gpio.c when on a brox reference platform variant. Therefor, you need to make sure that the GPIOs in the romstage_gpio_table in this file are also in the rom_gpio_table in variants/brox/gpio.c. Do you feel that the GPIOs in the romstage_gpio_table in variant/brox/gpio.c would not be common to many brox variants? If they are likely to be common, those gpios should be added to the romstage_gpio_table in this file. -- To view, visit https://review.coreboot.org/c/coreboot/+/79355?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I17615cda7df10e73e49fb49f736728787ef7625d Gerrit-Change-Number: 79355 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 01 Dec 2023 15:41:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Update amd_blobs submodule to upstream main branch
by Felix Held (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Matt DeVillier. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79365?usp=email ) Change subject: Update amd_blobs submodule to upstream main branch ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79365?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifd2ca49a472c516c69c9f43ed4dc3faefd8729d8 Gerrit-Change-Number: 79365 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 01 Dec 2023 15:40:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/amd: Add DBG2 ACPI table
by Felix Held (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Bao Zheng, Cliff Huang, Fred Reitberger, Jason Glenesk, Lance Zhao, Matt DeVillier, Raul Rangel, Simon Glass, Tim Wawrzynczak, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79174?usp=email ) Change subject: soc/amd: Add DBG2 ACPI table ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79174?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c97a78d1889549421baf0bc1a2e8f959a0f47e2 Gerrit-Change-Number: 79174 Gerrit-PatchSet: 12 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Simon Glass <sjg(a)chromium.org> Gerrit-Comment-Date: Fri, 01 Dec 2023 15:38:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Update amd_blobs submodule to upstream main branch
by Matt DeVillier (Code Review) 01 Dec '23

01 Dec '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79365?usp=email ) Change subject: Update amd_blobs submodule to upstream main branch ...................................................................... Update amd_blobs submodule to upstream main branch Updating from commit id eb91266f01db (2023-11-29): MDN: Update mendocino SMU to 90.43.0 to commit id 64cdd7c8ef19 (2023-12-01): Cezanne/PSP: clean up release notes This brings in 3 new commits: 64cdd7c8ef Cezanne/PSP: clean up release notes 54c45443b8 Stoneyridge: Drop PSP binaries for Bristol Ridge (BR) bfa3c44c8c Stoneyridge: Tidy up the PSP binaries folder Change-Id: Ifd2ca49a472c516c69c9f43ed4dc3faefd8729d8 Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M 3rdparty/amd_blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/79365/1 diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index eb91266..64cdd7c 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit eb91266f01db2d276614dc20d8d0f857e6ffbf00 +Subproject commit 64cdd7c8ef199f5d79be14e7972fb7316f41beed -- To view, visit https://review.coreboot.org/c/coreboot/+/79365?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifd2ca49a472c516c69c9f43ed4dc3faefd8729d8 Gerrit-Change-Number: 79365 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: acpi/acpi: add & use ACPI_DBG2_PORT_SERIAL_16550_GENERIC
by Felix Held (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Cliff Huang, Lance Zhao, Matt DeVillier, Raul Rangel, Tim Wawrzynczak. Hello Cliff Huang, Lance Zhao, Matt DeVillier, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79219?usp=email to look at the new patch set (#3). Change subject: acpi/acpi: add & use ACPI_DBG2_PORT_SERIAL_16550_GENERIC ...................................................................... acpi/acpi: add & use ACPI_DBG2_PORT_SERIAL_16550_GENERIC The Microsoft Debug Port Table 2 (DBG2) specification says that the serial port subtype 0x00 should only be used for I/O-mapped 16550 compatible UARTs. The subtype 0x12 is a superset of that, and supports specifying MMIO vs IO and the register access size via the generic address structure. Rename the subtype 0x00 definition to ACPI_DBG2_PORT_SERIAL_16550_IO_ONLY and add the subtype 0x12 definition as new ACPI_DBG2_PORT_SERIAL_16550, so that the acpi_write_dbg2_uart function will write the correct subtype for the generic 16550 UART. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I816bb22e6f76e661c8b8e39a2a4cb83b0085acb5 --- M src/include/acpi/acpi.h 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/79219/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79219?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I816bb22e6f76e661c8b8e39a2a4cb83b0085acb5 Gerrit-Change-Number: 79219 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/brya/var/dochi: Update overridetree for type c1
by Felix Held (Code Review) 01 Dec '23

01 Dec '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79343?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/brya/var/dochi: Update overridetree for type c1 ...................................................................... mb/google/brya/var/dochi: Update overridetree for type c1 Update overridetree to correct AUX pin to USB-C port 3 BUG=b:299570339 TEST=emerge-brya coreboot chromeos-bootimage Change-Id: I3a5a89c6008fbf28c927f83060e6e508d60845ba Signed-off-by: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79343 Reviewed-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/dochi/overridetree.cb 1 file changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved David Wu: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/dochi/overridetree.cb b/src/mainboard/google/brya/variants/dochi/overridetree.cb index cc74f8d..19ace7b 100644 --- a/src/mainboard/google/brya/variants/dochi/overridetree.cb +++ b/src/mainboard/google/brya/variants/dochi/overridetree.cb @@ -18,14 +18,14 @@ # SOC Aux orientation override: # This is a bitfield that corresponds to up to 4 TCSS ports. - # Bits (0,1) allocated for TCSS Port1 configuration, Bits (2,3)for TCSS Port2. - # TcssAuxOri = 0101b - # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports, otherwise is "0" - # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the + # Bits (0,1) allocated for TCSS Port1 configuration, Bits (4,5)for TCSS Port3. + # TcssAuxOri = 010001b + # Bit0,Bit4 set to "1" indicates no retimer on USBC Ports, otherwise is "0" + # Bit1,Bit5 set to "0" indicates Aux lines are not swapped on the # motherboard to USBC connector - register "tcss_aux_ori" = "0x5" + register "tcss_aux_ori" = "0x11" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" - register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" + register "typec_aux_bias_pads[2]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port 1 register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2 Port 3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a5a89c6008fbf28c927f83060e6e508d60845ba Gerrit-Change-Number: 79343 Gerrit-PatchSet: 3 Gerrit-Owner: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: arch/riscv/payload: Replace old RISC-V CSR names with their values
by Zebreus (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Philipp Hug, ron minnich. Hello Philipp Hug, build bot (Jenkins), ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79364?usp=email to look at the new patch set (#2). Change subject: arch/riscv/payload: Replace old RISC-V CSR names with their values ...................................................................... arch/riscv/payload: Replace old RISC-V CSR names with their values LLVM/clang 17 removed support for CSR names that are no longer included in the RISC-V ISA Manual Privileged Specification since version 1.12. Instead we now use the numerical values they represent directly. These magic numbers can not be defined in macros because they will not get expanded. Related LLVM commit: https://reviews.llvm.org/D149278 Change-Id: I7c8f2a06a109333f95230bf0a3056c8d5c8a9132 Signed-off-by: Lennart Eichhorn <lennarteichhorn(a)googlemail.com> --- M src/arch/riscv/payload.c 1 file changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/79364/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79364?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c8f2a06a109333f95230bf0a3056c8d5c8a9132 Gerrit-Change-Number: 79364 Gerrit-PatchSet: 2 Gerrit-Owner: Zebreus <lennarteichhorn(a)googlemail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: arch/riscv/payload: Replace old RISC-V CSR names with their values
by Zebreus (Code Review) 01 Dec '23

01 Dec '23

Zebreus has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79364?usp=email ) Change subject: arch/riscv/payload: Replace old RISC-V CSR names with their values ...................................................................... arch/riscv/payload: Replace old RISC-V CSR names with their values LLVM/clang 17 removed support for CSR names that are no longer included in the RISC-V ISA Manual Privileged Specification since version 1.12. Instead we now use the numerical values they represent directly. These magic numbers can not be defined in macros because they will not get expanded. Related LLVM commit: https://reviews.llvm.org/D149278 Change-Id: I7c8f2a06a109333f95230bf0a3056c8d5c8a9132 Signed-off-by: Zebreus <lennarteichhorn(a)googlemail.com> --- M src/arch/riscv/payload.c 1 file changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/79364/1 diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c index 3097ad1..1cbf50a 100644 --- a/src/arch/riscv/payload.c +++ b/src/arch/riscv/payload.c @@ -41,10 +41,12 @@ switch (payload_mode) { case RISCV_PAYLOAD_MODE_U: status = INSERT_FIELD(status, MSTATUS_MPP, PRV_U); - /* Trap vector base address point to the payload */ - write_csr(utvec, doit); - /* disable U-Mode interrupt */ - write_csr(uie, 0); + /* Trap vector base address point to the payload + 0x0005 is the User trap handler base address register. */ + write_csr(0x0005, doit); + /* disable U-Mode interrupt + 0x0004 is the User interrupt-enable register. */ + write_csr(0x0004, 0); break; case RISCV_PAYLOAD_MODE_S: status = INSERT_FIELD(status, MSTATUS_MPP, PRV_S); -- To view, visit https://review.coreboot.org/c/coreboot/+/79364?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c8f2a06a109333f95230bf0a3056c8d5c8a9132 Gerrit-Change-Number: 79364 Gerrit-PatchSet: 1 Gerrit-Owner: Zebreus <lennarteichhorn(a)googlemail.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2023