coreboot-gerrit December 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: util/docker/rocky: Add Dockerfile.base
by Felix Singer (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Martin L Roth. Hello Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79384?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: util/docker/rocky: Add Dockerfile.base ...................................................................... util/docker/rocky: Add Dockerfile.base Change-Id: I60e00932332801c0f62d88b7860afb330d9469e4 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- A util/docker/rocky/Dockerfile.base 1 file changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/79384/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79384?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60e00932332801c0f62d88b7860afb330d9469e4 Gerrit-Change-Number: 79384 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: util/docker/fedora: Add initial Dockerfile
by Felix Singer (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Martin L Roth. Hello Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79316?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: util/docker/fedora: Add initial Dockerfile ...................................................................... util/docker/fedora: Add initial Dockerfile Change-Id: I8d04c570f91215f534f173db2ae559b64b58012f Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- A util/docker/fedora/Dockerfile.base 1 file changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/79316/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/79316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d04c570f91215f534f173db2ae559b64b58012f Gerrit-Change-Number: 79316 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: acpi: Add PPTT support
by David Milosevic (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Angel Pons, Arthur Heymans, Cliff Huang, David Milosevic, Lance Zhao, Martin L Roth, Maximilian Brune, Nico Huber, Patrick Rudolph, Tim Wawrzynczak. Hello Arthur Heymans, Cliff Huang, Lance Zhao, Maximilian Brune, Nico Huber, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78071?usp=email to look at the new patch set (#23). The following approvals got outdated and were removed: Code-Review+1 by Nico Huber, Verified+1 by build bot (Jenkins) Change subject: acpi: Add PPTT support ...................................................................... acpi: Add PPTT support This patch adds code to generate Processor Properties Topology Tables (PPTT) compliant to the ACPI 6.4 specification. - The 'acpi_get_pptt_topology' hook is mandatory once ACPI_PPTT is selected. Its purpose is to return a pointer to a topology tree, which describes the relationship between CPUs and caches. The hook can be provided by, for example, mainboard code. Background: We are currently working on mainboard code for qemu-sbsa and Neoverse N2. Both require a valid PPTT table. Patch was tested against the qemu-sbsa board. Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> --- M src/acpi/Kconfig M src/acpi/Makefile.inc M src/acpi/acpi.c A src/acpi/acpi_pptt.c M src/include/acpi/acpi.h 5 files changed, 324 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/78071/23 -- To view, visit https://review.coreboot.org/c/coreboot/+/78071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Gerrit-Change-Number: 78071 Gerrit-PatchSet: 23 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: Trim GPIO comments
by Felix Held (Code Review) 01 Dec '23

01 Dec '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79321?usp=email ) Change subject: mb/google/nissa/var/anraggar: Trim GPIO comments ...................................................................... mb/google/nissa/var/anraggar: Trim GPIO comments Trim all GPIO comments like "origin ==> current". BUG=b:304920262 TEST=pass building Change-Id: I05daa4df16b6da3d3f971b75c7c467032e3f854d Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79321 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/anraggar/gpio.c 1 file changed, 13 insertions(+), 13 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/anraggar/gpio.c b/src/mainboard/google/brya/variants/anraggar/gpio.c index bc9e89d..8e0b76b 100644 --- a/src/mainboard/google/brya/variants/anraggar/gpio.c +++ b/src/mainboard/google/brya/variants/anraggar/gpio.c @@ -14,16 +14,16 @@ /* A18 : NC ==> HDMI_HPD_SRC*/ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), - /* A20 : DDSP_HPD2 ==> EC_SOC_HDMI_HPD ==> NC */ + /* A20 : DDSP_HPD2 ==> NC */ PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG), - /* A21 : GPP_A21 ==> USB_C1_AUX_DC_P ==> NC */ + /* A21 : GPP_A21 ==> NC */ PAD_NC_LOCK(GPP_A21, NONE, LOCK_CONFIG), - /* A22 : GPP_A22 ==> USB_C1_AUX_DC_N ==> NC */ + /* A22 : GPP_A22 ==> NC */ PAD_NC_LOCK(GPP_A22, NONE, LOCK_CONFIG), - /* B5 : I2C2_SDA ==> SOC_I2C_SUB_SDA ==> MIPI_WCAM_SDA */ + /* B5 : I2C2_SDA ==> MIPI_WCAM_SDA */ PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG), - /* B6 : I2C2_SCL ==> SOC_I2C_SUB_SCL ==> MIPI_WCAM_SCL */ + /* B6 : I2C2_SCL ==> MIPI_WCAM_SCL */ PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG), /* B11 : NC ==> EN_PP3300_WLAN_X*/ @@ -31,14 +31,14 @@ /* D6 : NC ==> WWAN_PWR_ENABLE */ PAD_CFG_GPO(GPP_D6, 1, DEEP), - /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL ==> NC */ + /* D8 : SRCCLKREQ3# ==> NC */ PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG), /* D13 : NC ==> EN_PP1800_WCAM_X */ PAD_CFG_GPO_LOCK(GPP_D13, 1, LOCK_CONFIG), - /* E20 : DDP2_CTRLCLK ==> HDMI_DDC_SCL ==> NC */ + /* E20 : DDP2_CTRLCLK ==> NC */ PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG), - /* E21 : DDP2_CTRLDATA ==> HDMI_DDC_SDA_STRAP ==> GPP_E21_STRAP */ + /* E21 : DDP2_CTRLDATA ==> GPP_E21_STRAP */ PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG), /* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */ @@ -52,22 +52,22 @@ PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), /* F18 : THC1_SPI2_INT# ==> EN_PP2800_AFVDD */ PAD_CFG_GPO(GPP_F18, 0, DEEP), - /* F23 : V1P05_CTRL ==> V1P05EXT_CTRL ==> NC*/ + /* F23 : V1P05_CTRL ==> NC*/ PAD_NC_LOCK(GPP_F23, NONE, LOCK_CONFIG), - /* H12 : UART0_RTS# ==> SD_PERST_L ==> NC*/ + /* H12 : UART0_RTS# ==> NC*/ PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), - /* H13 : UART0_CTS# ==> EN_PP3300_SD_X ==> NC */ + /* H13 : UART0_CTS# ==> NC */ PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG), /* H15 : DDPB_CTRLCLK ==> HDMI_DDC_SCL */ PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), /* H17 : DDPB_CTRLDATA ==> HDMI_DDC_SDA */ PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), - /* R6 : DMIC_CLK_A_1A ==> DMIC_WCAM_CLK_R ==> NC */ + /* R6 : DMIC_CLK_A_1A ==> NC */ PAD_NC_LOCK(GPP_R6, NONE, LOCK_CONFIG), - /* R7 : DMIC_DATA_1A ==> DMIC_WCAM_DATA ==> NC */ + /* R7 : DMIC_DATA_1A ==> NC */ PAD_NC_LOCK(GPP_R7, NONE, LOCK_CONFIG), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/79321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I05daa4df16b6da3d3f971b75c7c467032e3f854d Gerrit-Change-Number: 79321 Gerrit-PatchSet: 2 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/nissa/var/anraggar: Fix the GPP_D6 for LTE power.
by Felix Held (Code Review) 01 Dec '23

01 Dec '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79166?usp=email ) ( 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/nissa/var/anraggar: Fix the GPP_D6 for LTE power. ...................................................................... mb/google/nissa/var/anraggar: Fix the GPP_D6 for LTE power. Fix GPP_D6 configuration for LTE power enable. BUG=b:304920262 TEST=mmcli -m any Change-Id: I2996fd35c2897269997bc0290e0ce93bbbaa1bf8 Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79166 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/anraggar/gpio.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Dolan Liu: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/anraggar/gpio.c b/src/mainboard/google/brya/variants/anraggar/gpio.c index 40505bd..bc9e89d 100644 --- a/src/mainboard/google/brya/variants/anraggar/gpio.c +++ b/src/mainboard/google/brya/variants/anraggar/gpio.c @@ -29,6 +29,8 @@ /* B11 : NC ==> EN_PP3300_WLAN_X*/ PAD_CFG_GPO(GPP_B11, 0, DEEP), + /* D6 : NC ==> WWAN_PWR_ENABLE */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL ==> NC */ PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG), /* D13 : NC ==> EN_PP1800_WCAM_X */ -- To view, visit https://review.coreboot.org/c/coreboot/+/79166?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2996fd35c2897269997bc0290e0ce93bbbaa1bf8 Gerrit-Change-Number: 79166 Gerrit-PatchSet: 9 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/nissa/var/anraggar: Fix Type-C & DP functions
by Felix Held (Code Review) 01 Dec '23

01 Dec '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79165?usp=email ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/nissa/var/anraggar: Fix Type-C & DP functions ...................................................................... mb/google/nissa/var/anraggar: Fix Type-C & DP functions Due to TCPC0 & TCPC1 exchanged compare to Neried design, but related USB2 Ports not exchanged. BUG=b:304920262 TEST=Tpye-C & DP functions workable Change-Id: I9dacf06b1e672575a684856acdb10b6c88360b18 Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79165 Reviewed-by: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/anraggar/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Dolan Liu: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb index 5308317..b4b1659 100644 --- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb +++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb @@ -366,8 +366,8 @@ end device ref pch_espi on chip ec/google/chromeec - use conn0 as mux_conn[0] - use conn1 as mux_conn[1] + use conn0 as mux_conn[1] + use conn1 as mux_conn[0] device pnp 0c09.0 on end end end @@ -375,12 +375,12 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - use usb2_port1 as usb2_port + use usb2_port2 as usb2_port use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - use usb2_port2 as usb2_port + use usb2_port1 as usb2_port use tcss_usb3_port2 as usb3_port device generic 1 alias conn1 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/79165?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9dacf06b1e672575a684856acdb10b6c88360b18 Gerrit-Change-Number: 79165 Gerrit-PatchSet: 8 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: Enable ILITEK touchscreen
by Felix Held (Code Review) 01 Dec '23

01 Dec '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79164?usp=email ) Change subject: mb/google/nissa/var/anraggar: Enable ILITEK touchscreen ...................................................................... mb/google/nissa/var/anraggar: Enable ILITEK touchscreen For proto PCB: GPP_C0 for enable power supply which also for sensor subsystem. GPP_C0 must allways turn power on, so GPP_C6 is not only used for enable function but also for stop report. BUG=b:304920262 TEST=1. touchscreen function workable 2. INT pin no active during suspend Change-Id: I7dabf205dba616f57ef9717f950eba96282d8e3d Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79164 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/anraggar/gpio.c M src/mainboard/google/brya/variants/anraggar/overridetree.cb 2 files changed, 8 insertions(+), 3 deletions(-) Approvals: Dolan Liu: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/anraggar/gpio.c b/src/mainboard/google/brya/variants/anraggar/gpio.c index b01bc2c..40505bd 100644 --- a/src/mainboard/google/brya/variants/anraggar/gpio.c +++ b/src/mainboard/google/brya/variants/anraggar/gpio.c @@ -71,6 +71,11 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* C0 : SMBCLK ==> EN_PP3300_TCHSCR_X */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> TCHSCR_RST_L */ + PAD_CFG_GPO(GPP_C1, 1, DEEP), + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_H20, 0, DEEP), /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb index 30c3c1b..5308317 100644 --- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb +++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb @@ -221,10 +221,10 @@ register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" register "generic.reset_delay_ms" = "200" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C6)" register "generic.enable_delay_ms" = "12" - register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C6)" - register "generic.stop_off_delay_ms" = "2" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "200" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 41 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/79164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7dabf205dba616f57ef9717f950eba96282d8e3d Gerrit-Change-Number: 79164 Gerrit-PatchSet: 7 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/amd/common: Move PCIe CLKREQ programming under fsp
by Felix Held (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79016?usp=email ) Change subject: soc/amd/common: Move PCIe CLKREQ programming under fsp ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: > most of that code is fsp-agnostic; the main thing that's not fsp-agnostic is how that code gets the […] while this code isn't really fsp-specific, this will likely only be needed in the fsp use case. while i push for getting more things done in open source code, moving the gpp clk configuration out of fsp was probably not worth the trouble it has caused so far, since this is quite intertwined with the dxio init code. the function that gets moved here, fixes up the config in the devicetree so that it'll be valid for the dxio configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/79016?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I87b53d092ddc367b134c25949f9da7670a6a1d88 Gerrit-Change-Number: 79016 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 01 Dec 2023 16:29:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Update amd_blobs submodule to upstream main branch
by Varshit Pandya (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Matt DeVillier. Varshit Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79365?usp=email ) Change subject: Update amd_blobs submodule to upstream main branch ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79365?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifd2ca49a472c516c69c9f43ed4dc3faefd8729d8 Gerrit-Change-Number: 79365 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 01 Dec 2023 16:06:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: acpi/acpi: update ACPI_DBG2_PORT_SERIAL_16550 subtype
by Matt DeVillier (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Cliff Huang, Felix Held, Lance Zhao, Raul Rangel, Tim Wawrzynczak. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79219?usp=email ) Change subject: acpi/acpi: update ACPI_DBG2_PORT_SERIAL_16550 subtype ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79219?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I816bb22e6f76e661c8b8e39a2a4cb83b0085acb5 Gerrit-Change-Number: 79219 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 01 Dec 2023 15:53:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2023