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Change subject: soc/intel/xeon_sp: Redesign resource allocation
......................................................................
Patch Set 3:
(1 comment)
File src/device/pci_device.c:
https://review.coreboot.org/c/coreboot/+/78327/comment/b704e742_23f731ab :
PS3, Line 613: .set_resources = pci_domain_set_resources,
Does this change affect all boards, and should it be a separate commit ordered before?
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Change subject: soc/intel/xeon_sp: Redesign resource allocation
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Patch Set 3: Code-Review+1
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Hello Christian Walter, David Hendricks, Johnny Lin, Nill Ge, Shuo Liu, TangYiwei, Tim Chu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/xeon_sp: Redesign resource allocation
......................................................................
soc/intel/xeon_sp: Redesign resource allocation
The xeon_sp code worked around the coreboot allocator rather than using
it. Now the allocator is able to deal with the multiple IIOs so this is
not necessary anymore.
Instead do the following:
- Parse the FSP HOB information about IIO into coreboot PCI domains
- Use existing scan_bus and read_resource
- When a stack contains multiple host bridges as sometimes the case for
DINO stacks, add host bridges for each bus.
TEST: See that all resources are properly allocated on intel/archercity.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1
---
M src/device/pci_device.c
M src/include/device/device.h
M src/soc/intel/xeon_sp/acpi.c
M src/soc/intel/xeon_sp/chip_common.c
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/cpx/soc_util.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/include/soc/util.h
M src/soc/intel/xeon_sp/memmap.c
M src/soc/intel/xeon_sp/skx/chip.c
M src/soc/intel/xeon_sp/skx/soc_util.c
M src/soc/intel/xeon_sp/spr/chip.c
M src/soc/intel/xeon_sp/spr/soc_util.c
M src/soc/intel/xeon_sp/util.c
14 files changed, 172 insertions(+), 534 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/78327/3
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Change subject: soc/intel/xeon_sp: Redesign resource allocation
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Patch Set 2:
(1 comment)
File src/soc/intel/xeon_sp/spr/chip.c:
https://review.coreboot.org/c/coreboot/+/78327/comment/b6f75332_3a515377 :
PS2, Line 51: noop_set_resources
> in our setting, pci_domain_set_resources is needed here.
Done
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Change subject: soc/amd: Add DBG2 ACPI table
......................................................................
Patch Set 12:
(1 comment)
File src/soc/amd/common/block/acpi/tables.c:
https://review.coreboot.org/c/coreboot/+/79174/comment/a84a67f3_0b734b32 :
PS10, Line 15: current = acpi_16550_mmio32_write_dbg2_uart(rsdp, current,
> Use a regular `if`, not a `#if`
Done
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