coreboot-gerrit December 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: soc/amd/stoney/northbridge: Remove dead code
by Arthur Heymans (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Felix Held, Matt DeVillier. Hello Felix Held, Matt DeVillier, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79385?usp=email to look at the new patch set (#2). Change subject: soc/amd/stoney/northbridge: Remove dead code ...................................................................... soc/amd/stoney/northbridge: Remove dead code All the resource on the host bridge are fixed resources and therefore have the IORESOURCE_STORED flag set, so the body of this function which configures IO or MEM ranges is never reached. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I1839f030a4a365e5bc1cdaa3cf37cdf9ca382ff8 --- M src/soc/amd/stoneyridge/northbridge.c 1 file changed, 0 insertions(+), 74 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/79385/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79385?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1839f030a4a365e5bc1cdaa3cf37cdf9ca382ff8 Gerrit-Change-Number: 79385 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/amd/stoney/northbridge: Remove dead code
by Arthur Heymans (Code Review) 01 Dec '23

01 Dec '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79385?usp=email ) Change subject: soc/amd/stoney/northbridge: Remove dead code ...................................................................... soc/amd/stoney/northbridge: Remove dead code All the resource on the host bridge are fixed resources and therefore have the IORESOURCE_STORED flag set, so the body of this function which configures IO or MEM ranges is never reached. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I1839f030a4a365e5bc1cdaa3cf37cdf9ca382ff8 --- M src/soc/amd/stoneyridge/northbridge.c 1 file changed, 0 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/79385/1 diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 1e601cf..cc42321 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -30,31 +30,6 @@ #include "chip.h" -static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, - u32 io_min, u32 io_max) -{ - u32 tempreg; - - /* io range allocation. Limit */ - tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) - | ((io_max & 0xf0) << (12 - 4)); - pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg); - tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); /* base: ISA and VGA ? */ - pci_write_config32(SOC_ADDR_DEV, reg, tempreg); -} - -static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, - u32 mmio_min, u32 mmio_max) -{ - u32 tempreg; - - /* io range allocation. Limit */ - tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00); - pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg); - tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00); - pci_write_config32(SOC_ADDR_DEV, reg, tempreg); -} - static void read_resources(struct device *dev) { unsigned int idx = 0; @@ -73,50 +48,6 @@ mmio_range(dev, idx++, IO_APIC2_ADDR, 0x1000); } -static void set_resource(struct device *dev, struct resource *res, u32 nodeid) -{ - resource_t rbase, rend; - unsigned int reg, link_num; - char buf[50]; - - /* Make certain the resource has actually been set */ - if (!(res->flags & IORESOURCE_ASSIGNED)) - return; - - /* If I have already stored this resource don't worry about it */ - if (res->flags & IORESOURCE_STORED) - return; - - /* Only handle PCI memory and IO resources */ - if (!(res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) - return; - - /* Ensure I am actually looking at a resource of function 1 */ - if ((res->index & 0xffff) < 0x1000) - return; - - /* Get the base address */ - rbase = res->base; - - /* Get the limit (rounded up) */ - rend = resource_end(res); - - /* Get the register and link */ - reg = res->index & 0xfff; /* 4k */ - link_num = IOINDEX_LINK(res->index); - - if (res->flags & IORESOURCE_IO) - set_io_addr_reg(dev, nodeid, link_num, reg, rbase >> 8, rend >> 8); - else if (res->flags & IORESOURCE_MEM) - set_mmio_addr_reg(nodeid, link_num, reg, - (res->index >> 24), rbase >> 8, rend >> 8); - - res->flags |= IORESOURCE_STORED; - snprintf(buf, sizeof(buf), " <node %x link %x>", - nodeid, link_num); - report_resource_stored(dev, res, buf); -} - /** * I tried to reuse the resource allocation code in set_resource() * but it is too difficult to deal with the resource allocation magic. @@ -149,10 +80,6 @@ /* do we need this? */ create_vga_resource(dev); - /* Set each resource we have found */ - for (res = dev->resource_list ; res ; res = res->next) - set_resource(dev, res, 0); - for (bus = dev->link_list ; bus ; bus = bus->next) if (bus->children) assign_resources(bus); -- To view, visit https://review.coreboot.org/c/coreboot/+/79385?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1839f030a4a365e5bc1cdaa3cf37cdf9ca382ff8 Gerrit-Change-Number: 79385 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation
by Arthur Heymans (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Christian Walter, David Hendricks, Felix Held, Nico Huber, Nill Ge, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email ) Change subject: soc/intel/xeon_sp: Redesign resource allocation ...................................................................... Patch Set 4: (2 comments) Patchset: PS4: > Did the change-id change? I seem to remember a much longer review. CB:67020 I don't remember why. Maybe I messed up with the move to main from master? My bad... File src/device/pci_device.c: https://review.coreboot.org/c/coreboot/+/78327/comment/c5b5caab_73b31e52 : PS3, Line 613: .set_resources = pci_domain_set_resources, > It's an odd function anyway. I wonder why we don't always descend but leave > it to the device driver. It's a good idea for a follow-up -- To view, visit https://review.coreboot.org/c/coreboot/+/78327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 Gerrit-Change-Number: 78327 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 01 Dec 2023 14:20:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: util/docker/rocky: Add Dockerfile.base
by Felix Singer (Code Review) 01 Dec '23

01 Dec '23

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79384?usp=email ) Change subject: util/docker/rocky: Add Dockerfile.base ...................................................................... util/docker/rocky: Add Dockerfile.base Change-Id: I60e00932332801c0f62d88b7860afb330d9469e4 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- A util/docker/rocky/Dockerfile.base 1 file changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/79384/1 diff --git a/util/docker/rocky/Dockerfile.base b/util/docker/rocky/Dockerfile.base new file mode 100644 index 0000000..275db6b --- /dev/null +++ b/util/docker/rocky/Dockerfile.base @@ -0,0 +1,43 @@ +FROM rockylinux:9 + +RUN \ + echo "install_weak_deps=False" >> /etc/dnf/dnf.conf && \ + dnf update -y && \ + dnf install -y epel-release 'dnf-command(config-manager)' && \ + dnf config-manager --set-enabled epel && \ + dnf config-manager --set-enabled epel-testing && \ + dnf config-manager --set-enabled crb && \ + rpm --import /etc/pki/rpm-gpg/RPM-GPG-KEY-EPEL-9 && \ + dnf update -y && \ + dnf install -y \ + bash-completion \ + bison \ + bzip2 \ + ccache \ + cmake \ + cscope \ + diffutils \ + dtc \ + flex \ + gcc-c++ \ + git \ + go \ + htop \ + lcov \ + less \ + make \ + meson \ + ncurses-devel \ + neovim \ +# nss-pkcs11-devel \ + openssl-devel \ + patch \ + perl-English \ + perl-FindBin \ + perl-Hash-Util \ + perl-Sys-Hostname \ + shellcheck \ + tmux \ + xz \ + zlib-devel && \ + dnf install -y --repo epel-testing gcc-gnat -- To view, visit https://review.coreboot.org/c/coreboot/+/79384?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60e00932332801c0f62d88b7860afb330d9469e4 Gerrit-Change-Number: 79384 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation
by Nico Huber (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Felix Held, Nill Ge, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email ) Change subject: soc/intel/xeon_sp: Redesign resource allocation ...................................................................... Patch Set 4: (2 comments) Patchset: PS4: Did the change-id change? I seem to remember a much longer review. File src/device/pci_device.c: https://review.coreboot.org/c/coreboot/+/78327/comment/18b4ac53_f50c994d : PS3, Line 613: .set_resources = pci_domain_set_resources, > Acknowledged It's an odd function anyway. I wonder why we don't always descend but leave it to the device driver. -- To view, visit https://review.coreboot.org/c/coreboot/+/78327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 Gerrit-Change-Number: 78327 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 01 Dec 2023 13:09:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/rex/var/ovis: Add power limit support for MCH ID 0x7d14
by Paul Menzel (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Stefan Reinauer, Subrata Banik, Tarun. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79332?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/rex/var/ovis: Add power limit support for MCH ID 0x7d14 ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79332/comment/e5350883_a7c5ee0e : PS4, Line 10: 0x7d14 DID. Maybe mention it’s identical to PCI_DID_INTEL_MTL_P_ID_1. -- To view, visit https://review.coreboot.org/c/coreboot/+/79332?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iff71adb4e26d18970b5947927c258419f751de32 Gerrit-Change-Number: 79332 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 01 Dec 2023 12:14:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/rex/var/screebo: Override power limits
by Paul Menzel (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Subrata Banik, Tarun. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79330?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/rex/var/screebo: Override power limits ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79330/comment/0b76d98a_ab8ea9f8 : PS3, Line 21: [INFO ] Overriding power limits PL1 (mW) (10000, 15000) : PL2 (mW) (40000, 40000) PL4 (W) (84) : : After: : : [INFO ] Overriding power limits PL1 (mW) (10000, 15000) : PL2 (mW) (40000, 40000) PL4 (W) (84) The values are unchanged? -- To view, visit https://review.coreboot.org/c/coreboot/+/79330?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic66872c530963238a0bf5eebbd5b5a76a7985e5c Gerrit-Change-Number: 79330 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 01 Dec 2023 12:13:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: inteltool: improve support for Elkhart Lake
by Paul Menzel (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Alexander Couzens, Pratikkumar V Prajapati. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75214?usp=email ) Change subject: inteltool: improve support for Elkhart Lake ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75214?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida852f3c991cdd036d9c282f9cabceb23c765e25 Gerrit-Change-Number: 75214 Gerrit-PatchSet: 5 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Fri, 01 Dec 2023 12:12:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation
by Paul Menzel (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Felix Held, Nill Ge, Patrick Rudolph, TangYiwei, Tim Chu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email ) Change subject: soc/intel/xeon_sp: Redesign resource allocation ...................................................................... Patch Set 4: (1 comment) File src/device/pci_device.c: https://review.coreboot.org/c/coreboot/+/78327/comment/495d56a5_3d435348 : PS3, Line 613: .set_resources = pci_domain_set_resources, > > Does this change affect all boards, and should it be a separate commit ordered before? […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/78327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 Gerrit-Change-Number: 78327 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 01 Dec 2023 12:11:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation
by Arthur Heymans (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Christian Walter, David Hendricks, Felix Held, Nill Ge, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email ) Change subject: soc/intel/xeon_sp: Redesign resource allocation ...................................................................... Patch Set 3: (1 comment) File src/device/pci_device.c: https://review.coreboot.org/c/coreboot/+/78327/comment/11f32c02_29264e57 : PS3, Line 613: .set_resources = pci_domain_set_resources, > Does this change affect all boards, and should it be a separate commit ordered before? This code is the first one using this struct, so it only affects the boards from intel/xeon_sp -- To view, visit https://review.coreboot.org/c/coreboot/+/78327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 Gerrit-Change-Number: 78327 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 01 Dec 2023 10:57:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit December 2023