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Change subject: mb/google/{rex,ovis}: epp set to 45% for mtl performance expectation
......................................................................
Patch Set 3:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79386/comment/08baf12b_d772c50c :
PS3, Line 7: epp set to 45% for mtl performance expectation
> Maybe: […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/79386/comment/fddaad2c_504b0f3e :
PS3, Line 9: which is deemed insufficiently
: aggressive for meeting the MTL performance expectations in
: balance_performance mode.
> According to whom? Also, what does that mean exactly? It’s drawing too much power?
EPP=45% is giving the required performance with very minimum power impact. This is revirewd internally.
https://review.coreboot.org/c/coreboot/+/79386/comment/3815807a_5033ee73 :
PS3, Line 12: #cat
> Please add a space after #.
Acknowledged
https://review.coreboot.org/c/coreboot/+/79386/comment/308705b4_9600c9ef :
PS3, Line 11: balance_performance mode.
: #cat /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference
: balance_performance
: # iotools rdmsr 0 0x774
: 0x0000000080003f06
: EPP=45% is giving the required performance in MTL.
> I’d follow Markdown and intend code blocks with four spaces. […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/79386/comment/4f2258ce_9360fa47 :
PS3, Line 20: # iotools rdmsr 0 0x774
: 0x0000000073003d06
> How can the value be interpreted?
Details as in Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 4: Model-Specific Registers.
Also mentioned in patch - here is snapshot:
set EPP to 45%: 45 * 256/100 = 115 = 0x73
MSR 0x774 IA32_HWP_REQUEST [31:24] Energy/Performance Preference (R/W)
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Change subject: inteltool/gpio_names/*.h: Add GPL-2.0-only SPDX license header
......................................................................
Patch Set 4: Code-Review+2
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Change subject: inteltool/gpio_names/*.h: Add GPL-2.0-only SPDX license header
......................................................................
Patch Set 4:
(3 comments)
File util/inteltool/gpio_names/icelake.h:
https://review.coreboot.org/c/coreboot/+/78628/comment/88cd8c3b_30689e10 :
PS3, Line 1: /* inteltool - dump all registers on an Intel CPU + chipset based system */
> here as well
Done
File util/inteltool/gpio_names/lewisburg.h:
https://review.coreboot.org/c/coreboot/+/78628/comment/5a9abd15_e2f5ee3a :
PS3, Line 1: /* inteltool - dump all registers on an Intel CPU + chipset based system */
> here as well
Done
File util/inteltool/gpio_names/sunrise.h:
https://review.coreboot.org/c/coreboot/+/78628/comment/400c50b1_27dabae6 :
PS3, Line 1: /* inteltool - dump all registers on an Intel CPU + chipset based system */
> missed that
Seems like `vim -p *.h` hit a tab limit when I removed those from the other files. I also seemed to have missed adding a header to a few files for the same reason. Fixed.
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Hello Alexander Couzens, Felix Singer, Martin L Roth, Pratikkumar V Prajapati, Stefan Reinauer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/78628?usp=email
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The following approvals got outdated and were removed:
Code-Review+2 by Felix Singer, Verified+1 by build bot (Jenkins)
Change subject: inteltool/gpio_names/*.h: Add GPL-2.0-only SPDX license header
......................................................................
inteltool/gpio_names/*.h: Add GPL-2.0-only SPDX license header
Inteltool is GPLv2 licensed so all files that link to it should be GPLv2
by default. In addition, the contents of several of these headers were
originally moved directly from gpio_groups.c, which is explicitly marked
as GPL-2.0-only.
Change-Id: Ie897cb238c0c9e89fe677c999cbf1803f5f4609a
Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com>
---
M util/inteltool/gpio_names/alderlake_h.h
M util/inteltool/gpio_names/alderlake_p.h
M util/inteltool/gpio_names/apollolake.h
M util/inteltool/gpio_names/cannonlake.h
M util/inteltool/gpio_names/cannonlake_lp.h
M util/inteltool/gpio_names/denverton.h
M util/inteltool/gpio_names/elkhartlake.h
M util/inteltool/gpio_names/emmitsburg.h
M util/inteltool/gpio_names/geminilake.h
M util/inteltool/gpio_names/gpio_groups.h
M util/inteltool/gpio_names/icelake.h
M util/inteltool/gpio_names/jasperlake.h
M util/inteltool/gpio_names/lewisburg.h
M util/inteltool/gpio_names/sunrise.h
M util/inteltool/gpio_names/tigerlake.h
15 files changed, 30 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/78628/4
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Change subject: mb/google/rex/var/ovis: Add power limit support for MCH ID 0x7d14
......................................................................
Patch Set 4: Code-Review+2
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Change subject: mb/google/nissa/var/anraggar: Fix the GPP_D6 for LTE power.
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79166/comment/625f7427_a8b0e996 :
PS8, Line 6:
> Please do not ignore such comments next time. […]
Didn't we have a linter for that?
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Change subject: mb/google/{rex,ovis}: epp set to 45% for mtl performance expectation
......................................................................
Patch Set 3:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79386/comment/2b429b5b_d96c5573 :
PS3, Line 7: epp set to 45% for mtl performance expectation
Maybe:
> Decrease EPP to 45 % for MTL performance expectation
https://review.coreboot.org/c/coreboot/+/79386/comment/e51023fb_a398e364 :
PS3, Line 9: which is deemed insufficiently
: aggressive for meeting the MTL performance expectations in
: balance_performance mode.
According to whom? Also, what does that mean exactly? It’s drawing too much power?
https://review.coreboot.org/c/coreboot/+/79386/comment/46909162_acee6072 :
PS3, Line 12: #cat
Please add a space after #.
https://review.coreboot.org/c/coreboot/+/79386/comment/18ffa3d2_a755e492 :
PS3, Line 11: balance_performance mode.
: #cat /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference
: balance_performance
: # iotools rdmsr 0 0x774
: 0x0000000080003f06
: EPP=45% is giving the required performance in MTL.
I’d follow Markdown and intend code blocks with four spaces. (And also add blank lines around the block.)
https://review.coreboot.org/c/coreboot/+/79386/comment/f3d5ff83_f9f51e09 :
PS3, Line 20: # iotools rdmsr 0 0x774
: 0x0000000073003d06
How can the value be interpreted?
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Change subject: mb/google/nissa/var/anraggar: Fix the GPP_D6 for LTE power.
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79166/comment/00af2d65_80e955b1 :
PS8, Line 6:
Please do not ignore such comments next time.
> `Subject line should not end with a period.`
Please fix.
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The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: inteltool/gpio_names/*.h: Add GPL-2.0-only SPDX license header
......................................................................
Patch Set 3:
(3 comments)
File util/inteltool/gpio_names/icelake.h:
https://review.coreboot.org/c/coreboot/+/78628/comment/d44e147d_96aebd26 :
PS3, Line 1: /* inteltool - dump all registers on an Intel CPU + chipset based system */
here as well
File util/inteltool/gpio_names/lewisburg.h:
https://review.coreboot.org/c/coreboot/+/78628/comment/5c76f90c_3b5a04df :
PS3, Line 1: /* inteltool - dump all registers on an Intel CPU + chipset based system */
here as well
File util/inteltool/gpio_names/sunrise.h:
https://review.coreboot.org/c/coreboot/+/78628/comment/738f21be_a4378f57 :
PS3, Line 1: /* inteltool - dump all registers on an Intel CPU + chipset based system */
missed that
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