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[M] Change in coreboot[master]: cpu/x86/64bit/mode_switch2: The reverse function to mode_switch
by Patrick Rudolph (Code Review) 29 Dec '23

29 Dec '23

Attention is currently required from: Jérémy Compostella. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79749?usp=email ) Change subject: cpu/x86/64bit/mode_switch2: The reverse function to mode_switch ...................................................................... cpu/x86/64bit/mode_switch2: The reverse function to mode_switch Add another mode_switch assembly function to call x86_64 code from x86_32 code. This is particullary useful for BLOBs like mrc.bin or FSP that calls back into coreboot. Tested: - Called x86_64 code from x86_32 code in qemu. - Booted Lenovo X220 using x86_32 MRC using x86_64 console. Change-Id: Ib625233e5f673eae9f3dcb2d03004c06bb07b149 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/include/mode_switch.h M src/cpu/x86/64bit/Makefile.inc A src/cpu/x86/64bit/mode_switch2.S 3 files changed, 114 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/79749/1 diff --git a/src/arch/x86/include/mode_switch.h b/src/arch/x86/include/mode_switch.h index 4235db9..c2cbbf5 100644 --- a/src/arch/x86/include/mode_switch.h +++ b/src/arch/x86/include/mode_switch.h @@ -3,6 +3,27 @@ #include <stdint.h> #if ENV_X86_64 +static inline int long_mode_call(void *func) +{ + int (*doit)(void) = func; + + return doit(); +} + +static inline int long_mode_call_1arg(void *func, uint32_t arg1) +{ + int (*doit)(uint32_t arg1) = func; + + return doit(arg1); +} + +static inline int long_mode_call_2arg(void *func, uint32_t arg1, uint32_t arg2) +{ + int (*doit)(uint32_t arg1, uint32_t arg2) = func; + + return doit(arg1, arg2); +} + /* * Assembly code that drops into protected mode and calls the function * specified as first argument, which must have been compiled for x86_32. @@ -54,6 +75,55 @@ return protected_mode_call_3arg((uintptr_t)func, arg1, arg2, 0); } #else +/* + * Assembly function that elevates into long mode and calls the function + * specified as first argument, which must have been compiled for x86_64. + * After the function returns it enters protected mode again. + * The function pointer destination must be below 4GiB in physical memory. + * + * The called function has three arguments and returns an int. + */ +int long_mode_call_3arg(uint32_t func_ptr, + uint32_t opt_arg1, + uint32_t opt_arg2, + uint32_t opt_arg3); + +/* + * Elevates into long mode and calls the function, which must have been compiled for x86_64. + * After the function returns it enters protected mode again. + * The function pointer destination must be below 4GiB in physical memory. + * + * The called function doesn't have arguments and returns an int. + */ +static inline int long_mode_call(void *func) +{ + return long_mode_call_3arg((uintptr_t)func, 0, 0, 0); +} + +/* + * Elevates into long mode and calls the function, which must have been compiled for x86_64. + * After the function returns it enters protected mode again. + * The function pointer destination must be below 4GiB in physical memory. + * + * The called function has one argument and returns an int. + */ +static inline int long_mode_call_1arg(void *func, uint32_t arg1) +{ + return long_mode_call_3arg((uintptr_t)func, arg1, 0, 0); +} + +/* + * Elevates into long mode and calls the function, which must have been compiled for x86_64. + * After the function returns it enters protected mode again. + * The function pointer destination must be below 4GiB in physical memory. + * + * The called function has two arguments and returns an int. + */ +static inline int long_mode_call_2arg(void *func, uint32_t arg1, uint32_t arg2) +{ + return long_mode_call_3arg((uintptr_t)func, arg1, arg2, 0); +} + static inline int protected_mode_call(void *func) { int (*doit)(void) = func; diff --git a/src/cpu/x86/64bit/Makefile.inc b/src/cpu/x86/64bit/Makefile.inc index e1cf743..24a5a96 100644 --- a/src/cpu/x86/64bit/Makefile.inc +++ b/src/cpu/x86/64bit/Makefile.inc @@ -1,6 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only all_x86-y += mode_switch.S +all_x86-y += mode_switch2.S # Add --defsym=_start=0 to suppress a linker warning. $(objcbfs)/pt: $(dir)/pt.S $(obj)/config.h diff --git a/src/cpu/x86/64bit/mode_switch2.S b/src/cpu/x86/64bit/mode_switch2.S new file mode 100644 index 0000000..0d39f50 --- /dev/null +++ b/src/cpu/x86/64bit/mode_switch2.S @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Calls a x86_64 function from x86_32 context */ + +.text +.code32 + .section ".text.long_mode_call_3arg", "ax", @progbits + .globl long_mode_call_3arg +long_mode_call_3arg: + + /* Backup registers */ + pushal + + /* Backup stack pointer */ + mov %esp, %ebp + + /* Enter long mode, preserves ebx */ + #include <cpu/x86/64bit/entry64.inc> + + /* Align stack */ + movabs $0xfffffffffffffff0, %rax + andq %rax, %rsp + + movl 36(%rbp), %ebx /* Function to call */ + movl 40(%rbp), %edi /* 1st arg */ + movl 44(%rbp), %esi /* 2nd arg */ + movl 48(%rbp), %edx /* 3rd arg */ + + call *%rbx + + /* Store return value on stack. popal will fetch it. */ + mov %eax, 28(%rbp) + shr $32, %rax + movl %eax, 24(%rbp) + + #include <cpu/x86/64bit/exit32.inc> + + /* Restore stack pointer */ + mov %ebp, %esp + + /* Restore registers */ + popal + + ret -- To view, visit https://review.coreboot.org/c/coreboot/+/79749?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib625233e5f673eae9f3dcb2d03004c06bb07b149 Gerrit-Change-Number: 79749 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: cpu/x86/64bit/mode_switch: Simplify assembly code
by Patrick Rudolph (Code Review) 29 Dec '23

29 Dec '23

Attention is currently required from: Jérémy Compostella. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79748?usp=email ) Change subject: cpu/x86/64bit/mode_switch: Simplify assembly code ...................................................................... cpu/x86/64bit/mode_switch: Simplify assembly code Drop the first argument specifying the number of arguments pushed to the stack. Instead always push the 3 arguments to stack and use the first one as function pointer to call while in protected mode. While on it add more comments and simplify register restore code. Tested: - On qemu can call x86_32 function and pass argument and return value. - Booted Lenovo X220 in x86_64 mode using x86_32 MRC. Change-Id: I30809453a1800ba3c0df60acd7eca778841c520f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/include/mode_switch.h M src/cpu/x86/64bit/mode_switch.S 2 files changed, 45 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/79748/1 diff --git a/src/arch/x86/include/mode_switch.h b/src/arch/x86/include/mode_switch.h index 24efb1e..4235db9 100644 --- a/src/arch/x86/include/mode_switch.h +++ b/src/arch/x86/include/mode_switch.h @@ -3,10 +3,18 @@ #include <stdint.h> #if ENV_X86_64 -int protected_mode_call_narg(uint32_t arg_count, - uint32_t func_ptr, +/* + * Assembly code that drops into protected mode and calls the function + * specified as first argument, which must have been compiled for x86_32. + * After the function returns it enters long mode again. + * The function pointer destination must be below 4GiB in physical memory. + * + * The called function has 0-3 arguments and returns an int. + */ +int protected_mode_call_3arg(uint32_t func_ptr, uint32_t opt_arg1, - uint32_t opt_arg2); + uint32_t opt_arg2, + uint32_t opt_arg3); /* * Drops into protected mode and calls the function, which must have been compiled for x86_32. @@ -17,7 +25,7 @@ */ static inline int protected_mode_call(void *func) { - return protected_mode_call_narg(0, (uintptr_t)func, 0, 0); + return protected_mode_call_3arg((uintptr_t)func, 0, 0, 0); } /* @@ -30,7 +38,7 @@ */ static inline int protected_mode_call_1arg(void *func, uint32_t arg1) { - return protected_mode_call_narg(1, (uintptr_t)func, arg1, 0); + return protected_mode_call_3arg((uintptr_t)func, arg1, 0, 0); } /* @@ -43,7 +51,7 @@ */ static inline int protected_mode_call_2arg(void *func, uint32_t arg1, uint32_t arg2) { - return protected_mode_call_narg(2, (uintptr_t)func, arg1, arg2); + return protected_mode_call_3arg((uintptr_t)func, arg1, arg2, 0); } #else static inline int protected_mode_call(void *func) diff --git a/src/cpu/x86/64bit/mode_switch.S b/src/cpu/x86/64bit/mode_switch.S index c27f540..f9f784e 100644 --- a/src/cpu/x86/64bit/mode_switch.S +++ b/src/cpu/x86/64bit/mode_switch.S @@ -1,14 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +/* Calls a x86_32 function from x86_64 context */ .text .code64 .section ".text.protected_mode_call", "ax", @progbits - .globl protected_mode_call_narg -protected_mode_call_narg: - - push %rbp - mov %rsp, %rbp + .globl protected_mode_call_3arg +protected_mode_call_3arg: /* Preserve registers */ + push %rbp push %rbx push %r12 push %r13 @@ -19,58 +18,47 @@ movl %gs, %eax push %rax - /* Arguments to stack */ - push %rdi - push %rsi - push %rdx - push %rcx + /* Store stack pointer */ + mov %rsp, %rbp + /* Align stack and make space for arguments */ + movabs $0xfffffffffffffff0, %rax + andq %rax, %rsp + sub $16, %rsp + + /* Arguments to stack */ + movl %edi, 12(%rsp) + movl %esi, 0(%rsp) + movl %edx, 4(%rsp) + movl %ecx, 8(%rsp) + + /* Drop to protected mode */ #include <cpu/x86/64bit/exit32.inc> - movl -56(%ebp), %eax /* Argument count */ - movl -72(%ebp), %edx /* Argument 0 */ - movl -80(%ebp), %ecx /* Argument 1 */ + /* Fetch function to call */ + movl 12(%esp), %ebx - /* Align the stack */ - andl $0xFFFFFFF0, %esp - test %eax, %eax - je 1f /* Zero arguments */ - - subl $1, %eax - test %eax, %eax - je 2f /* One argument */ - - /* Two arguments */ - subl $8, %esp - pushl %ecx /* Argument 1 */ - pushl %edx /* Argument 0 */ - jmp 1f -2: - subl $12, %esp - pushl %edx /* Argument 0 */ - -1: - movl -64(%ebp), %ebx /* Function to call */ + /* Call function */ call *%ebx movl %eax, %ebx - /* Preserves ebx */ + /* Jump to long mode. Preserves ebx */ #include <cpu/x86/64bit/entry64.inc> /* Place return value in rax */ movl %ebx, %eax - /* Restore registers */ - mov -48(%rbp), %rbx - movl %ebx, %gs - mov -40(%rbp), %r15 - mov -32(%rbp), %r14 - mov -24(%rbp), %r13 - mov -16(%rbp), %r12 - mov -8(%rbp), %rbx - /* Restore stack pointer */ mov %rbp, %rsp + + /* Restore registers */ + pop %rbx + movl %ebx, %gs + pop %r15 + pop %r14 + pop %r13 + pop %r12 + pop %rbx pop %rbp ret -- To view, visit https://review.coreboot.org/c/coreboot/+/79748?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30809453a1800ba3c0df60acd7eca778841c520f Gerrit-Change-Number: 79748 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: northbridge/intel/sandybridge/raminit: Prepare MRC path for x86_64
by Patrick Rudolph (Code Review) 29 Dec '23

29 Dec '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79747?usp=email ) Change subject: northbridge/intel/sandybridge/raminit: Prepare MRC path for x86_64 ...................................................................... northbridge/intel/sandybridge/raminit: Prepare MRC path for x86_64 - Remove pointers in argument list passed to MRC to make sure the struct has the same size on x86_64 as on x86_32. - Add assembly wrapper to call the MRC with argument in EAX. - Wrap calling MRC in protected_mode_call_2arg, which is a stub on x86_32 Tested: Boots on Lenovo X220 using MRC in x86_32 and x86_64 Change-Id: Id755e7381c5a94360e3511c53432d68b7687df67 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/Makefile.inc A src/northbridge/intel/sandybridge/mrc_wrapper.S M src/northbridge/intel/sandybridge/pei_data.h M src/northbridge/intel/sandybridge/raminit_mrc.c 4 files changed, 51 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/79747/1 diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 36fc16b..6ecb17a 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -27,6 +27,7 @@ romstage-y += raminit_tables.c else romstage-y += raminit_mrc.c +romstage-y += mrc_wrapper.S cbfs-files-y += mrc.bin mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE)) mrc.bin-position := 0xfffa0000 diff --git a/src/northbridge/intel/sandybridge/mrc_wrapper.S b/src/northbridge/intel/sandybridge/mrc_wrapper.S new file mode 100644 index 0000000..e169064 --- /dev/null +++ b/src/northbridge/intel/sandybridge/mrc_wrapper.S @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Functions to call MRC.bin from x86_64 */ + +.text +.code32 + .section ".text.mrc_wrapper", "ax", @progbits + .globl mrc_wrapper +mrc_wrapper: + /* Set up new stack frame */ + pushal + mov %esp, %ebp + + /* Align stack */ + andl $0xfffffff0, %esp + + movl 36(%ebp), %ebx /* Get function pointer */ + movl 40(%ebp), %eax /* Get argument */ + + call *%ebx + + /* Place return value on stack so that popal fetches it */ + movl %eax, 28(%ebp) + + /* Restore stack pointer */ + mov %ebp, %esp + popal + ret + diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h index 7abc25f..0309cf3 100644 --- a/src/northbridge/intel/sandybridge/pei_data.h +++ b/src/northbridge/intel/sandybridge/pei_data.h @@ -50,10 +50,10 @@ uint32_t scrambler_seed; uint32_t scrambler_seed_s3; /* Data read from flash and passed into MRC */ - unsigned char *mrc_input; + uint32_t mrc_input_ptr; unsigned int mrc_input_len; /* Data from MRC that should be saved to flash */ - unsigned char *mrc_output; + uint32_t mrc_output_ptr; unsigned int mrc_output_len; /* * Max frequency DDR3 could be ran at. Could be one of four values: @@ -87,7 +87,9 @@ * which DIMMs should use the SPD from spd_data[0]. */ uint8_t spd_data[4][256]; - tx_byte_func tx_byte; + /* 32 bit pointer to tx_byte_func */ + uint32_t tx_byte_ptr; + int ddr3lv_support; /* * pcie_init needs to be set to 1 to have the system agent initialize PCIe. diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 68b02b8..d59aa86 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -28,6 +28,7 @@ #include <security/vboot/vboot_common.h> #include <southbridge/intel/bd82x6x/pch.h> #include <memory_info.h> +#include <mode_switch.h> /* Management Engine is in the southbridge */ #include <southbridge/intel/bd82x6x/me.h> @@ -49,13 +50,17 @@ #define MRC_CACHE_VERSION 0 +/* Assembly functions: */ +void mrc_wrapper(void *func_ptr, uint32_t arg1); + static void save_mrc_data(struct pei_data *pei_data) { u16 c1, c2, checksum; /* Save the MRC S3 restore data to cbmem */ - mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, pei_data->mrc_output, - pei_data->mrc_output_len); + mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, + (void *)(uintptr_t)pei_data->mrc_output_ptr, + pei_data->mrc_output_len); /* Save the MRC seed values to CMOS */ cmos_write32(pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); @@ -81,7 +86,7 @@ size_t mrc_size; /* Preset just in case there is an error */ - pei_data->mrc_input = NULL; + pei_data->mrc_input_ptr = 0; pei_data->mrc_input_len = 0; /* Read scrambler seeds from CMOS */ @@ -108,18 +113,18 @@ return; } - pei_data->mrc_input = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, + pei_data->mrc_input_ptr = (uintptr_t)mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &mrc_size); - if (!pei_data->mrc_input) { + if (!pei_data->mrc_input_ptr) { /* Error message printed in find_current_mrc_cache */ return; } pei_data->mrc_input_len = mrc_size; - printk(BIOS_DEBUG, "%s: at %p, size %zx\n", __func__, - pei_data->mrc_input, mrc_size); + printk(BIOS_DEBUG, "%s: at 0x%x, size %zx\n", __func__, + pei_data->mrc_input_ptr, mrc_size); } /** @@ -129,7 +134,7 @@ */ static void sdram_initialize(struct pei_data *pei_data) { - int (*entry)(struct pei_data *pei_data) __attribute__((regparm(1))); + int (*entry)(struct pei_data *pei_data); /* Wait for ME to be ready */ intel_early_me_init(); @@ -144,19 +149,19 @@ prepare_mrc_cache(pei_data); /* If MRC data is not found we cannot continue S3 resume. */ - if (pei_data->boot_mode == 2 && !pei_data->mrc_input) { + if (pei_data->boot_mode == 2 && !pei_data->mrc_input_ptr) { printk(BIOS_DEBUG, "Giving up in %s: No MRC data\n", __func__); system_reset(); } /* Pass console handler in pei_data */ - pei_data->tx_byte = do_putchar; + pei_data->tx_byte_ptr = (uintptr_t)do_putchar; /* Locate and call UEFI System Agent binary. */ entry = cbfs_map("mrc.bin", NULL); if (entry) { int rv; - rv = entry(pei_data); + rv = protected_mode_call_2arg(mrc_wrapper, (uintptr_t)entry, (uintptr_t)pei_data); if (rv) { switch (rv) { case -1: @@ -403,7 +408,7 @@ /* Sanity check mrc_var location by verifying a known field */ mrc_var = (void *)DCACHE_RAM_MRC_VAR_BASE; - if (mrc_var->tx_byte == (uintptr_t)pei_data.tx_byte) { + if (mrc_var->tx_byte == pei_data.tx_byte_ptr) { printk(BIOS_DEBUG, "MRC_VAR pool occupied [%08x,%08x]\n", mrc_var->pool_base, mrc_var->pool_base + mrc_var->pool_used); -- To view, visit https://review.coreboot.org/c/coreboot/+/79747?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id755e7381c5a94360e3511c53432d68b7687df67 Gerrit-Change-Number: 79747 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: mb/google/nissa/var/craaskov: Implement touchscreen power sequencing
by Eric Lai (Code Review) 29 Dec '23

29 Dec '23

Attention is currently required from: Dtrain Hsu, Kenny Pan, Nick Vaccaro, Rex Chou, Shou-Chieh Hsu, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79764?usp=email ) Change subject: mb/google/nissa/var/craaskov: Implement touchscreen power sequencing ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79764?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ca2e2d12a86eaae9e37870a2541c0287e354690 Gerrit-Change-Number: 79764 Gerrit-PatchSet: 1 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kenny Pan <kennypan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kenny Pan <kennypan(a)google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Fri, 29 Dec 2023 06:39:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa/var/craaskov: Implement touchscreen power sequencing
by Eric Lai (Code Review) 29 Dec '23

29 Dec '23

Attention is currently required from: Dtrain Hsu, Kenny Pan, Nick Vaccaro, Rex Chou, Shou-Chieh Hsu, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79764?usp=email ) Change subject: mb/google/nissa/var/craaskov: Implement touchscreen power sequencing ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79764/comment/25861e97_1d669454 : PS1, Line 11: This will allow coreboot : to detect the presence of i2c touchscreens during ACPI SSDT generation : (implemented in a subsequent commit). : is true? -- To view, visit https://review.coreboot.org/c/coreboot/+/79764?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ca2e2d12a86eaae9e37870a2541c0287e354690 Gerrit-Change-Number: 79764 Gerrit-PatchSet: 1 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kenny Pan <kennypan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kenny Pan <kennypan(a)google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Fri, 29 Dec 2023 06:39:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa/var/craaskov: Implement touchscreen power sequencing
by Rex Chou (Code Review) 29 Dec '23

29 Dec '23

Rex Chou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79764?usp=email ) Change subject: mb/google/nissa/var/craaskov: Implement touchscreen power sequencing ...................................................................... mb/google/nissa/var/craaskov: Implement touchscreen power sequencing For brya variants with a touchscreen, drive the enable GPIO high starting in romstage while holding in reset, then disable the reset GPIO in ramstage (done in the baseboard). This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). BUG=b:317746281 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I85f2bee58582c0f56331d20a2984a3079c967be4 Signed-off-by: rex_chou <rex_chou(a)compal.corp-partner.google.com> Change-Id: I3ca2e2d12a86eaae9e37870a2541c0287e354690 --- M src/mainboard/google/brya/variants/craaskov/gpio.c 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/79764/1 diff --git a/src/mainboard/google/brya/variants/craaskov/gpio.c b/src/mainboard/google/brya/variants/craaskov/gpio.c index 8b1446d..0d280ce 100644 --- a/src/mainboard/google/brya/variants/craaskov/gpio.c +++ b/src/mainboard/google/brya/variants/craaskov/gpio.c @@ -63,6 +63,14 @@ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), }; +static const struct pad_config romstage_gpio_table[] = { + /* Enable touchscreen, hold in reset */ + /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C1, 0, DEEP), +}; + const struct pad_config *variant_gpio_override_table(size_t *num) { *num = ARRAY_SIZE(override_gpio_table); @@ -74,3 +82,9 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/79764?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ca2e2d12a86eaae9e37870a2541c0287e354690 Gerrit-Change-Number: 79764 Gerrit-PatchSet: 1 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Enable SSE2 accelerated RSA sign. verification
by Subrata Banik (Code Review) 29 Dec '23

29 Dec '23

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Tarun. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79291?usp=email ) Change subject: soc/intel/meteorlake: Enable SSE2 accelerated RSA sign. verification ...................................................................... Patch Set 10: (1 comment) Patchset: PS4: > > unfortunately, I don't see any savings after picking this cl. > > Are you sure you have the vboot repository up-to-date in your build environment ? except this CL, all other Cls are now landed in downstream (including coreboot, vboot project). I have picked this CL and performed 20 cycles. I don't see 5ms savings in run to run variation. > Also the benefit is very small compared to the whole boot flow so you need an appropriate performance analysis methodology if you want to observe the benefit on the overall boot time in clear manner. Personally, I collect 20 warm reset `cbmem -t` logs. For those 20 logs, I generate the median of each time interval. Then I compare those. > > However, I you look at the the 505-506 interval which is when `modexp` is executed, you should observe a solid and systematic improvement of about 4.8 ms. > > I just re-did my boot performance analysis described above twice. In both cases I observe an overall boot time improvement. One is of 3.6 ms and the other of 9 ms. > > Note that the improvement is bit lower than it used to be. This is because only two RSA verification are performed now instead of 3. It seems to have changed in the last few months. I have updated the commit message accordingly. -- To view, visit https://review.coreboot.org/c/coreboot/+/79291?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I382e62a765dbf2027c4ac54d6eb19a9542a8c302 Gerrit-Change-Number: 79291 Gerrit-PatchSet: 10 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 29 Dec 2023 05:29:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: vboot: Add firmware PCR support
by Yi Chou (Code Review) 29 Dec '23

29 Dec '23

Attention is currently required from: Christian Walter, Julius Werner, Paul Menzel, Yu-Ping Wu. Yi Chou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79437?usp=email ) Change subject: vboot: Add firmware PCR support ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79437/comment/91b8fa9f_7a829255 : PS6, Line 24: to 10 (and we plan to use PCR 12 for kernel version). > Wait what? I thought we were planning to mix both versions into one PCR? Was there a specific reason […] hmmm, those were discussed in go/cros-arm-widevine-cert A potential advantage of separating them into two different PCRs is we can do the "double extended" prevention on the GSC side if we really need it. (Although I hope we don't need it.) The "double extended prevention" on PCR0: https://chromium-review.googlesource.com/c/chromiumos/third_party/tpm2/+/43… I think that should be a good reason to use an extra PCR for that. -- To view, visit https://review.coreboot.org/c/coreboot/+/79437?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I601ad31e8c893a8e9ae1a9cdd27193edce10ec61 Gerrit-Change-Number: 79437 Gerrit-PatchSet: 6 Gerrit-Owner: Yi Chou <yich(a)google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 29 Dec 2023 01:29:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: util: add smmstoretool for editing SMMSTORE
by Sergii Dmytruk (Code Review) 28 Dec '23

28 Dec '23

Attention is currently required from: Filip Lewiński, Michał Kopeć, Michał Żygowski. Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79080?usp=email ) Change subject: util: add smmstoretool for editing SMMSTORE ...................................................................... Patch Set 6: (2 comments) Patchset: PS6: > Can't compile it under bare metal Ubuntu 22.04: https://paste.dasharo. […] Thanks, looks like Ubuntu compiles code as position independent causing `#pragma GCC visibility push (hidden)` in `src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/X64/ProcessorBind.h` otherwise disabled by `#if ... && defined(__pic__) && ...` to break external definitions. Should be fixed now. File util/smmstoretool/Makefile: https://review.coreboot.org/c/coreboot/+/79080/comment/d82dd446_39205883 : PS6, Line 8: CC := $(CROSS_COMPILE)gcc > This is rather an utility, so it should have something like: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79080?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6c1c06f1d0c39c13b5be76a3070f09b715aca6e0 Gerrit-Change-Number: 79080 Gerrit-PatchSet: 6 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Filip Lewiński Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Filip Lewiński Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Thu, 28 Dec 2023 22:35:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: util: add smmstoretool for editing SMMSTORE
by Sergii Dmytruk (Code Review) 28 Dec '23

28 Dec '23

Attention is currently required from: Filip Lewiński, Michał Kopeć, Sergii Dmytruk. Hello Filip Lewiński, Michał Kopeć, Michał Żygowski, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79080?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Code-Review+1 by Filip Lewiński, Verified+1 by build bot (Jenkins) Change subject: util: add smmstoretool for editing SMMSTORE ...................................................................... util: add smmstoretool for editing SMMSTORE Offline SMMSTORE variable modification tool. Can be used to pre-configure ROM image or debug EFI state stored in a dump. Change-Id: I6c1c06f1d0c39c13b5be76a3070f09b715aca6e0 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M Documentation/util.md A Documentation/util/smmstoretool/index.md M util/README.md A util/smmstoretool/.gitignore A util/smmstoretool/Makefile A util/smmstoretool/data.c A util/smmstoretool/data.h A util/smmstoretool/description.md A util/smmstoretool/fv.c A util/smmstoretool/fv.h A util/smmstoretool/guids.c A util/smmstoretool/guids.h A util/smmstoretool/main.c A util/smmstoretool/storage.c A util/smmstoretool/storage.h A util/smmstoretool/udk2017.h A util/smmstoretool/utils.c A util/smmstoretool/utils.h A util/smmstoretool/vs.c A util/smmstoretool/vs.h M util/util_readme/post_util.md 21 files changed, 1,730 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/79080/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/79080?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6c1c06f1d0c39c13b5be76a3070f09b715aca6e0 Gerrit-Change-Number: 79080 Gerrit-PatchSet: 7 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Filip Lewiński Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Filip Lewiński Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2023