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Change subject: security/tpm: Retrieve factory configuration for device w/ Google TPM
......................................................................
Patch Set 5:
(1 comment)
File src/security/tpm/tss/vendor/cr50/cr50.c:
https://review.coreboot.org/c/coreboot/+/79736/comment/af053fbd_3f7ce748 :
PS5, Line 186: printk(BIOS_INFO, "Reading factory config\n");
> nit: I'd maybe consider putting this at the end of the function and then printing the received value […]
Actually, the caching would probably better be done in chromeos_get_factory_config(), if anything.
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Change subject: arch/arm64: Support calling a trusted monitor
......................................................................
Patch Set 13:
(2 comments)
File src/arch/arm64/include/armv8/arch/smc.h:
https://review.coreboot.org/c/coreboot/+/78284/comment/938d47ba_f1bd6914 :
PS13, Line 8: static inline u
Sorry, this one can't be static inline. I'm actually surprised the compiler doesn't complain about that. A function should either be static inline and then have the function body right there in the header file (like smc_call3() here), or it should be just declared as a prototype like this and then be neither static nor inline.
File src/arch/arm64/smc.c:
https://review.coreboot.org/c/coreboot/+/78284/comment/44355721_dd6bc58f :
PS11, Line 10: inline uint64_t smc_call(uint32_t function_id, uint64_t arg1, uint64_t arg2, uint64_t arg3,
> > I actually found that other boards broke if this file was compiled unconditionally. […]
I just meant putting smc_call() into the header and leaving smc() as it was. But I'm fine with just getting rid of the assert() as well (the Makefile ifeq will already take care of that, essentially).
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Change subject: security/tpm: Retrieve factory configuration for device w/ Google TPM
......................................................................
Patch Set 5:
(3 comments)
File src/security/tpm/tss/tcg-2.0/tss_structures.h:
https://review.coreboot.org/c/coreboot/+/79736/comment/ea1848a9_13873b68 :
PS5, Line 361: uint64_t factory_config;
Why are you doing it like this? Unless I'm missing something here I think you should just put it inside the union, next to the others. You also shouldn't need to add explicit padding in this structures, this is not a serialized structure, it's just for internal data passing within the TPM API.
File src/security/tpm/tss/vendor/cr50/cr50.c:
https://review.coreboot.org/c/coreboot/+/79736/comment/b7f03002_9423cc33 :
PS5, Line 186: printk(BIOS_INFO, "Reading factory config\n");
nit: I'd maybe consider putting this at the end of the function and then printing the received value while you're at it? (We might also want to consider caching the value in a static variable like board_id(), although we can also wait with that until we have multiple callers.)
https://review.coreboot.org/c/coreboot/+/79736/comment/1947f6fb_7264504a :
PS5, Line 196: * ladder.
Is this actually relevant to this command and its use case? Why would the key ladder be disabled here? This looks like it was just copied from `tlcl_cr50_get_tpm_mode()` but doesn't apply here.
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Change subject: soc/intel/meteorlake: Enable SSE2 accelerated RSA sign. verification
......................................................................
Patch Set 9:
(1 comment)
Patchset:
PS4:
> unfortunately, I don't see any savings after picking this cl.
Are you sure you have the vboot repository up-to-date in your build environment ? Also the benefit is very small compared to the whole boot flow so you need an appropriate performance analysis methodology if you want to observe the benefit on the overall boot time in clear manner. Personally, I collect 20 warm reset `cbmem -t` logs. For those 20 logs, I generate the median of each time interval. Then I compare those.
However, I you look at the the 505-506 interval which is when `modexp` is executed, you should observe a solid and systematic improvement of about 4.8 ms.
I just re-did my boot performance analysis described above twice. In both cases I observe an overall boot time improvement. One is of 3.6 ms and the other of 9 ms.
Note that the improvement is bit lower than it used to be. This is because only two RSA verification are performed now instead of 3. It seems to have changed in the last few months. I have updated the commit message accordingly.
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Change subject: devicetree.cb: Use a macro to make IO genx_dec more comprehensible
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/51nb/x210/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/79742/comment/4a0944d9_b5129e24 :
PS3, Line 29: 0x0c | 0x3
I assume the `| 0x3` is just to communicate that bits 1:0 are effectively "included" in the mask since the chipset ignores those bits completely (and they are masked out anyway in the macro definition)?
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Change subject: devicetree.cb: Use a macro to make IO genx_dec more comprehensible
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79742/comment/e4ad6191_6334ad04 :
PS3, Line 13: 0x00
> > Based on a quick skim of the output of `grep -E "gen[1-4]_dec" $(find -name "*. […]
Based on playing around with a regex tester something like `sed -i 's/register "gen\([1-4]\)_dec" = "0x0\{0,2\}\([0-9A-Fa-f]\{2\}\)\([0-9A-Fa-f]\{3\}\)1"/register "gen\1_dec" = "LPC_IO_DEC(0x\30, 0x\2 | 0x3)"/g' $devicetree` would work, but I guess whatever is easiest/most understandable is best.
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Change subject: mb/dell: Add Latitude E6400
......................................................................
Patch Set 12:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59704/comment/ace11896_cc455942 :
PS12, Line 32: SD card slot
> Is this under the traditional PCI bus (1e.0)? If so, the effective content of acpi/ich9_pci_irqs. […]
Fixed in commit 5c1455495e (mb/dell/e6400/acpi: Route Ricoh R5C847 PCI IRQ lines as DBC)
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Change subject: devicetree.cb: Use a macro to make IO genx_dec more comprehensible
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Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79742/comment/abecb461_92bef637 :
PS3, Line 13: 0x00
> Based on a quick skim of the output of `grep -E "gen[1-4]_dec" $(find -name "*.cb")`, there seem to be a few cases where the leading 00 isn't present, such as the x230,
I guess sed won't cut it. I'll write a small program. Thanks
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