coreboot-gerrit December 2023

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[XS] Change in coreboot[main]: mb/pcengines/apu2/mainboard: add PIRQ routing for 02.4 and 02.5
by Felix Held (Code Review) 28 Dec '23

28 Dec '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79674?usp=email ) Change subject: mb/pcengines/apu2/mainboard: add PIRQ routing for 02.4 and 02.5 ...................................................................... mb/pcengines/apu2/mainboard: add PIRQ routing for 02.4 and 02.5 Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Change-Id: I30cff76abddd3f9a81ac5041260ca7ab1d5244f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79674 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/pcengines/apu2/mainboard.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index ab9156f..9d218e6 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -98,6 +98,8 @@ {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */ {NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe: 02.2 */ {NB_PCIE_PORT3_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}}, /* NIC: 02.3 */ + {NB_PCIE_PORT4_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C}}, /* 02.4 */ + {NB_PCIE_PORT5_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* 02.5 */ {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */ {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/79674?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I30cff76abddd3f9a81ac5041260ca7ab1d5244f9 Gerrit-Change-Number: 79674 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/pcengines/apu2/mainboard: add PIRQ routing for 02.4 and 02.5
by Felix Held (Code Review) 28 Dec '23

28 Dec '23

Attention is currently required from: Krystian Hebel, Michał Żygowski, Piotr Król. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79674?usp=email ) Change subject: mb/pcengines/apu2/mainboard: add PIRQ routing for 02.4 and 02.5 ...................................................................... Patch Set 1: (1 comment) File src/mainboard/pcengines/apu2/mainboard.c: https://review.coreboot.org/c/coreboot/+/79674/comment/db9afb7b_78ed689b : PS1, Line 101: {NB_PCIE_PORT4_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C}}, /* 02.4 */ addressed in CB:79676 -- To view, visit https://review.coreboot.org/c/coreboot/+/79674?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I30cff76abddd3f9a81ac5041260ca7ab1d5244f9 Gerrit-Change-Number: 79674 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Thu, 28 Dec 2023 16:54:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: devicetree.cb: Use a macro to make IO genx_dec more comprehensible
by Nicholas Chin (Code Review) 28 Dec '23

28 Dec '23

Attention is currently required from: Alexander Couzens, Angel Pons, Arthur Heymans, Christian Walter, Dinesh Gehlot, Eran Mitrani, Eric Lai, Erik van den Bogaert, Evgeny Sorokin, Frans Hendriks, Jakub Czapiga, Jeremy Soller, Johnny Lin, Jonathon Hall, Kapil Porwal, Kevin Keijzer, Lean Sheng Tan, Michael Niewöhner, Michał Kopeć, Michał Żygowski, Morgan Jang, Nick Vaccaro, Nico Huber, Piotr Król, Sean Rhodes, Stefan Ott, Subrata Banik, Tarun, Tim Chu, Tim Crawford, Werner Zeh. Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79742?usp=email ) Change subject: devicetree.cb: Use a macro to make IO genx_dec more comprehensible ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79742/comment/413f91cf_558f27f0 : PS3, Line 9: command commands -- To view, visit https://review.coreboot.org/c/coreboot/+/79742?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic05a7b1e6d0bafcd3c376b8f8dc4acce0f2629a7 Gerrit-Change-Number: 79742 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Evgeny Sorokin <me(a)ch1p.io> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Evgeny Sorokin <me(a)ch1p.io> Gerrit-Comment-Date: Thu, 28 Dec 2023 16:48:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: devicetree.cb: Use a macro to make IO genx_dec more comprehensible
by Nicholas Chin (Code Review) 28 Dec '23

28 Dec '23

Attention is currently required from: Alexander Couzens, Angel Pons, Arthur Heymans, Christian Walter, Dinesh Gehlot, Eran Mitrani, Eric Lai, Erik van den Bogaert, Evgeny Sorokin, Frans Hendriks, Jakub Czapiga, Jeremy Soller, Johnny Lin, Jonathon Hall, Kapil Porwal, Kevin Keijzer, Lean Sheng Tan, Michael Niewöhner, Michał Kopeć, Michał Żygowski, Morgan Jang, Nick Vaccaro, Nico Huber, Piotr Król, Sean Rhodes, Stefan Ott, Subrata Banik, Tarun, Tim Chu, Tim Crawford, Werner Zeh. Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79742?usp=email ) Change subject: devicetree.cb: Use a macro to make IO genx_dec more comprehensible ...................................................................... Patch Set 3: (1 comment) File src/southbridge/intel/common/lpc.h: https://review.coreboot.org/c/coreboot/+/79742/comment/5d5d1705_6b46951f : PS3, Line 7: LPC_IO_DEC This conflicts with the some of the `soc/intel/*/include/soc/lpc.h` and `sb/intel/*/i82801*x.h` and `sb/intel/*/pch.h` files, which have an LPC_IO_DEC macro to refer to the I/O Decode Ranges Register (enables for legacy decode ranges like COM ports, KBC, etc) at offset 0x80. The Jenkins failures seem to be due to this. -- To view, visit https://review.coreboot.org/c/coreboot/+/79742?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic05a7b1e6d0bafcd3c376b8f8dc4acce0f2629a7 Gerrit-Change-Number: 79742 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Evgeny Sorokin <me(a)ch1p.io> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Evgeny Sorokin <me(a)ch1p.io> Gerrit-Comment-Date: Thu, 28 Dec 2023 16:46:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: devicetree.cb: Use a macro to make IO genx_dec more comprehensible
by Nicholas Chin (Code Review) 28 Dec '23

28 Dec '23

Attention is currently required from: Alexander Couzens, Angel Pons, Arthur Heymans, Christian Walter, Dinesh Gehlot, Eran Mitrani, Eric Lai, Erik van den Bogaert, Evgeny Sorokin, Frans Hendriks, Jakub Czapiga, Jeremy Soller, Johnny Lin, Jonathon Hall, Kapil Porwal, Kevin Keijzer, Lean Sheng Tan, Michael Niewöhner, Michał Kopeć, Michał Żygowski, Morgan Jang, Nick Vaccaro, Nico Huber, Piotr Król, Sean Rhodes, Stefan Ott, Subrata Banik, Tarun, Tim Chu, Tim Crawford, Werner Zeh. Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79742?usp=email ) Change subject: devicetree.cb: Use a macro to make IO genx_dec more comprehensible ...................................................................... Patch Set 3: (2 comments) Commit Message: PS3: Are there any cases where the lower nibble is 0xd or 0x5? These two commands only seem to account for cases 0x1 and 0x9. The lowest two bits should always be 0b01, but any of the 4 possibilities of the upper 2 bits should be valid based on the GENx_DEC register descriptions in Intel Datasheets. File src/southbridge/intel/common/lpc.h: https://review.coreboot.org/c/coreboot/+/79742/comment/bcaf8ee8_c6aef60a : PS3, Line 7: (mask) & 0xfc) This should be shifted 16 bits such that bits 7:2 of the mask line up with bits 23:18 in the register as per the GENx_DEC register descriptions. -- To view, visit https://review.coreboot.org/c/coreboot/+/79742?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic05a7b1e6d0bafcd3c376b8f8dc4acce0f2629a7 Gerrit-Change-Number: 79742 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Evgeny Sorokin <me(a)ch1p.io> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Evgeny Sorokin <me(a)ch1p.io> Gerrit-Comment-Date: Thu, 28 Dec 2023 16:36:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: devicetree.cb: Use a macro to make IO genx_dec more comprehensible
by Arthur Heymans (Code Review) 28 Dec '23

28 Dec '23

Attention is currently required from: Alexander Couzens, Angel Pons, Christian Walter, Dinesh Gehlot, Eran Mitrani, Eric Lai, Erik van den Bogaert, Evgeny Sorokin, Frans Hendriks, Jakub Czapiga, Jeremy Soller, Johnny Lin, Jonathon Hall, Kapil Porwal, Kevin Keijzer, Lean Sheng Tan, Michael Niewöhner, Michał Kopeć, Michał Żygowski, Morgan Jang, Nicholas Chin, Nick Vaccaro, Nico Huber, Piotr Król, Sean Rhodes, Stefan Ott, Subrata Banik, Tarun, Tim Chu, Tim Crawford, Werner Zeh. Hello Alexander Couzens, Angel Pons, Christian Walter, Dinesh Gehlot, Eran Mitrani, Eric Lai, Erik van den Bogaert, Evgeny Sorokin, Frans Hendriks, Jakub Czapiga, Jeremy Soller, Johnny Lin, Jonathon Hall, Kapil Porwal, Kevin Keijzer, Lean Sheng Tan, Michael Niewöhner, Michał Kopeć, Michał Żygowski, Morgan Jang, Nicholas Chin, Nick Vaccaro, Nico Huber, Piotr Król, Sean Rhodes, Stefan Ott, Subrata Banik, Tarun, Tim Chu, Tim Crawford, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79742?usp=email to look at the new patch set (#3). Change subject: devicetree.cb: Use a macro to make IO genx_dec more comprehensible ...................................................................... devicetree.cb: Use a macro to make IO genx_dec more comprehensible Done using the following command: "for devicetree in $(find -name '*.cb'); do sed -i 's/register "gen$[1-4]$_dec" = "0x00$[0-9A-Fa-f]\{2\}$$[0-9A-Fa-f]\{3\}$1"/register "gen\1_dec" = "LPC_IO_DEC(0x\30, 0x\2 | 0x3)"/g' $devicetree; done" and "for devicetree in $(find -name '*.cb'); do sed -i 's/register "gen$[1-4]$_dec" = "0x00$[0-9A-Fa-f]\{2\}$$[0-9A-Fa-f]\{3\}$9"/register "gen\1_dec" = "LPC_IO_DEC(0x\38, 0x\2 | 0x3)"/g' $devicetree; done" Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Ic05a7b1e6d0bafcd3c376b8f8dc4acce0f2629a7 --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/acer/aspire_vn7_572g/devicetree.cb M src/mainboard/acer/g43t-am3/devicetree.cb M src/mainboard/apple/macbook21/devicetree.cb M src/mainboard/apple/macbookair4_2/devicetree.cb M src/mainboard/asrock/b75m-itx/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/asrock/h77pro4-m/devicetree.cb M src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb M src/mainboard/asus/p5gc-mx/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb M src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb M src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb M src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb M src/mainboard/biostar/th61-itx/devicetree.cb M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/compulab/intense_pc/devicetree.cb M src/mainboard/dell/e6400/devicetree.cb M src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/foxconn/d41s/devicetree.cb M src/mainboard/foxconn/g41s-k/devicetree.cb M src/mainboard/getac/p470/devicetree.cb M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb M src/mainboard/gigabyte/ga-d510ud/devicetree.cb M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/gigabyte/ga-h61m-series/devicetree.cb M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/beltino/devicetree.cb M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb M src/mainboard/google/butterfly/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/google/link/devicetree.cb M src/mainboard/google/parrot/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/google/puff/variants/baseboard/devicetree.cb M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb M src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/slippy/devicetree.cb M src/mainboard/google/stout/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/hp/280_g2/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb M src/mainboard/hp/elitebook_820_g2/devicetree.cb M src/mainboard/hp/folio_9480m/devicetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb M src/mainboard/hp/z220_series/devicetree.cb M src/mainboard/ibase/mb899/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/devicetree_n.cb M src/mainboard/intel/baskingridge/devicetree.cb M src/mainboard/intel/dcp847ske/devicetree.cb M src/mainboard/intel/dg41wv/devicetree.cb M src/mainboard/intel/dg43gt/devicetree.cb M src/mainboard/intel/dq67sw/devicetree.cb M src/mainboard/intel/emeraldlake2/devicetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/kontron/986lcd-m/devicetree.cb M src/mainboard/kontron/bsl6/devicetree.cb M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb M src/mainboard/lenovo/haswell/variants/w541/devicetree.cb M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t400/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t60/devicetree.cb M src/mainboard/lenovo/thinkcentre_a58/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x200/devicetree.cb M src/mainboard/lenovo/x60/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/msi/ms7707/devicetree.cb M src/mainboard/msi/ms7d25/devicetree.cb M src/mainboard/msi/ms7e06/devicetree.cb M src/mainboard/ocp/deltalake/devicetree.cb M src/mainboard/ocp/tiogapass/devicetree.cb M src/mainboard/prodrive/atlas/devicetree.cb M src/mainboard/protectli/vault_cml/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb M src/mainboard/purism/librem_l1um_v2/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/roda/rk886ex/devicetree.cb M src/mainboard/roda/rk9/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb M src/mainboard/sapphire/pureplatinumh61/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb M src/mainboard/supermicro/x9sae/devicetree.cb M src/mainboard/supermicro/x9scl/devicetree.cb M src/mainboard/system76/addw1/devicetree.cb M src/mainboard/system76/adl/devicetree.cb M src/mainboard/system76/bonw14/devicetree.cb M src/mainboard/system76/cml-u/devicetree.cb M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/kbl-u/devicetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/rpl/devicetree.cb M src/mainboard/system76/tgl-h/devicetree.cb M src/mainboard/system76/tgl-u/devicetree.cb M src/mainboard/system76/whl-u/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/apollolake/chip.h M src/soc/intel/broadwell/chip.h M src/soc/intel/cannonlake/chip.h M src/soc/intel/elkhartlake/chip.h M src/soc/intel/jasperlake/chip.h M src/soc/intel/meteorlake/chip.h M src/soc/intel/skylake/chip.h M src/soc/intel/tigerlake/chip.h M src/soc/intel/xeon_sp/cpx/chip.h M src/soc/intel/xeon_sp/skx/chip.h M src/soc/intel/xeon_sp/spr/chip.h M src/soc/intel/xeon_sp/spr/chipset.cb M src/southbridge/intel/bd82x6x/chip.h A src/southbridge/intel/common/lpc.h M src/southbridge/intel/i82801gx/chip.h M src/southbridge/intel/i82801ix/chip.h M src/southbridge/intel/i82801jx/chip.h M src/southbridge/intel/lynxpoint/chip.h 184 files changed, 420 insertions(+), 394 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/79742/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79742?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic05a7b1e6d0bafcd3c376b8f8dc4acce0f2629a7 Gerrit-Change-Number: 79742 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Evgeny Sorokin <me(a)ch1p.io> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Tim Chu 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1 0

[L] Change in coreboot[main]: devicetree.cb: Use a macro to make IO genx_dec more comprehensible
by Arthur Heymans (Code Review) 28 Dec '23

28 Dec '23

Attention is currently required from: Alexander Couzens, Angel Pons, Christian Walter, Dinesh Gehlot, Eran Mitrani, Eric Lai, Erik van den Bogaert, Evgeny Sorokin, Frans Hendriks, Jakub Czapiga, Jeremy Soller, Johnny Lin, Jonathon Hall, Kapil Porwal, Kevin Keijzer, Lean Sheng Tan, Michael Niewöhner, Michał Kopeć, Michał Żygowski, Morgan Jang, Nicholas Chin, Nick Vaccaro, Nico Huber, Piotr Król, Sean Rhodes, Stefan Ott, Subrata Banik, Tarun, Tim Chu, Tim Crawford, Werner Zeh. Hello Alexander Couzens, Angel Pons, Christian Walter, Dinesh Gehlot, Eran Mitrani, Eric Lai, Erik van den Bogaert, Evgeny Sorokin, Frans Hendriks, Jakub Czapiga, Jeremy Soller, Johnny Lin, Jonathon Hall, Kapil Porwal, Kevin Keijzer, Lean Sheng Tan, Michael Niewöhner, Michał Kopeć, Michał Żygowski, Morgan Jang, Nicholas Chin, Nick Vaccaro, Nico Huber, Piotr Król, Sean Rhodes, Stefan Ott, Subrata Banik, Tarun, Tim Chu, Tim Crawford, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79742?usp=email to look at the new patch set (#2). Change subject: devicetree.cb: Use a macro to make IO genx_dec more comprehensible ...................................................................... devicetree.cb: Use a macro to make IO genx_dec more comprehensible Done using the following command: for devicetree in $(find -name '*.cb'); do sed -i 's/register "gen$[1-4]$_dec" = "0x00$[0-9A-Fa-f]\{2\}$$[0-9A-Fa-f]\{3\}$1"/register "gen\1_dec" = "LPC_IO_DEC(0x\30, 0x\2 | 0x3)"/g' $devicetree; done Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Ic05a7b1e6d0bafcd3c376b8f8dc4acce0f2629a7 --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/acer/aspire_vn7_572g/devicetree.cb M src/mainboard/acer/g43t-am3/devicetree.cb M src/mainboard/apple/macbook21/devicetree.cb M src/mainboard/apple/macbookair4_2/devicetree.cb M src/mainboard/asrock/b75m-itx/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/asrock/h77pro4-m/devicetree.cb M src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb M src/mainboard/asus/p5gc-mx/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb M src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb M src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb M src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb M src/mainboard/biostar/th61-itx/devicetree.cb M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/compulab/intense_pc/devicetree.cb M src/mainboard/dell/e6400/devicetree.cb M src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/foxconn/d41s/devicetree.cb M src/mainboard/foxconn/g41s-k/devicetree.cb M src/mainboard/getac/p470/devicetree.cb M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb M src/mainboard/gigabyte/ga-d510ud/devicetree.cb M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/gigabyte/ga-h61m-series/devicetree.cb M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/beltino/devicetree.cb M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb M src/mainboard/google/butterfly/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/google/link/devicetree.cb M src/mainboard/google/parrot/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/google/puff/variants/baseboard/devicetree.cb M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb M src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/slippy/devicetree.cb M src/mainboard/google/stout/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/hp/280_g2/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb M src/mainboard/hp/elitebook_820_g2/devicetree.cb M src/mainboard/hp/folio_9480m/devicetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb M src/mainboard/hp/z220_series/devicetree.cb M src/mainboard/ibase/mb899/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/devicetree_n.cb M src/mainboard/intel/baskingridge/devicetree.cb M src/mainboard/intel/dcp847ske/devicetree.cb M src/mainboard/intel/dg41wv/devicetree.cb M src/mainboard/intel/dg43gt/devicetree.cb M src/mainboard/intel/dq67sw/devicetree.cb M src/mainboard/intel/emeraldlake2/devicetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/kontron/986lcd-m/devicetree.cb M src/mainboard/kontron/bsl6/devicetree.cb M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb M src/mainboard/lenovo/haswell/variants/w541/devicetree.cb M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t400/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t60/devicetree.cb M src/mainboard/lenovo/thinkcentre_a58/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x200/devicetree.cb M src/mainboard/lenovo/x60/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/msi/ms7707/devicetree.cb M src/mainboard/msi/ms7d25/devicetree.cb M src/mainboard/msi/ms7e06/devicetree.cb M src/mainboard/ocp/deltalake/devicetree.cb M src/mainboard/ocp/tiogapass/devicetree.cb M src/mainboard/prodrive/atlas/devicetree.cb M src/mainboard/protectli/vault_cml/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb M src/mainboard/purism/librem_l1um_v2/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/roda/rk886ex/devicetree.cb M src/mainboard/roda/rk9/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb M src/mainboard/sapphire/pureplatinumh61/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb M src/mainboard/supermicro/x9sae/devicetree.cb M src/mainboard/supermicro/x9scl/devicetree.cb M src/mainboard/system76/addw1/devicetree.cb M src/mainboard/system76/adl/devicetree.cb M src/mainboard/system76/bonw14/devicetree.cb M src/mainboard/system76/cml-u/devicetree.cb M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/kbl-u/devicetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/rpl/devicetree.cb M src/mainboard/system76/tgl-h/devicetree.cb M src/mainboard/system76/tgl-u/devicetree.cb M src/mainboard/system76/whl-u/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/apollolake/chip.h M src/soc/intel/broadwell/chip.h M src/soc/intel/cannonlake/chip.h M src/soc/intel/elkhartlake/chip.h M src/soc/intel/jasperlake/chip.h M src/soc/intel/meteorlake/chip.h M src/soc/intel/skylake/chip.h M src/soc/intel/tigerlake/chip.h M src/soc/intel/xeon_sp/cpx/chip.h M src/soc/intel/xeon_sp/skx/chip.h M src/soc/intel/xeon_sp/spr/chip.h M src/soc/intel/xeon_sp/spr/chipset.cb M src/southbridge/intel/bd82x6x/chip.h A src/southbridge/intel/common/lpc.h M src/southbridge/intel/i82801gx/chip.h M src/southbridge/intel/i82801ix/chip.h M src/southbridge/intel/i82801jx/chip.h M src/southbridge/intel/lynxpoint/chip.h 184 files changed, 381 insertions(+), 355 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/79742/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79742?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic05a7b1e6d0bafcd3c376b8f8dc4acce0f2629a7 Gerrit-Change-Number: 79742 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Evgeny Sorokin <me(a)ch1p.io> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> 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1 0

[L] Change in coreboot[main]: devicetree.cb: Use a macro to make IO genx_dec more comprehensible
by Arthur Heymans (Code Review) 28 Dec '23

28 Dec '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79742?usp=email ) Change subject: devicetree.cb: Use a macro to make IO genx_dec more comprehensible ...................................................................... devicetree.cb: Use a macro to make IO genx_dec more comprehensible Done using the following command: for devicetree in $(find -name '*.cb'); do sed -i 's/register "gen$[1-4]$_dec" = "0x$[0-9A-Fa-f]\{4\}$$[0-9A-Fa-f]\{3\}$1"/register "gen\1_dec" = "LPC_IO_DEC(0x\30, 0x\2 | 0x3)"/g' $devicetree; done Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Ic05a7b1e6d0bafcd3c376b8f8dc4acce0f2629a7 --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/acer/aspire_vn7_572g/devicetree.cb M src/mainboard/acer/g43t-am3/devicetree.cb M src/mainboard/apple/macbook21/devicetree.cb M src/mainboard/apple/macbookair4_2/devicetree.cb M src/mainboard/asrock/b75m-itx/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/asrock/h77pro4-m/devicetree.cb M src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb M src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb M src/mainboard/asus/p5gc-mx/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb M src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb M src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb M src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb M src/mainboard/biostar/th61-itx/devicetree.cb M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/compulab/intense_pc/devicetree.cb M src/mainboard/dell/e6400/devicetree.cb M src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/foxconn/d41s/devicetree.cb M src/mainboard/foxconn/g41s-k/devicetree.cb M src/mainboard/getac/p470/devicetree.cb M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb M src/mainboard/gigabyte/ga-d510ud/devicetree.cb M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/gigabyte/ga-h61m-series/devicetree.cb M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/beltino/devicetree.cb M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb M src/mainboard/google/butterfly/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/google/link/devicetree.cb M src/mainboard/google/parrot/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/google/puff/variants/baseboard/devicetree.cb M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb M src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/slippy/devicetree.cb M src/mainboard/google/stout/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/hp/280_g2/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb M src/mainboard/hp/elitebook_820_g2/devicetree.cb M src/mainboard/hp/folio_9480m/devicetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb M src/mainboard/hp/z220_series/devicetree.cb M src/mainboard/ibase/mb899/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/devicetree_n.cb M src/mainboard/intel/baskingridge/devicetree.cb M src/mainboard/intel/dcp847ske/devicetree.cb M src/mainboard/intel/dg41wv/devicetree.cb M src/mainboard/intel/dg43gt/devicetree.cb M src/mainboard/intel/dq67sw/devicetree.cb M src/mainboard/intel/emeraldlake2/devicetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/kontron/986lcd-m/devicetree.cb M src/mainboard/kontron/bsl6/devicetree.cb M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb M src/mainboard/lenovo/haswell/variants/w541/devicetree.cb M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t400/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t60/devicetree.cb M src/mainboard/lenovo/thinkcentre_a58/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x200/devicetree.cb M src/mainboard/lenovo/x60/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/msi/ms7707/devicetree.cb M src/mainboard/msi/ms7d25/devicetree.cb M src/mainboard/msi/ms7e06/devicetree.cb M src/mainboard/ocp/deltalake/devicetree.cb M src/mainboard/ocp/tiogapass/devicetree.cb M src/mainboard/prodrive/atlas/devicetree.cb M src/mainboard/protectli/vault_cml/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb M src/mainboard/purism/librem_l1um_v2/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/roda/rk886ex/devicetree.cb M src/mainboard/roda/rk9/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb M src/mainboard/sapphire/pureplatinumh61/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb M src/mainboard/supermicro/x9sae/devicetree.cb M src/mainboard/supermicro/x9scl/devicetree.cb M src/mainboard/system76/addw1/devicetree.cb M src/mainboard/system76/adl/devicetree.cb M src/mainboard/system76/bonw14/devicetree.cb M src/mainboard/system76/cml-u/devicetree.cb M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/kbl-u/devicetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/rpl/devicetree.cb M src/mainboard/system76/tgl-h/devicetree.cb M src/mainboard/system76/tgl-u/devicetree.cb M src/mainboard/system76/whl-u/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/apollolake/chip.h M src/soc/intel/broadwell/chip.h M src/soc/intel/cannonlake/chip.h M src/soc/intel/elkhartlake/chip.h M src/soc/intel/jasperlake/chip.h M src/soc/intel/meteorlake/chip.h M src/soc/intel/skylake/chip.h M src/soc/intel/tigerlake/chip.h M src/soc/intel/xeon_sp/cpx/chip.h M src/soc/intel/xeon_sp/skx/chip.h M src/soc/intel/xeon_sp/spr/chip.h M src/soc/intel/xeon_sp/spr/chipset.cb M src/southbridge/intel/bd82x6x/chip.h A src/southbridge/intel/common/lpc.h M src/southbridge/intel/i82801gx/chip.h M src/southbridge/intel/i82801ix/chip.h M src/southbridge/intel/i82801jx/chip.h M src/southbridge/intel/lynxpoint/chip.h 184 files changed, 381 insertions(+), 355 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/79742/1 diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 2695451..f85913c 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -26,8 +26,8 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "gen1_dec" = "0x000c0681" - register "gen2_dec" = "0x000c1641" + register "gen1_dec" = "LPC_IO_DEC(0x0680, 0x000c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x1640, 0x000c | 0x3)" # Disable DPTF register "dptf_enable" = "0" diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb index 0328ec7..cfc84ea 100644 --- a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb +++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb @@ -295,7 +295,7 @@ register "lpc_ioe" = "LPC_IOE_COMA_EN | LPC_IOE_COMB_EN | LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66 | LPC_IOE_SUPERIO_2E_2F | LPC_IOE_EC_4E_4F" # 82h-83h register "gen3_dec" = "0x00040069" # 8Ch-8Fh; EC (sideband): Port 68h/6Ch - register "gen4_dec" = "0x000c1201" # 90h-93h; EC (index): Port 1200h + register "gen4_dec" = "LPC_IO_DEC(0x1200, 0x000c | 0x3)" # 90h-93h; EC (index): Port 1200h # EC/KBC requires continuous mode register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/mainboard/acer/g43t-am3/devicetree.cb b/src/mainboard/acer/g43t-am3/devicetree.cb index 94067a6..f88e79d 100644 --- a/src/mainboard/acer/g43t-am3/devicetree.cb +++ b/src/mainboard/acer/g43t-am3/devicetree.cb @@ -22,7 +22,7 @@ # "Additional LPC IO decode ranges": used for SuperIO's # Environment Controller on 0xa15/0xa16 - register "gen1_dec" = "0x00fc0a01" + register "gen1_dec" = "LPC_IO_DEC(0x0a00, 0x00fc | 0x3)" device pci 19.0 on end # GBE device pci 1a.0 on end # USB diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index fd86e93..a635177 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -57,9 +57,9 @@ register "c3_latency" = "0x23" register "p_cnt_throttling_supported" = "true" - register "gen1_dec" = "0x000c0681" - register "gen2_dec" = "0x000c1641" - register "gen4_dec" = "0x001c0301" + register "gen1_dec" = "LPC_IO_DEC(0x0680, 0x000c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x1640, 0x000c | 0x3)" + register "gen4_dec" = "LPC_IO_DEC(0x0300, 0x001c | 0x3)" device pci 1b.0 on # Audio Controller subsystemid 0x8384 0x7680 diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index c408d5a..16a8295 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -17,10 +17,10 @@ device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "docking_supported" = "0" - register "gen1_dec" = "0x000c0681" - register "gen2_dec" = "0x000c1641" - register "gen3_dec" = "0x001c0301" - register "gen4_dec" = "0x00fc0701" + register "gen1_dec" = "LPC_IO_DEC(0x0680, 0x000c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x1640, 0x000c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0x0300, 0x001c | 0x3)" + register "gen4_dec" = "LPC_IO_DEC(0x0700, 0x00fc | 0x3)" register "gpi7_routing" = "2" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "true" diff --git a/src/mainboard/asrock/b75m-itx/devicetree.cb b/src/mainboard/asrock/b75m-itx/devicetree.cb index 6d4ca2d..2675d0a 100644 --- a/src/mainboard/asrock/b75m-itx/devicetree.cb +++ b/src/mainboard/asrock/b75m-itx/devicetree.cb @@ -17,9 +17,9 @@ subsystemid 0x1849 0x0152 end chip southbridge/intel/bd82x6x - register "gen1_dec" = "0x000c0291" - register "gen2_dec" = "0x000c0241" - register "gen3_dec" = "0x000c0251" + register "gen1_dec" = "LPC_IO_DEC(0x0290, 0x000c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0240, 0x000c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0x0250, 0x000c | 0x3)" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x3f" register "superspeed_capable_ports" = "0x0000000f" diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index e2c898d..d834fd6 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -27,9 +27,9 @@ end chip southbridge/intel/bd82x6x register "docking_supported" = "0" - register "gen1_dec" = "0x000c0291" - register "gen2_dec" = "0x000c0241" - register "gen3_dec" = "0x000c0251" + register "gen1_dec" = "LPC_IO_DEC(0x0290, 0x000c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0240, 0x000c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0x0250, 0x000c | 0x3)" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "false" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index 3eeeafd..8d0b555 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -34,7 +34,7 @@ register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" - register "gen1_dec" = "0x000c0291" # Superio HWM + register "gen1_dec" = "LPC_IO_DEC(0x0290, 0x000c | 0x3)" # Superio HWM device pci 1b.0 on # Audio subsystemid 0x1849 0x3662 diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb index 3b1f7fa..76e14ae 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb @@ -28,7 +28,7 @@ register "ide_enable_primary" = "true" register "gpe0_en" = "0x440" - register "gen1_dec" = "0x000c0291" # Superio HWM + register "gen1_dec" = "LPC_IO_DEC(0x0290, 0x000c | 0x3)" # Superio HWM device pci 1b.0 on # Audio subsystemid 0x1849 0x3662 diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index c041c63..5329de5 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -29,7 +29,7 @@ register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" - register "gen1_dec" = "0x000c0291" # Superio HWM + register "gen1_dec" = "LPC_IO_DEC(0x0290, 0x000c | 0x3)" # Superio HWM device pci 1b.0 on # Audio subsystemid 0x1849 0x3662 diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb index a89388f..267d1f6 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb @@ -27,7 +27,7 @@ register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" - register "gen1_dec" = "0x000c0291" # Superio HWM + register "gen1_dec" = "LPC_IO_DEC(0x0290, 0x000c | 0x3)" # Superio HWM device pci 1b.0 on # Audio subsystemid 0x1849 0x3662 diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb index 353e80b..7526fe6 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb @@ -28,7 +28,7 @@ register "ide_enable_primary" = "true" register "gpe0_en" = "0x440" - register "gen1_dec" = "0x000c0291" # Superio HWM + register "gen1_dec" = "LPC_IO_DEC(0x0290, 0x000c | 0x3)" # Superio HWM device pci 1b.0 on # Audio subsystemid 0x1849 0x3662 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index a6d16f9..1a3f59c 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -144,7 +144,7 @@ subsystemid 0x1849 0x1a43 # Set @0x280-0x2ff I/O Range for SuperIO HWM - register "gen1_dec" = "0x007c0281" + register "gen1_dec" = "LPC_IO_DEC(0x0280, 0x007c | 0x3)" # Set LPC Serial IRQ mode register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/mainboard/asrock/h77pro4-m/devicetree.cb b/src/mainboard/asrock/h77pro4-m/devicetree.cb index 2624c38..d4b6d81 100644 --- a/src/mainboard/asrock/h77pro4-m/devicetree.cb +++ b/src/mainboard/asrock/h77pro4-m/devicetree.cb @@ -11,9 +11,9 @@ subsystemid 0x1849 0x0102 end chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH - register "gen1_dec" = "0x000c0291" - register "gen2_dec" = "0x000c0241" - register "gen3_dec" = "0x000c0251" + register "gen1_dec" = "LPC_IO_DEC(0x0290, 0x000c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0240, 0x000c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0x0250, 0x000c | 0x3)" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x3f" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb b/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb index cb30fc3..f0b33d3 100644 --- a/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb @@ -4,7 +4,7 @@ device domain 0 on subsystemid 0x1043 0x844d inherit chip southbridge/intel/bd82x6x - register "gen1_dec" = "0x000c0291" + register "gen1_dec" = "LPC_IO_DEC(0x0290, 0x000c | 0x3)" device pci 1b.0 on # High Definition Audio controller subsystemid 0x1043 0x8445 end diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb index 5d9635c..760063e 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb @@ -4,7 +4,7 @@ device domain 0 on subsystemid 0x1043 0x844d inherit chip southbridge/intel/bd82x6x - register "gen1_dec" = "0x000c0291" + register "gen1_dec" = "LPC_IO_DEC(0x0290, 0x000c | 0x3)" device pci 1c.0 on end # RP #1 device pci 1c.1 off end # RP #2 diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb index d726131..e3c7aeb 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb @@ -3,7 +3,7 @@ chip northbridge/intel/sandybridge device domain 0 on chip southbridge/intel/bd82x6x - register "gen1_dec" = "0x000c0291" # HWM + register "gen1_dec" = "LPC_IO_DEC(0x0290, 0x000c | 0x3)" # HWM device pci 1c.0 on end # PCIe x1 Port (PCIEX1_1) device pci 1c.1 on end # PCIe x1 Port (PCIEX1_2) diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb index 1b78b9b..c6f2062 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb @@ -4,7 +4,7 @@ register "spd_addresses" = "{0x51, 0, 0x53, 0}" device domain 0 on chip southbridge/intel/bd82x6x - register "gen1_dec" = "0x000c0291" # HWM + register "gen1_dec" = "LPC_IO_DEC(0x0290, 0x000c | 0x3)" # HWM device pci 1c.0 on end # PCIe x1 Port (PCIEX1_1) device pci 1c.1 on end # PCIe x1 Port (PCIEX1_2) diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb index 3518a01..6eddfe4 100644 --- a/src/mainboard/asus/p5gc-mx/devicetree.cb +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -34,7 +34,7 @@ register "p_cnt_throttling_supported" = "false" # SuperIO Power Management Events - register "gen1_dec" = "0x00040291" + register "gen1_dec" = "LPC_IO_DEC(0x0290, 0x0004 | 0x3)" device pci 1b.0 on end # High Definition Audio device pci 1c.0 on end # PCIe diff --git a/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb index 4b1d290..4248112 100644 --- a/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb @@ -17,7 +17,7 @@ register "pcie_slot_implemented" = "0x31" register "gen1_dec" = "0x00000295" - register "gen2_dec" = "0x001c4701" + register "gen2_dec" = "LPC_IO_DEC(0x4700, 0x001c | 0x3)" device pci 19.0 off end # GBE device pci 1a.0 on end # USB diff --git a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb index b1b0106..e9ef714 100644 --- a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb @@ -22,7 +22,7 @@ register "pcie_slot_implemented" = "0x31" register "gen1_dec" = "0x00000295" - register "gen2_dec" = "0x001c4701" + register "gen2_dec" = "LPC_IO_DEC(0x4700, 0x001c | 0x3)" device pci 19.0 off end # GBE device pci 1a.0 on end # USB diff --git a/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb index 602ef02..4eadad3 100644 --- a/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb @@ -22,7 +22,7 @@ register "pcie_slot_implemented" = "0x31" register "gen1_dec" = "0x00000295" - register "gen2_dec" = "0x001c4701" + register "gen2_dec" = "LPC_IO_DEC(0x4700, 0x001c | 0x3)" device pci 19.0 off end # GBE device pci 1a.0 on end # USB diff --git a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb index 6e7d142..3188834 100644 --- a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb @@ -22,7 +22,7 @@ register "pcie_slot_implemented" = "0x31" register "gen1_dec" = "0x00000295" - register "gen2_dec" = "0x001c4701" + register "gen2_dec" = "LPC_IO_DEC(0x4700, 0x001c | 0x3)" device pci 19.0 off end # GBE device pci 1a.0 on end # USB diff --git a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb index 602ef02..4eadad3 100644 --- a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb @@ -22,7 +22,7 @@ register "pcie_slot_implemented" = "0x31" register "gen1_dec" = "0x00000295" - register "gen2_dec" = "0x001c4701" + register "gen2_dec" = "LPC_IO_DEC(0x4700, 0x001c | 0x3)" device pci 19.0 off end # GBE device pci 1a.0 on end # USB diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb index 4de539b..1206ecc 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb @@ -6,7 +6,7 @@ device pci 06.0 on end # PCIEX16_3 (electrical x4) subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x - register "gen1_dec" = "0x000c0291" + register "gen1_dec" = "LPC_IO_DEC(0x0290, 0x000c | 0x3)" device pci 1c.0 on end # RP #1: PCIEX16_4 (electrical x4) device pci 1c.1 off end # RP #2: device pci 1c.2 off end # RP #3: diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb index f20b49c..09da46a 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb @@ -4,7 +4,7 @@ device domain 0 on subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x - register "gen1_dec" = "0x000c0291" + register "gen1_dec" = "LPC_IO_DEC(0x0290, 0x000c | 0x3)" device pci 1c.0 on end # RP #1: PCIEX16_2 (electrical x4) device pci 1c.1 off end # RP #2: device pci 1c.2 off end # RP #3: diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb index c9fd784..a621df6 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb @@ -9,7 +9,7 @@ device domain 0 on subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH - register "gen1_dec" = "0x000c0291" + register "gen1_dec" = "LPC_IO_DEC(0x0290, 0x000c | 0x3)" device pci 1c.0 on end # PCIe Port #1 (PCIe x4 slot) device pci 1c.1 off end # PCIe Port #2 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb index d7aea49..5b97d26 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb @@ -9,7 +9,7 @@ device domain 0 on subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x - register "gen1_dec" = "0x000c0291" + register "gen1_dec" = "LPC_IO_DEC(0x0290, 0x000c | 0x3)" register "gen4_dec" = "0x0000ff29" register "pcie_port_coalesce" = "true" diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb index 77484c7..f5a57e2 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb @@ -5,7 +5,7 @@ subsystemid 0x1043 0x84ca inherit device pci 01.1 on end # PCIEX_16_2 chip southbridge/intel/bd82x6x - register "gen1_dec" = "0x000c0291" + register "gen1_dec" = "LPC_IO_DEC(0x0290, 0x000c | 0x3)" device pci 19.0 on end # Intel Gigabit Ethernet device pci 1c.0 on end # PCIe Port 1 PCIEX_16_3 (electrical x1 or x4) diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb index 6be23fa..dd164e6 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb @@ -4,7 +4,7 @@ device domain 0 on subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x - register "gen1_dec" = "0x000c0291" + register "gen1_dec" = "LPC_IO_DEC(0x0290, 0x000c | 0x3)" device pci 1c.0 on end # RP #1: PCIEX16_2 (electrical x4) device pci 1c.1 off end # RP #2: diff --git a/src/mainboard/biostar/th61-itx/devicetree.cb b/src/mainboard/biostar/th61-itx/devicetree.cb index af9f9b5..d38be38 100644 --- a/src/mainboard/biostar/th61-itx/devicetree.cb +++ b/src/mainboard/biostar/th61-itx/devicetree.cb @@ -10,7 +10,7 @@ device ref igd on end # iGPU chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "gen1_dec" = "0x003c0a01" + register "gen1_dec" = "LPC_IO_DEC(0x0a00, 0x003c | 0x3)" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index 765d17c..682d145 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -104,8 +104,8 @@ smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" end device ref lpc_espi on - register "gen1_dec" = "0x000c0681" - register "gen2_dec" = "0x000c1641" + register "gen1_dec" = "LPC_IO_DEC(0x0680, 0x000c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x1640, 0x000c | 0x3)" register "gen3_dec" = "0x00040069" register "serirq_mode" = "SERIRQ_CONTINUOUS" chip drivers/pc80/tpm diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb index d09c9e0..a142a12 100644 --- a/src/mainboard/compulab/intense_pc/devicetree.cb +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -26,9 +26,9 @@ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "docking_supported" = "1" register "gen1_dec" = "0x0000164d" - register "gen2_dec" = "0x000c0681" - register "gen3_dec" = "0x000406f1" - register "gen4_dec" = "0x000c06a1" + register "gen2_dec" = "LPC_IO_DEC(0x0680, 0x000c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0x06f0, 0x0004 | 0x3)" + register "gen4_dec" = "LPC_IO_DEC(0x06a0, 0x000c | 0x3)" register "gpi7_routing" = "2" register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/e6400/devicetree.cb index bb954cb..eae733d 100644 --- a/src/mainboard/dell/e6400/devicetree.cb +++ b/src/mainboard/dell/e6400/devicetree.cb @@ -63,7 +63,7 @@ [3] = { 10, 0 }, }" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - register "gen1_dec" = "0x007c0901" + register "gen1_dec" = "LPC_IO_DEC(0x0900, 0x007c | 0x3)" device pci 19.0 on end # LAN device pci 1a.0 on end # UHCI diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb index bf04692..cf1170b 100644 --- a/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb +++ b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb @@ -19,10 +19,10 @@ register "alt_gp_smi_en" = "0x0004" register "gpi2_routing" = "1" register "gpi12_routing" = "2" - register "gen1_dec" = "0x007c0a01" - register "gen2_dec" = "0x007c0901" - register "gen3_dec" = "0x003c07e1" - register "gen4_dec" = "0x001c0901" + register "gen1_dec" = "LPC_IO_DEC(0x0a00, 0x007c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0900, 0x007c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0x07e0, 0x003c | 0x3)" + register "gen4_dec" = "LPC_IO_DEC(0x0900, 0x001c | 0x3)" register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 3f71ca9..669031d 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -20,7 +20,7 @@ # CPLD host command ranges are in 0x280-0x2BF # EC PNP registers are at 0x6e and 0x6f - register "gen1_dec" = "0x003c0281" + register "gen1_dec" = "LPC_IO_DEC(0x0280, 0x003c | 0x3)" register "gen3_dec" = "0x0004006d" # LPC serial IRQ diff --git a/src/mainboard/foxconn/d41s/devicetree.cb b/src/mainboard/foxconn/d41s/devicetree.cb index b815835..266537f 100644 --- a/src/mainboard/foxconn/d41s/devicetree.cb +++ b/src/mainboard/foxconn/d41s/devicetree.cb @@ -24,7 +24,7 @@ register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x441" - register "gen1_dec" = "0x00fc0a01" # Environment Controller + register "gen1_dec" = "LPC_IO_DEC(0x0a00, 0x00fc | 0x3)" # Environment Controller device pci 1b.0 on end # Audio device pci 1c.0 on end # PCIe 1 diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb index b63d204..b9dbce1 100644 --- a/src/mainboard/foxconn/g41s-k/devicetree.cb +++ b/src/mainboard/foxconn/g41s-k/devicetree.cb @@ -27,7 +27,7 @@ register "ide_enable_secondary" = "false" register "sata_ports_implemented" = "0x3" - register "gen1_dec" = "0x003c0a01" # Super I/O EC and GPIO + register "gen1_dec" = "LPC_IO_DEC(0x0a00, 0x003c | 0x3)" # Super I/O EC and GPIO device pci 1b.0 on end # Audio device pci 1c.0 on end # PCIe 1 diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index 86bae67..ad7de60 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -45,8 +45,8 @@ register "docking_supported" = "1" register "p_cnt_throttling_supported" = "true" - register "gen1_dec" = "0x001c02e1" - register "gen2_dec" = "0x00fc0601" + register "gen1_dec" = "LPC_IO_DEC(0x02e0, 0x001c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0600, 0x00fc | 0x3)" register "gen3_dec" = "0x00040069" device pci 1b.0 on end # High Definition Audio diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index a903347..313ccd5 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -58,8 +58,8 @@ register "p_cnt_throttling_supported" = "false" - register "gen1_dec" = "0x000c0801" # ??? - register "gen2_dec" = "0x00040291" # Environment Controller + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x000c | 0x3)" # ??? + register "gen2_dec" = "LPC_IO_DEC(0x0290, 0x0004 | 0x3)" # Environment Controller device pci 1b.0 on end # High Definition Audio device pci 1c.0 on end # PCIe diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 3b95843..3059df6 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -12,7 +12,7 @@ end chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH - register "gen1_dec" = "0x003c0a01" + register "gen1_dec" = "LPC_IO_DEC(0x0a00, 0x003c | 0x3)" # Set max SATA speed to 6.0 Gb/s register "sata_port_map" = "0x3f" diff --git a/src/mainboard/gigabyte/ga-d510ud/devicetree.cb b/src/mainboard/gigabyte/ga-d510ud/devicetree.cb index 891594a..8d598e2 100644 --- a/src/mainboard/gigabyte/ga-d510ud/devicetree.cb +++ b/src/mainboard/gigabyte/ga-d510ud/devicetree.cb @@ -23,7 +23,7 @@ register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x441" - register "gen1_dec" = "0x00040291" # Environment Controller + register "gen1_dec" = "LPC_IO_DEC(0x0290, 0x0004 | 0x3)" # Environment Controller device pci 1b.0 on end # HD Audio device pci 1c.0 on end # PCIe 1: Realtek GbE NIC diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 4f6d900..846b4c4 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -29,7 +29,7 @@ register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x40" - register "gen2_dec" = "0x007c0291" # HWM + register "gen2_dec" = "LPC_IO_DEC(0x0290, 0x007c | 0x3)" # HWM device pci 1b.0 on # Audio subsystemid 0x1458 0xa002 diff --git a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb index 8a29171..af33baa 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb @@ -10,7 +10,7 @@ device ref igd on end # iGPU chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "gen1_dec" = "0x003c0a01" + register "gen1_dec" = "LPC_IO_DEC(0x0a00, 0x003c | 0x3)" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index 2ded452..1f2d2fd 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -28,8 +28,8 @@ chip soc/intel/broadwell/pch # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # EC_SMI is GPIO34 register "alt_gp_smi_en" = "0x0004" diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index cdaab35..b2122d6 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -26,7 +26,7 @@ chip southbridge/intel/lynxpoint # SuperIO range is 0x700-0x73f - register "gen2_dec" = "0x003c0701" + register "gen2_dec" = "LPC_IO_DEC(0x0700, 0x003c | 0x3)" register "alt_gp_smi_en" = "0x0000" register "gpe0_en_1" = "0x00000000" diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index 23db754..e67efbc 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -6,10 +6,10 @@ register "pmc_gpe0_dw2" = "GPP_E" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # S0ix enable register "s0ix_enable" = "1" diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 38535a4..1a60920 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -9,10 +9,10 @@ register "pmc_gpe0_dw2" = "GPP_F" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # S0ix enable register "s0ix_enable" = "1" diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 0290181..b995cae 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -6,10 +6,10 @@ register "pmc_gpe0_dw2" = "GPP_F" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # S0ix enable register "s0ix_enable" = "1" diff --git a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb index 4372888..fe303dc 100644 --- a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb @@ -6,10 +6,10 @@ register "pmc_gpe0_dw2" = "GPP_F" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # S0ix enable register "s0ix_enable" = "1" diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index 55bd9c0..c5b45df 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -22,10 +22,10 @@ register "pmc_gpe0_dw2" = "GPP_F" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # S0ix enable register "s0ix_enable" = "1" diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index f3960ca..bc89543 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -64,7 +64,7 @@ register "gen1_dec" = "0x00040069" # EC range is 0x380-0387 - register "gen2_dec" = "0x00040381" + register "gen2_dec" = "LPC_IO_DEC(0x0380, 0x0004 | 0x3)" # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 2631b61..a2bf461 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -56,10 +56,10 @@ register "pmc_gpe0_dw2" = "PMC_GPP_D" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # USB Port Configuration register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C0 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 950dab9..a4613c0 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -9,9 +9,9 @@ register "gpe0_dw2" = "PMC_GPP_D" # EC host command ranges - register "gen1_dec" = "0x00040931" # 0x930-0x937 - register "gen2_dec" = "0x00040941" # 0x940-0x947 - register "gen3_dec" = "0x000c0951" # 0x950-0x95f + register "gen1_dec" = "LPC_IO_DEC(0x0930, 0x0004 | 0x3)" # 0x930-0x937 + register "gen2_dec" = "LPC_IO_DEC(0x0940, 0x0004 | 0x3)" # 0x940-0x947 + register "gen3_dec" = "LPC_IO_DEC(0x0950, 0x000c | 0x3)" # 0x950-0x95f register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index dfa7a6e..35a22d3d 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -30,10 +30,10 @@ register "gpe0_dw2" = "GPP_E" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # FSP Configuration register "SataSalpSupport" = "0" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 46069ce..cd34072 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -53,10 +53,10 @@ register "gpe0_dw2" = "GPP_E" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 58b421c..d055a7a 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -28,8 +28,8 @@ register "gpe0_dw2" = "GPP_E" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index c4679e3..9edd628 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -12,10 +12,10 @@ register "gpe0_dw2" = "PMC_GPP_D" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # FSP configuration register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index 1bf8a2a..edf8b50 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -23,7 +23,7 @@ chip soc/intel/broadwell/pch # SuperIO range is 0x700-0x73f - register "gen2_dec" = "0x003c0701" + register "gen2_dec" = "LPC_IO_DEC(0x0700, 0x003c | 0x3)" register "alt_gp_smi_en" = "0x0000" register "gpe0_en_1" = "0x00000000" diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 88983dc..12019d1 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -59,8 +59,8 @@ # EC range is 0x800-0x9ff # Please note: you MUST not change this unless # you also change romstage.c:pch_enable_lpc - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index 49b40b9..4922ac3 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -57,7 +57,7 @@ register "sata_port_map" = "0x1" # EC range is 0xFD60 (EC_IO) and 0x68/0x6C - register "gen1_dec" = "0x0004fd61" + register "gen1_dec" = "LPC_IO_DEC(0xfd60, 0x0004 | 0x3)" register "gen2_dec" = "0x00040069" # Enable zero-based linear PCIe root port functions diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 4ba644f..e7dc049 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -28,10 +28,10 @@ register "gpe0_dw2" = "GPP_E" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 717ab54..b1ad5e0 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -19,10 +19,10 @@ register "gpe0_dw2" = "GPP_E" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index d1d0441..26c8f7f 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -28,10 +28,10 @@ register "gpe0_dw2" = "GPP_E" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 6cc1f8e..8b12f51 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -28,10 +28,10 @@ register "gpe0_dw2" = "GPP_E" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 5f322b1..50058fd 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -21,10 +21,10 @@ register "gpe0_dw2" = "GPP_E" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 8a3d4fd..887232e 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -28,10 +28,10 @@ register "gpe0_dw2" = "GPP_E" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index db79337..0ec1e0b 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -28,10 +28,10 @@ register "gpe0_dw2" = "GPP_E" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index b7a9674..fafbf41 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -12,10 +12,10 @@ register "gpe0_dw2" = "PMC_GPP_D" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # FSP configuration register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb index aace5ad..77770f9 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb @@ -6,10 +6,10 @@ register "pmc_gpe0_dw2" = "GPP_F" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" register "usb2_ports[0]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 0 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 1 diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb index 7358eeb..306fd4b 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb @@ -6,10 +6,10 @@ register "pmc_gpe0_dw2" = "GPP_F" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" register "usb2_ports[0]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 0 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 1 diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 9f86840..0628f55 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -6,10 +6,10 @@ register "pmc_gpe0_dw2" = "GPP_F" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" register "usb2_ports[0]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 0 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 1 diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb index 625a36b..f1e3958 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb @@ -6,10 +6,10 @@ register "pmc_gpe0_dw2" = "GPP_F" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" register "usb2_ports[0]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 0 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 93ec7cf..6411d48 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -9,9 +9,9 @@ register "gpe0_dw2" = "PMC_GPP_D" # EC host command ranges - register "gen1_dec" = "0x00040931" # 0x930-0x937 - register "gen2_dec" = "0x00040941" # 0x940-0x947 - register "gen3_dec" = "0x000c0951" # 0x950-0x95f + register "gen1_dec" = "LPC_IO_DEC(0x0930, 0x0004 | 0x3)" # 0x930-0x937 + register "gen2_dec" = "LPC_IO_DEC(0x0940, 0x0004 | 0x3)" # 0x940-0x947 + register "gen3_dec" = "LPC_IO_DEC(0x0950, 0x000c | 0x3)" # 0x950-0x95f # FSP configuration register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index b216235..1a525c5 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -9,9 +9,9 @@ register "gpe0_dw2" = "PMC_GPP_D" # EC host command ranges - register "gen1_dec" = "0x00040931" # 0x930-0x937 - register "gen2_dec" = "0x00040941" # 0x940-0x947 - register "gen3_dec" = "0x000c0951" # 0x950-0x95f + register "gen1_dec" = "LPC_IO_DEC(0x0930, 0x0004 | 0x3)" # 0x930-0x937 + register "gen2_dec" = "LPC_IO_DEC(0x0940, 0x0004 | 0x3)" # 0x940-0x947 + register "gen3_dec" = "LPC_IO_DEC(0x0950, 0x000c | 0x3)" # 0x950-0x95f # FSP configuration register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index 0c1222c..b61f042 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -27,8 +27,8 @@ chip southbridge/intel/lynxpoint # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # EC_SMI is GPIO34 register "alt_gp_smi_en" = "0x0004" diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 8fd19fc..581f678 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -71,7 +71,7 @@ register "gen1_dec" = "0x00040069" # EC range is 0x800-0x9ff - register "gen2_dec" = "0x00fc0901" + register "gen2_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # EC range is 0x1610-0x161F register "gen3_dec" = "0x0001C1611" diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 078deb2..2e650ff 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -107,10 +107,10 @@ register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC0)" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # Enable NVMe PCIE 9 using clk 0 register "PcieRpEnable[8]" = "1" diff --git a/src/mainboard/hp/280_g2/devicetree.cb b/src/mainboard/hp/280_g2/devicetree.cb index 3b25a42..c2f3e62 100644 --- a/src/mainboard/hp/280_g2/devicetree.cb +++ b/src/mainboard/hp/280_g2/devicetree.cb @@ -97,7 +97,7 @@ register "serirq_mode" = "SERIRQ_CONTINUOUS" # FIXME: Missing Super I/O HWM config - register "gen1_dec" = "0x000c0291" + register "gen1_dec" = "LPC_IO_DEC(0x0290, 0x000c | 0x3)" end device ref pmc on register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index 993721b..38ec8d1 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -17,8 +17,8 @@ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "docking_supported" = "0" - register "gen1_dec" = "0x00fc0601" - register "gen2_dec" = "0x00fc0801" + register "gen1_dec" = "LPC_IO_DEC(0x0600, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb index 7a62df1..c06c9fd 100644 --- a/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb +++ b/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb @@ -6,8 +6,8 @@ device domain 0x0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "docking_supported" = "0" - register "gen1_dec" = "0x00fc0a01" - register "gen2_dec" = "0x00fc0801" + register "gen1_dec" = "LPC_IO_DEC(0x0a00, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/hp/elitebook_820_g2/devicetree.cb b/src/mainboard/hp/elitebook_820_g2/devicetree.cb index d6cb2ed..b5ea22e 100644 --- a/src/mainboard/hp/elitebook_820_g2/devicetree.cb +++ b/src/mainboard/hp/elitebook_820_g2/devicetree.cb @@ -55,8 +55,8 @@ end device pci 1d.0 on end # USB2 EHCI #1 device pci 1f.0 on # LPC bridge - register "gen1_dec" = "0x007c0201" - register "gen2_dec" = "0x000c0101" + register "gen1_dec" = "LPC_IO_DEC(0x0200, 0x007c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0100, 0x000c | 0x3)" register "gen4_dec" = "0x000402e9" register "gpe0_en_1" = "0x40" register "gpe0_en_2" = "0x600" diff --git a/src/mainboard/hp/folio_9480m/devicetree.cb b/src/mainboard/hp/folio_9480m/devicetree.cb index 6a8e919..34cf5df 100644 --- a/src/mainboard/hp/folio_9480m/devicetree.cb +++ b/src/mainboard/hp/folio_9480m/devicetree.cb @@ -24,8 +24,8 @@ device pci 03.0 on end # Mini-HD audio chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH - register "gen1_dec" = "0x007c0201" - register "gen2_dec" = "0x000c0101" + register "gen1_dec" = "LPC_IO_DEC(0x0200, 0x007c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0100, 0x000c | 0x3)" register "gen4_dec" = "0x000402e9" register "xhci_default" = "1" register "sata_port1_gen3_dtle" = "0x6" diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb index 8f35eee..da3fb89 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb @@ -12,9 +12,9 @@ chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH # mailbox at 0x200/0x201 and PM1 at 0x220 - register "gen1_dec" = "0x007c0201" - register "gen2_dec" = "0x000c0101" - register "gen3_dec" = "0x00fcfe01" + register "gen1_dec" = "LPC_IO_DEC(0x0200, 0x007c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0100, 0x000c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0xfe00, 0x00fc | 0x3)" register "gen4_dec" = "0x000402e9" register "gpi6_routing" = "2" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb index d69a21e..5d22529 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb @@ -12,9 +12,9 @@ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # mailbox at 0x200/0x201 and PM1 at 0x220 - register "gen1_dec" = "0x007c0201" - register "gen2_dec" = "0x000c0101" - register "gen3_dec" = "0x00fcfe01" + register "gen1_dec" = "LPC_IO_DEC(0x0200, 0x007c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0100, 0x000c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0xfe00, 0x00fc | 0x3)" register "gen4_dec" = "0x000402e9" register "gpi6_routing" = "2" register "pcie_hotplug_map" = "{ 0, 1, 0, 0, 0, 0, 0, 0 }" diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb index d89492f..4ecc323 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb @@ -12,9 +12,9 @@ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # mailbox at 0x200/0x201 and PM1 at 0x220 - register "gen1_dec" = "0x007c0201" - register "gen2_dec" = "0x000c0101" - register "gen3_dec" = "0x00fcfe01" + register "gen1_dec" = "LPC_IO_DEC(0x0200, 0x007c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0100, 0x000c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0xfe00, 0x00fc | 0x3)" register "gen4_dec" = "0x000402e9" register "gpi6_routing" = "2" register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb index d911112..6238aa5 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb @@ -12,10 +12,10 @@ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # mailbox at 0x200/0x201 and PM1 at 0x220 - register "gen1_dec" = "0x007c0201" - register "gen2_dec" = "0x000c0101" - register "gen3_dec" = "0x00fcfe01" - register "gen4_dec" = "0x007c0281" + register "gen1_dec" = "LPC_IO_DEC(0x0200, 0x007c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0100, 0x000c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0xfe00, 0x00fc | 0x3)" + register "gen4_dec" = "LPC_IO_DEC(0x0280, 0x007c | 0x3)" register "gpi6_routing" = "2" register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" register "sata_port_map" = "0x21" diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb index 02dc6a4..873668c 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb @@ -12,9 +12,9 @@ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # mailbox at 0x200/0x201 and PM1 at 0x220 - register "gen1_dec" = "0x007c0201" - register "gen2_dec" = "0x000c0101" - register "gen3_dec" = "0x00fcfe01" + register "gen1_dec" = "LPC_IO_DEC(0x0200, 0x007c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0100, 0x000c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0xfe00, 0x00fc | 0x3)" register "gen4_dec" = "0x000402e9" register "gpi6_routing" = "2" register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb index 729db13..9180924 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb @@ -12,9 +12,9 @@ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # mailbox at 0x200/0x201 and PM1 at 0x220 - register "gen1_dec" = "0x007c0201" - register "gen2_dec" = "0x000c0101" - register "gen3_dec" = "0x00fcfe01" + register "gen1_dec" = "LPC_IO_DEC(0x0200, 0x007c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0100, 0x000c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0xfe00, 0x00fc | 0x3)" register "gen4_dec" = "0x000402e9" register "gpi6_routing" = "2" register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb index 02ee795..8ee3ca2 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb @@ -14,9 +14,9 @@ chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH register "docking_supported" = "0" # mailbox at 0x200/0x201 and PM1 at 0x220 - register "gen1_dec" = "0x007c0201" - register "gen2_dec" = "0x000c0101" - register "gen3_dec" = "0x00fcfe01" + register "gen1_dec" = "LPC_IO_DEC(0x0200, 0x007c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0100, 0x000c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0xfe00, 0x00fc | 0x3)" register "gen4_dec" = "0x000402e9" register "gpi6_routing" = "2" register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb index 1eb9c4c..42c939a 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb @@ -12,9 +12,9 @@ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # mailbox at 0x200/0x201 and PM1 at 0x220 - register "gen1_dec" = "0x007c0201" - register "gen2_dec" = "0x000c0101" - register "gen3_dec" = "0x00fcfe01" + register "gen1_dec" = "LPC_IO_DEC(0x0200, 0x007c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0100, 0x000c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0xfe00, 0x00fc | 0x3)" register "gen4_dec" = "0x000402e9" register "gpi6_routing" = "2" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb index 3289588..6aff5fc 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb @@ -10,9 +10,9 @@ device pci 02.0 on end # iGPU chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "gen1_dec" = "0x007c0201" - register "gen2_dec" = "0x000c0101" - register "gen3_dec" = "0x00fcfe01" + register "gen1_dec" = "LPC_IO_DEC(0x0200, 0x007c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0100, 0x000c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0xfe00, 0x00fc | 0x3)" register "gen4_dec" = "0x000402e9" register "gpi6_routing" = "2" register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb index 68b6daa..ac06fa9 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb @@ -12,9 +12,9 @@ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # mailbox at 0x200/0x201 and PM1 at 0x220 - register "gen1_dec" = "0x007c0201" - register "gen2_dec" = "0x000c0101" - register "gen3_dec" = "0x00fcfe01" + register "gen1_dec" = "LPC_IO_DEC(0x0200, 0x007c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0100, 0x000c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0xfe00, 0x00fc | 0x3)" register "gen4_dec" = "0x000402e9" register "gpi6_routing" = "2" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" diff --git a/src/mainboard/hp/z220_series/devicetree.cb b/src/mainboard/hp/z220_series/devicetree.cb index f02ff76..9e9d92f 100644 --- a/src/mainboard/hp/z220_series/devicetree.cb +++ b/src/mainboard/hp/z220_series/devicetree.cb @@ -18,8 +18,8 @@ chip southbridge/intel/bd82x6x # Intel Series 7 PCH register "docking_supported" = "0" - register "gen1_dec" = "0x00fc0601" - register "gen2_dec" = "0x00fc0801" + register "gen1_dec" = "LPC_IO_DEC(0x0600, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index 93f3640..573db32 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -35,8 +35,8 @@ register "c3_latency" = "85" register "p_cnt_throttling_supported" = "false" - register "gen1_dec" = "0x00fc0291" - register "gen4_dec" = "0x00000301" + register "gen1_dec" = "LPC_IO_DEC(0x0290, 0x00fc | 0x3)" + register "gen4_dec" = "LPC_IO_DEC(0x0300, 0x0000 | 0x3)" #device pci 1b.0 on end # High Definition Audio device pci 1c.0 on end # PCIe diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 68c0754..1686aed 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -42,10 +42,10 @@ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # Enable PCH PCIE RP 5 using CLK 2 register "pch_pcie_rp[PCH_RP(5)]" = "{ diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 70a8706..23ddebe 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -40,10 +40,10 @@ register "cnvi_bt_core" = "true" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" #Enable PCH PCIE RP 4 using CLK 5 register "pch_pcie_rp[PCH_RP(4)]" = "{ diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index 6776284..1981d40 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -38,10 +38,10 @@ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # Enable PCH PCIE RP 7 using CLK 3 register "pch_pcie_rp[PCH_RP(7)]" = "{ diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index 3226170..d4f9fdf 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -33,7 +33,7 @@ register "sata_port_map" = "0x3f" # SuperIO range is 0x700-0x73f - register "gen2_dec" = "0x003c0701" + register "gen2_dec" = "LPC_IO_DEC(0x0700, 0x003c | 0x3)" device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb index f4e948f..c93d60a 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/dcp847ske/devicetree.cb @@ -41,7 +41,7 @@ register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" - register "gen1_dec" = "0x00fc0a01" # SuperIO @0xa00-0xaff + register "gen1_dec" = "LPC_IO_DEC(0x0a00, 0x00fc | 0x3)" # SuperIO @0xa00-0xaff device ref xhci off end # USB xHCI device ref mei1 on end # Management Engine Interface 1 diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index 49d6f8b..0892b69 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -45,7 +45,7 @@ register "ide_enable_primary" = "true" register "gpe0_en" = "0x440" - register "gen1_dec" = "0x00fc0a01" # HWM + register "gen1_dec" = "LPC_IO_DEC(0x0a00, 0x00fc | 0x3)" # HWM device pci 1b.0 on # Audio subsystemid 0x8086 0x5756 diff --git a/src/mainboard/intel/dg43gt/devicetree.cb b/src/mainboard/intel/dg43gt/devicetree.cb index c33509b..ff09dba 100644 --- a/src/mainboard/intel/dg43gt/devicetree.cb +++ b/src/mainboard/intel/dg43gt/devicetree.cb @@ -20,8 +20,8 @@ # Enable PCIe ports 0,2,3 as slots. register "pcie_slot_implemented" = "0xb" - register "gen1_dec" = "0x00fc0601" - register "gen2_dec" = "0x00fc0291" + register "gen1_dec" = "LPC_IO_DEC(0x0600, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0290, 0x00fc | 0x3)" device pci 19.0 on end # GBE device pci 1a.0 on end # USB diff --git a/src/mainboard/intel/dq67sw/devicetree.cb b/src/mainboard/intel/dq67sw/devicetree.cb index f29b772..540aeb8 100644 --- a/src/mainboard/intel/dq67sw/devicetree.cb +++ b/src/mainboard/intel/dq67sw/devicetree.cb @@ -9,7 +9,7 @@ device ref igd on end # iGPU chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "gen1_dec" = "0x000c0291" + register "gen1_dec" = "LPC_IO_DEC(0x0290, 0x000c | 0x3)" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x3f" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index e75505e..b1533ee 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -53,11 +53,11 @@ register "sata_port_map" = "0x3f" - register "gen1_dec" = "0x00fc1601" + register "gen1_dec" = "LPC_IO_DEC(0x1600, 0x00fc | 0x3)" # runtime_port registers - register "gen2_dec" = "0x000c0181" + register "gen2_dec" = "LPC_IO_DEC(0x0180, 0x000c | 0x3)" # SuperIO range is 0x700-0x73f - register "gen3_dec" = "0x003c0701" + register "gen3_dec" = "LPC_IO_DEC(0x0700, 0x003c | 0x3)" device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 957ab1d..27685e1 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -48,10 +48,10 @@ register "pch_isclk" = "1" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # Skip the CPU replacement check register "SkipCpuReplacementCheck" = "1" diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index b015fc6..3a229b4 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -14,7 +14,7 @@ register "gpe0_dw2" = "GPP_E" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index 4a1c67b..18c79fd 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -4,7 +4,7 @@ register "gpe0_dw0" = "GPP_C" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen2_dec" = "0x000c0201" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # FSP Configuration register "DspEnable" = "1" diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index f7baaa8..ed1b61432 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -11,7 +11,7 @@ register "deep_s5_enable_dc" = "1" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen2_dec" = "0x000c0201" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 0d9331b..de96236 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -14,8 +14,8 @@ register "gpe0_dw2" = "GPP_E" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index a0f27f0..aea64f8 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -16,10 +16,10 @@ register "pmc_gpe0_dw2" = "GPP_E" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoPci, diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 932a5c7..e08998a 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -36,10 +36,10 @@ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # Enable PCH PCIE RP 5 using CLK 1 register "pch_pcie_rp[PCH_RP(5)]" = "{ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 1af05c4..62f8fc2 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -32,10 +32,10 @@ register "CpuReplacementCheck" = "1" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" register "PcieRpEnable[2]" = "1" register "PcieRpEnable[3]" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index ad1a45d..2a0e8e6 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -33,10 +33,10 @@ register "CpuReplacementCheck" = "1" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" register "PcieRpEnable[2]" = "1" register "PcieRpEnable[3]" = "1" diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index 5e392e6..0eb8c24 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -36,10 +36,10 @@ register "p_cnt_throttling_supported" = "false" # ICH-7 generic decode IO ports range for LPC - register "gen1_dec" = "0x00fc0a01" # HWM + register "gen1_dec" = "LPC_IO_DEC(0x0a00, 0x00fc | 0x3)" # HWM register "gen2_dec" = "0x000403e9" # COM3 register "gen3_dec" = "0x000402e9" # COM4 - register "gen4_dec" = "0x00000301" # ?? + register "gen4_dec" = "LPC_IO_DEC(0x0300, 0x0000 | 0x3)" # ?? device pci 1b.0 on end # High Definition Audio device pci 1c.0 on end # Ethernet 1 diff --git a/src/mainboard/kontron/bsl6/devicetree.cb b/src/mainboard/kontron/bsl6/devicetree.cb index 08b90ce..f9f407c 100644 --- a/src/mainboard/kontron/bsl6/devicetree.cb +++ b/src/mainboard/kontron/bsl6/devicetree.cb @@ -100,7 +100,7 @@ register "serirq_mode" = "SERIRQ_CONTINUOUS" # EC/kempld at 0xa80/0xa81 - register "gen1_dec" = "0x00000a81" + register "gen1_dec" = "LPC_IO_DEC(0x0a80, 0x0000 | 0x3)" chip drivers/pc80/tpm device pnp 0c31.0 on end diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index a035628..ddd8e0e 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -45,7 +45,7 @@ register "sata_interface_speed_support" = "0x3" # TODO: Enable generic LPC decodes... - register "gen1_dec" = "0x001c02e1" + register "gen1_dec" = "LPC_IO_DEC(0x02e0, 0x001c | 0x3)" #register "gen2_dec" = "0x00000000" #register "gen3_dec" = "0x00000000" #register "gen4_dec" = "0x00000000" diff --git a/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb b/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb index f8467c7..265897f 100644 --- a/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb +++ b/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb @@ -27,9 +27,9 @@ device pci 03.0 on end # Mini-HD audio chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH - register "gen1_dec" = "0x007c1601" - register "gen2_dec" = "0x000c15e1" - register "gen4_dec" = "0x000c06a1" + register "gen1_dec" = "LPC_IO_DEC(0x1600, 0x007c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x15e0, 0x000c | 0x3)" + register "gen4_dec" = "LPC_IO_DEC(0x06a0, 0x000c | 0x3)" register "gpi13_routing" = "2" register "gpi1_routing" = "2" # 0(HDD), 1(M.2), 5(ODD) diff --git a/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb b/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb index 0d705fb..4d22b7e 100644 --- a/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb +++ b/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb @@ -28,10 +28,10 @@ device pci 03.0 on end # Mini-HD chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH - register "gen1_dec" = "0x007c1601" - register "gen2_dec" = "0x000c15e1" - register "gen3_dec" = "0x00040291" - register "gen4_dec" = "0x000c06a1" + register "gen1_dec" = "LPC_IO_DEC(0x1600, 0x007c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x15e0, 0x000c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0x0290, 0x0004 | 0x3)" + register "gen4_dec" = "LPC_IO_DEC(0x06a0, 0x000c | 0x3)" register "gpi13_routing" = "2" register "gpi1_routing" = "2" # 0(HDD), 1(I/O Subcard M.2), 4(WWAN/SSD M.2), 5(ODD) diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index ead7e0b..40e7cf9 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -22,9 +22,9 @@ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "docking_supported" = "1" - register "gen1_dec" = "0x007c1611" + register "gen1_dec" = "LPC_IO_DEC(0x1610, 0x007c | 0x3)" register "gen2_dec" = "0x00040069" - register "gen3_dec" = "0x000c0701" + register "gen3_dec" = "LPC_IO_DEC(0x0700, 0x000c | 0x3)" register "gen4_dec" = "0x00000000" register "gpi13_routing" = "2" register "gpi6_routing" = "2" diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index eae9696..56f31d8 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -22,9 +22,9 @@ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "docking_supported" = "1" register "gen1_dec" = "0x00000000" - register "gen2_dec" = "0x000c0701" + register "gen2_dec" = "LPC_IO_DEC(0x0700, 0x000c | 0x3)" register "gen3_dec" = "0x000c0069" - register "gen4_dec" = "0x000c06a1" + register "gen4_dec" = "LPC_IO_DEC(0x06a0, 0x000c | 0x3)" register "gpi13_routing" = "2" register "gpi7_routing" = "2" register "pcie_hotplug_map" = "{ 0, 1, 0, 1, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 259c3e1..b0b0580 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -65,9 +65,9 @@ # Maybe we should set less for Mini PCIe. register "pcie_power_limits" = "{ { 10, 0 }, { 10, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 }, { 0, 0 } }" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - register "gen1_dec" = "0x007c1601" - register "gen2_dec" = "0x000c15e1" - register "gen3_dec" = "0x001c1681" + register "gen1_dec" = "LPC_IO_DEC(0x1600, 0x007c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x15e0, 0x000c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0x1680, 0x001c | 0x3)" device pci 19.0 on end # LAN device pci 1a.0 on # UHCI diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 6492542..5b4dbe7 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -21,9 +21,9 @@ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "docking_supported" = "1" - register "gen1_dec" = "0x000c15e1" - register "gen2_dec" = "0x007c1601" - register "gen3_dec" = "0x000c06a1" + register "gen1_dec" = "LPC_IO_DEC(0x15e0, 0x000c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x1600, 0x007c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0x06a0, 0x000c | 0x3)" register "gpi13_routing" = "2" register "gpi1_routing" = "2" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 25782e97..c262f8d 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -63,9 +63,9 @@ register "docking_supported" = "true" register "p_cnt_throttling_supported" = "true" - register "gen1_dec" = "0x007c1601" - register "gen2_dec" = "0x000c15e1" - register "gen3_dec" = "0x001c1681" + register "gen1_dec" = "LPC_IO_DEC(0x1600, 0x007c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x15e0, 0x000c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0x1680, 0x001c | 0x3)" device pci 1b.0 on # Audio Controller subsystemid 0x17aa 0x2010 diff --git a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb index 4afbec9..cfdc008 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb +++ b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb @@ -26,7 +26,7 @@ register "ide_enable_primary" = "true" register "gpe0_en" = "0x440" - register "gen1_dec" = "0x00fc0a01" + register "gen1_dec" = "LPC_IO_DEC(0x0a00, 0x00fc | 0x3)" device pci 1b.0 on end # Audio device pci 1c.0 on end # PCIe 1 diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index 96385ed..eb74b91 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -35,10 +35,10 @@ # Set max SATA speed to 6.0 Gb/s register "sata_interface_speed_support" = "0x3" - register "gen1_dec" = "0x007c1611" + register "gen1_dec" = "LPC_IO_DEC(0x1610, 0x007c | 0x3)" register "gen2_dec" = "0x00040069" - register "gen3_dec" = "0x000c0701" - register "gen4_dec" = "0x000c06a1" + register "gen3_dec" = "LPC_IO_DEC(0x0700, 0x000c | 0x3)" + register "gen4_dec" = "LPC_IO_DEC(0x06a0, 0x000c | 0x3)" register "xhci_switchable_ports" = "0xf" register "superspeed_capable_ports" = "0xf" diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 7871cfd..7700737 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -58,9 +58,9 @@ # Set thermal throttling to 75%. register "throttle_duty" = "THTL_75_0" - register "gen1_dec" = "0x007c1601" - register "gen2_dec" = "0x000c15e1" - register "gen3_dec" = "0x001c1681" + register "gen1_dec" = "LPC_IO_DEC(0x1600, 0x007c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x15e0, 0x000c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0x1680, 0x001c | 0x3)" device pci 19.0 on end # LAN device pci 1a.0 on # UHCI diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 0e1e5fc..749481c 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -57,9 +57,9 @@ register "docking_supported" = "true" register "p_cnt_throttling_supported" = "true" - register "gen1_dec" = "0x007c1601" - register "gen2_dec" = "0x000c15e1" - register "gen3_dec" = "0x001c1681" + register "gen1_dec" = "LPC_IO_DEC(0x1600, 0x007c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x15e0, 0x000c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0x1680, 0x001c | 0x3)" device pci 1b.0 on # Audio Controller subsystemid 0x17aa 0x2010 diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index cdddf3d..f9df03c 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -25,9 +25,9 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "gen1_dec" = "0x007c0a01" # EC 0xa00-0xa7f - register "gen2_dec" = "0x000c03e1" # COM3 port 0x3e0 - 0x3ef - register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff + register "gen1_dec" = "LPC_IO_DEC(0x0a00, 0x007c | 0x3)" # EC 0xa00-0xa7f + register "gen2_dec" = "LPC_IO_DEC(0x03e0, 0x000c | 0x3)" # COM3 port 0x3e0 - 0x3ef + register "gen3_dec" = "LPC_IO_DEC(0x02e0, 0x00fc | 0x3)" # COM2/4/5/6 ports 0x2e0 - 0x2ff # Disable DPTF register "dptf_enable" = "0" diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index 90eea95..8c04241 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -9,8 +9,8 @@ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "docking_supported" = "0" - register "gen1_dec" = "0x000c0291" - register "gen2_dec" = "0x000c0a01" + register "gen1_dec" = "LPC_IO_DEC(0x0290, 0x000c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0a00, 0x000c | 0x3)" register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index f0c8d2d..2610a60 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -42,10 +42,10 @@ register "usb3_ports[9]" = "USB3_PORT_EMPTY" # LPC generic I/O ranges - register "gen1_dec" = "0x00fc0201" - register "gen2_dec" = "0x003c0a01" - register "gen3_dec" = "0x000c03f1" - register "gen4_dec" = "0x000c0081" + register "gen1_dec" = "LPC_IO_DEC(0x0200, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0a00, 0x003c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0x03f0, 0x000c | 0x3)" + register "gen4_dec" = "LPC_IO_DEC(0x0080, 0x000c | 0x3)" register "sata_salp_support" = "1" diff --git a/src/mainboard/msi/ms7e06/devicetree.cb b/src/mainboard/msi/ms7e06/devicetree.cb index 65ba314..ce11c86 100644 --- a/src/mainboard/msi/ms7e06/devicetree.cb +++ b/src/mainboard/msi/ms7e06/devicetree.cb @@ -197,10 +197,10 @@ "M2_2" "SlotDataBusWidth4X" end device ref pch_espi on - register "gen1_dec" = "0x00fc0201" - register "gen2_dec" = "0x003c0a01" - register "gen3_dec" = "0x000c03f1" - register "gen4_dec" = "0x000c0081" + register "gen1_dec" = "LPC_IO_DEC(0x0200, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0a00, 0x003c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0x03f0, 0x000c | 0x3)" + register "gen4_dec" = "LPC_IO_DEC(0x0080, 0x000c | 0x3)" chip superio/nuvoton/nct6687d device pnp 4e.1 off end # Parallel port diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb index 7d5839e..81d1c1a 100644 --- a/src/mainboard/ocp/deltalake/devicetree.cb +++ b/src/mainboard/ocp/deltalake/devicetree.cb @@ -37,8 +37,8 @@ register "vtd_support" = "1" register "x2apic" = "1" - register "gen1_dec" = "0x00fc0601" # BIC in-band update support - register "gen2_dec" = "0x000c0ca1" # IPMI KCS + register "gen1_dec" = "LPC_IO_DEC(0x0600, 0x00fc | 0x3)" # BIC in-band update support + register "gen2_dec" = "LPC_IO_DEC(0x0ca0, 0x000c | 0x3)" # IPMI KCS # configure PCH PCIe port register "pch_pci_port[8]" = "{ diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index fbf0662..424f866 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -38,7 +38,7 @@ register "coherency_support" = "1" register "ats_support" = "1" - register "gen2_dec" = "0x000c0ca1" # IPMI KCS + register "gen2_dec" = "LPC_IO_DEC(0x0ca0, 0x000c | 0x3)" # IPMI KCS device cpu_cluster 0 on end diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb index 1c4af58..c0a57c6 100644 --- a/src/mainboard/prodrive/atlas/devicetree.cb +++ b/src/mainboard/prodrive/atlas/devicetree.cb @@ -9,12 +9,12 @@ register "pmc_gpe0_dw2" = "GPP_E" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + register "gen1_dec" = "LPC_IO_DEC(0x0800, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0200, 0x000c | 0x3)" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "LPC_IO_DEC(0x0900, 0x00fc | 0x3)" # EC EMI 0 range is 0xc00 - 0xc0f - register "gen4_dec" = "0x000c0c01" + register "gen4_dec" = "LPC_IO_DEC(0x0c00, 0x000c | 0x3)" # SaGv Configuration register "sagv" = "CONFIG(ATLAS_ENABLE_SAGV) ? SaGv_Enabled : SaGv_Disabled" diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb index dd04aa9..9ccde12 100644 --- a/src/mainboard/protectli/vault_cml/devicetree.cb +++ b/src/mainboard/protectli/vault_cml/devicetree.cb @@ -4,10 +4,10 @@ register "cpu_pl2_4_cfg" = "baseline" - register "gen1_dec" = "0x00fc0201" - register "gen2_dec" = "0x007c0a01" - register "gen3_dec" = "0x000c03e1" - register "gen4_dec" = "0x001c02e1" + register "gen1_dec" = "LPC_IO_DEC(0x0200, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0a00, 0x007c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0x03e0, 0x000c | 0x3)" + register "gen4_dec" = "LPC_IO_DEC(0x02e0, 0x001c | 0x3)" # GPIO register "PchUnlockGpioPads" = "1" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 092115c..c5ebdd1 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -12,10 +12,10 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "gen1_dec" = "0x00fc0201" - register "gen2_dec" = "0x007c0a01" - register "gen3_dec" = "0x000c03e1" - register "gen4_dec" = "0x001c02e1" + register "gen1_dec" = "LPC_IO_DEC(0x0200, 0x00fc | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0a00, 0x007c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0x03e0, 0x000c | 0x3)" + register "gen4_dec" = "LPC_IO_DEC(0x02e0, 0x001c | 0x3)" register "eist_enable" = "1" diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index 45350b6..4e64779 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -31,7 +31,7 @@ chip soc/intel/broadwell/pch # EC host command ranges are in 0x380-0x383 & 0x80-0x8f - register "gen1_dec" = "0x00000381" + register "gen1_dec" = "LPC_IO_DEC(0x0380, 0x0000 | 0x3)" device pci 13.0 off end # Smart Sound Audio DSP device pci 14.0 on end # USB3 XHCI diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb index ef35ac0..2cffc86 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb @@ -188,9 +188,9 @@ # Address 0x88: Decode 0x68 - 0x6F (EC PM channel) register "gen1_dec" = "0x00040069" # Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command) - register "gen2_dec" = "0x00fc0e01" + register "gen2_dec" = "LPC_IO_DEC(0x0e00, 0x00fc | 0x3)" # Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug) - register "gen3_dec" = "0x00fc0f01" + register "gen3_dec" = "LPC_IO_DEC(0x0f00, 0x00fc | 0x3)" chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/purism/librem_l1um_v2/devicetree.cb b/src/mainboard/purism/librem_l1um_v2/devicetree.cb index 0144f22..e23c9ea 100644 --- a/src/mainboard/purism/librem_l1um_v2/devicetree.cb +++ b/src/mainboard/purism/librem_l1um_v2/devicetree.cb @@ -257,9 +257,9 @@ device pci 1f.0 on # LPC Interface # This board has a lot of SuperIO LDNs with I/O BARs, the LPC generic # I/O ranges must be configured manually. - register "gen1_dec" = "0x000c0ca1" # IPMI: ca0-caf - register "gen2_dec" = "0x007c0a01" # ASpeed SuperIO SWC and mailbox: a00-a7f - register "gen3_dec" = "0x00040291" # Nuvoton SuperIO HW monitor: 290-297 + register "gen1_dec" = "LPC_IO_DEC(0x0ca0, 0x000c | 0x3)" # IPMI: ca0-caf + register "gen2_dec" = "LPC_IO_DEC(0x0a00, 0x007c | 0x3)" # ASpeed SuperIO SWC and mailbox: a00-a7f + register "gen3_dec" = "LPC_IO_DEC(0x0290, 0x0004 | 0x3)" # Nuvoton SuperIO HW monitor: 290-297 # AST2500 Super IO UART1 requires continuous mode register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 1928d15..0e45bc3 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -35,7 +35,7 @@ register "gpe0_dw2" = "GPP_E" # EC host command ranges are in 0x380-0x383 & 0x80-0x8f - register "gen1_dec" = "0x00000381" + register "gen1_dec" = "LPC_IO_DEC(0x0380, 0x0000 | 0x3)" # Disable DPTF register "dptf_enable" = "0" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index f88c99d..3413e50 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -15,8 +15,8 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "gen1_dec" = "0x000c0681" - register "gen2_dec" = "0x000c1641" + register "gen1_dec" = "LPC_IO_DEC(0x0680, 0x000c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x1640, 0x000c | 0x3)" # Disable DPTF register "dptf_enable" = "0" diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 52c96de..a0d083b 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -44,8 +44,8 @@ register "ide_enable_primary" = "true" register "ide_enable_secondary" = "false" - register "gen1_dec" = "0x001c02e1" # COM3, COM4 - register "gen2_dec" = "0x00fc0601" # ?? + register "gen1_dec" = "LPC_IO_DEC(0x02e0, 0x001c | 0x3)" # COM3, COM4 + register "gen2_dec" = "LPC_IO_DEC(0x0600, 0x00fc | 0x3)" # ?? register "gen3_dec" = "0x00040069" # EC decode ?? device pci 1b.0 off end # High Definition Audio diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb index e070ae1..7851b41 100644 --- a/src/mainboard/roda/rk9/devicetree.cb +++ b/src/mainboard/roda/rk9/devicetree.cb @@ -51,7 +51,7 @@ # Maybe we should set less for Mini PCIe. register "pcie_power_limits" = "{ { 10, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 } }" - register "gen1_dec" = "0x000c0601" + register "gen1_dec" = "LPC_IO_DEC(0x0600, 0x000c | 0x3)" device pci 19.0 off end # LAN device pci 1a.0 on end # UHCI diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index 9dae3ff..37cbb7e 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -54,7 +54,7 @@ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # LPC i/o generic decodes - register "gen1_dec" = "0x003c0a01" # ITE environment controller + register "gen1_dec" = "LPC_IO_DEC(0x0a00, 0x003c | 0x3)" # ITE environment controller register "gen2_dec" = "0x000403e9" # additional com port register "gen3_dec" = "0x000402e9" # additional com port diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index a8efd67..3e808cb 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -53,9 +53,9 @@ register "sata_port_map" = "0x1" # EC range is 0xa00-0xa3f - register "gen1_dec" = "0x003c0a01" - register "gen2_dec" = "0x003c0b01" - register "gen3_dec" = "0x00fc1601" + register "gen1_dec" = "LPC_IO_DEC(0x0a00, 0x003c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0b00, 0x003c | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0x1600, 0x00fc | 0x3)" device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index ae3aab5..d4809ff 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -50,9 +50,9 @@ register "sata_port_map" = "0x3" - register "gen1_dec" = "0x00fc1601" + register "gen1_dec" = "LPC_IO_DEC(0x1600, 0x00fc | 0x3)" # SuperIO range is 0x700-0x73f - register "gen2_dec" = "0x003c0701" + register "gen2_dec" = "LPC_IO_DEC(0x0700, 0x003c | 0x3)" device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index 87d1532..affe21a 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -4,8 +4,8 @@ register "spd_addresses" = "{0x50, 0, 0x51, 0}" device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "gen1_dec" = "0x000c0291" - register "gen2_dec" = "0x000c0a01" + register "gen1_dec" = "LPC_IO_DEC(0x0290, 0x000c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x0a00, 0x000c | 0x3)" register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb index 98bfb04..84527a3 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb @@ -8,8 +8,8 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "gen1_dec" = "0x007c0a01" # Super IO SWC - register "gen2_dec" = "0x000c0ca1" # IPMI KCS + register "gen1_dec" = "LPC_IO_DEC(0x0a00, 0x007c | 0x3)" # Super IO SWC + register "gen2_dec" = "LPC_IO_DEC(0x0ca0, 0x000c | 0x3)" # IPMI KCS # Additional FSP Configuration # This board has an IGD with no output. diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index b46b220..269f399 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -8,8 +8,8 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "gen1_dec" = "0x007c0a01" # Super IO SWC - register "gen2_dec" = "0x000c0ca1" # IPMI KCS + register "gen1_dec" = "LPC_IO_DEC(0x0a00, 0x007c | 0x3)" # Super IO SWC + register "gen2_dec" = "LPC_IO_DEC(0x0ca0, 0x000c | 0x3)" # IPMI KCS # FIXME: find out why FSP crashes without this register "PchHdaVcType" = "Vc1" diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index 29252fe..0d0b1e5 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -8,8 +8,8 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "gen1_dec" = "0x007c0a01" # Super IO SWC - register "gen2_dec" = "0x000c0ca1" # IPMI KCS + register "gen1_dec" = "LPC_IO_DEC(0x0a00, 0x007c | 0x3)" # Super IO SWC + register "gen2_dec" = "LPC_IO_DEC(0x0ca0, 0x000c | 0x3)" # IPMI KCS register "usb2_ports" = "{ [0] = USB2_PORT_MID(OC3), /* USB 9 (3.0) */ diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb index 29babda..4561fc7 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb @@ -8,8 +8,8 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "gen1_dec" = "0x007c0a01" # Super IO SWC - register "gen2_dec" = "0x000c0ca1" # IPMI KCS + register "gen1_dec" = "LPC_IO_DEC(0x0a00, 0x007c | 0x3)" # Super IO SWC + register "gen2_dec" = "LPC_IO_DEC(0x0ca0, 0x000c | 0x3)" # IPMI KCS # Additional FSP Configuration # This board has an IGD with no output. diff --git a/src/mainboard/supermicro/x9sae/devicetree.cb b/src/mainboard/supermicro/x9sae/devicetree.cb index f518381..9aaef9e 100644 --- a/src/mainboard/supermicro/x9sae/devicetree.cb +++ b/src/mainboard/supermicro/x9sae/devicetree.cb @@ -18,7 +18,7 @@ device ref peg60 on end # CPU1 SLOT7 (electrical x4 in x8) chip southbridge/intel/bd82x6x - register "gen1_dec" = "0x00fc0a01" # NCT6776 SuperIO (0x0a00-0aff) + register "gen1_dec" = "LPC_IO_DEC(0x0a00, 0x00fc | 0x3)" # NCT6776 SuperIO (0x0a00-0aff) register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x3f" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/supermicro/x9scl/devicetree.cb b/src/mainboard/supermicro/x9scl/devicetree.cb index 203a7a6..c88f2f8 100644 --- a/src/mainboard/supermicro/x9scl/devicetree.cb +++ b/src/mainboard/supermicro/x9scl/devicetree.cb @@ -8,10 +8,10 @@ device ref igd off end # iGPU device ref peg60 on end # PEG chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "gen1_dec" = "0x00fc0a01" # NCT6776 SuperIO (0x0a00-0aff) - register "gen2_dec" = "0x00fc1641" # WPCM450 SuperIO (0x1600-16ff) - register "gen3_dec" = "0x00040ca1" # IPMI KCS (0x0ca0-0ca3) - register "gen4_dec" = "0x001c03e1" # 3rd UART (0x03e0-03ff) + register "gen1_dec" = "LPC_IO_DEC(0x0a00, 0x00fc | 0x3)" # NCT6776 SuperIO (0x0a00-0aff) + register "gen2_dec" = "LPC_IO_DEC(0x1640, 0x00fc | 0x3)" # WPCM450 SuperIO (0x1600-16ff) + register "gen3_dec" = "LPC_IO_DEC(0x0ca0, 0x0004 | 0x3)" # IPMI KCS (0x0ca0-0ca3) + register "gen4_dec" = "LPC_IO_DEC(0x03e0, 0x001c | 0x3)" # 3rd UART (0x03e0-03ff) register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x3f" diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb index 529767c..1687538 100644 --- a/src/mainboard/system76/addw1/devicetree.cb +++ b/src/mainboard/system76/addw1/devicetree.cb @@ -184,8 +184,8 @@ device pci 1e.3 off end # GSPI #1 device pci 1f.0 on # LPC Interface register "gen1_dec" = "0x00040069" - register "gen2_dec" = "0x00fc0e01" - register "gen3_dec" = "0x00fc0f01" + register "gen2_dec" = "LPC_IO_DEC(0x0e00, 0x00fc | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0x0f00, 0x00fc | 0x3)" chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/system76/adl/devicetree.cb b/src/mainboard/system76/adl/devicetree.cb index ad70b05..3d9b836 100644 --- a/src/mainboard/system76/adl/devicetree.cb +++ b/src/mainboard/system76/adl/devicetree.cb @@ -73,8 +73,8 @@ end device ref pch_espi on register "gen1_dec" = "0x00040069" # EC PM channel - register "gen2_dec" = "0x00fc0e01" # AP/EC command - register "gen3_dec" = "0x00fc0f01" # AP/EC debug + register "gen2_dec" = "LPC_IO_DEC(0x0e00, 0x00fc | 0x3)" # AP/EC command + register "gen3_dec" = "LPC_IO_DEC(0x0f00, 0x00fc | 0x3)" # AP/EC debug chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb index d79aa76..78d9e02 100644 --- a/src/mainboard/system76/bonw14/devicetree.cb +++ b/src/mainboard/system76/bonw14/devicetree.cb @@ -208,8 +208,8 @@ device pci 1e.3 off end # GSPI #1 device pci 1f.0 on # LPC Interface register "gen1_dec" = "0x00040069" - register "gen2_dec" = "0x00fc0e01" - register "gen3_dec" = "0x00fc0f01" + register "gen2_dec" = "LPC_IO_DEC(0x0e00, 0x00fc | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0x0f00, 0x00fc | 0x3)" chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/system76/cml-u/devicetree.cb b/src/mainboard/system76/cml-u/devicetree.cb index 90c5b71..974a0e1 100644 --- a/src/mainboard/system76/cml-u/devicetree.cb +++ b/src/mainboard/system76/cml-u/devicetree.cb @@ -111,8 +111,8 @@ device pci 1e.3 off end # GSPI #1 device pci 1f.0 on # LPC Interface register "gen1_dec" = "0x00040069" - register "gen2_dec" = "0x00fc0e01" - register "gen3_dec" = "0x00fc0f01" + register "gen2_dec" = "LPC_IO_DEC(0x0e00, 0x00fc | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0x0f00, 0x00fc | 0x3)" chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index 4ae412d..96663d8 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -169,8 +169,8 @@ device pci 1e.3 off end # GSPI #1 device pci 1f.0 on # LPC Interface register "gen1_dec" = "0x00040069" - register "gen2_dec" = "0x00fc0e01" - register "gen3_dec" = "0x00fc0f01" + register "gen2_dec" = "LPC_IO_DEC(0x0e00, 0x00fc | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0x0f00, 0x00fc | 0x3)" chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb index 3b84d7f..68085b6 100644 --- a/src/mainboard/system76/kbl-u/devicetree.cb +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -173,8 +173,8 @@ register "PcieRpLtrEnable[8]" = "1" end device ref lpc_espi on - register "gen1_dec" = "0x000c0681" - register "gen2_dec" = "0x000c1641" + register "gen1_dec" = "LPC_IO_DEC(0x0680, 0x000c | 0x3)" + register "gen2_dec" = "LPC_IO_DEC(0x1640, 0x000c | 0x3)" register "gen3_dec" = "0x00040069" chip drivers/pc80/tpm device pnp 0c31.0 on end diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index f17862f..932a8e8 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -184,8 +184,8 @@ device pci 1e.3 off end # GSPI #1 device pci 1f.0 on # LPC Interface register "gen1_dec" = "0x00040069" - register "gen2_dec" = "0x00fc0e01" - register "gen3_dec" = "0x00fc0f01" + register "gen2_dec" = "LPC_IO_DEC(0x0e00, 0x00fc | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0x0f00, 0x00fc | 0x3)" chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index c0c1b4a..3644a72 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -196,8 +196,8 @@ device pci 1e.3 off end # GSPI #1 device pci 1f.0 on # LPC Interface register "gen1_dec" = "0x00040069" # EC PM channel - register "gen2_dec" = "0x00fc0e01" # AP/EC command - register "gen3_dec" = "0x00fc0f01" # AP/EC debug + register "gen2_dec" = "LPC_IO_DEC(0x0e00, 0x00fc | 0x3)" # AP/EC command + register "gen3_dec" = "LPC_IO_DEC(0x0f00, 0x00fc | 0x3)" # AP/EC debug chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/system76/rpl/devicetree.cb b/src/mainboard/system76/rpl/devicetree.cb index a016dec..618bd5c 100644 --- a/src/mainboard/system76/rpl/devicetree.cb +++ b/src/mainboard/system76/rpl/devicetree.cb @@ -57,8 +57,8 @@ end device ref pch_espi on register "gen1_dec" = "0x00040069" # EC PM channel - register "gen2_dec" = "0x00fc0e01" # AP/EC command - register "gen3_dec" = "0x00fc0f01" # AP/EC debug + register "gen2_dec" = "LPC_IO_DEC(0x0e00, 0x00fc | 0x3)" # AP/EC command + register "gen3_dec" = "LPC_IO_DEC(0x0f00, 0x00fc | 0x3)" # AP/EC debug chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/system76/tgl-h/devicetree.cb b/src/mainboard/system76/tgl-h/devicetree.cb index 353a96d..764ace9 100644 --- a/src/mainboard/system76/tgl-h/devicetree.cb +++ b/src/mainboard/system76/tgl-h/devicetree.cb @@ -132,8 +132,8 @@ end device ref pch_espi on register "gen1_dec" = "0x00040069" # EC PM channel - register "gen2_dec" = "0x00fc0E01" # AP/EC command - register "gen3_dec" = "0x00fc0F01" # AP/EC debug + register "gen2_dec" = "LPC_IO_DEC(0x0E00, 0x00fc | 0x3)" # AP/EC command + register "gen3_dec" = "LPC_IO_DEC(0x0F00, 0x00fc | 0x3)" # AP/EC debug chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/system76/tgl-u/devicetree.cb b/src/mainboard/system76/tgl-u/devicetree.cb index f056da7..ff098e9 100644 --- a/src/mainboard/system76/tgl-u/devicetree.cb +++ b/src/mainboard/system76/tgl-u/devicetree.cb @@ -123,8 +123,8 @@ end device ref pch_espi on register "gen1_dec" = "0x00040069" - register "gen2_dec" = "0x00fc0E01" - register "gen3_dec" = "0x00fc0F01" + register "gen2_dec" = "LPC_IO_DEC(0x0E00, 0x00fc | 0x3)" + register "gen3_dec" = "LPC_IO_DEC(0x0F00, 0x00fc | 0x3)" chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index 0899f62..35ddca0 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -160,10 +160,10 @@ device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 device pci 1f.0 on # LPC Interface - register "gen1_dec" = "0x000c0081" + register "gen1_dec" = "LPC_IO_DEC(0x0080, 0x000c | 0x3)" register "gen2_dec" = "0x00040069" - register "gen3_dec" = "0x00fc0e01" - register "gen4_dec" = "0x00fc0f01" + register "gen3_dec" = "LPC_IO_DEC(0x0e00, 0x00fc | 0x3)" + register "gen4_dec" = "LPC_IO_DEC(0x0f00, 0x00fc | 0x3)" chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index b1e90fa..51f512f 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -20,6 +20,7 @@ #include <soc/usb.h> #include <soc/vr_config.h> #include <stdint.h> +#include <southbridge/intel/common/lpc.h> /* Define config parameters for In-Band ECC (IBECC). */ #define MAX_IBECC_REGIONS 8 diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 392f586..85278d2 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -15,6 +15,7 @@ #include <drivers/i2c/designware/dw_i2c.h> #include <soc/pm.h> #include <soc/usb.h> +#include <southbridge/intel/common/lpc.h> #define MAX_PCIE_PORTS 6 #define CLKREQ_DISABLED 0xf diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 2b5cccd..33f7c17 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -4,6 +4,7 @@ #define _SOC_INTEL_BROADWELL_CHIP_H_ #include <drivers/intel/gma/gma.h> +#include <southbridge/intel/common/lpc.h> #include <stdint.h> struct soc_intel_broadwell_config { diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 994f2ae..a0985c0 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -26,6 +26,7 @@ #else #include <soc/gpio_defs.h> #endif +#include <southbridge/intel/common/lpc.h> #define SOC_INTEL_CML_UART_DEV_MAX 3 #define SOC_INTEL_CML_SATA_DEV_MAX 8 diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 204d073..090037f 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -15,6 +15,7 @@ #include <soc/pmc.h> #include <soc/serialio.h> #include <soc/usb.h> +#include <southbridge/intel/common/lpc.h> #include <types.h> #define MAX_HD_AUDIO_SDI_LINKS 2 diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 66ad223..82d8634 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -19,6 +19,7 @@ #include <soc/pmc.h> #include <soc/serialio.h> #include <soc/usb.h> +#include <southbridge/intel/common/lpc.h> #include <stdint.h> #include <stdbool.h> diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index cfef3c1..ddeda8b 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -16,6 +16,7 @@ #include <soc/pmc.h> #include <soc/serialio.h> #include <soc/usb.h> +#include <southbridge/intel/common/lpc.h> #include <stdint.h> /* Define config parameters for In-Band ECC (IBECC). */ diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 3070c46..5df29a3 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -22,6 +22,7 @@ #include <soc/serialio.h> #include <soc/usb.h> #include <soc/vr_config.h> +#include <southbridge/intel/common/lpc.h> #define MAX_PEG_PORTS 3 diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 3de8ffa..bd79868d 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -18,6 +18,7 @@ #include <soc/pmc.h> #include <soc/serialio.h> #include <soc/usb.h> +#include <southbridge/intel/common/lpc.h> #include <types.h> #define MAX_HD_AUDIO_DMIC_LINKS 2 diff --git a/src/soc/intel/xeon_sp/cpx/chip.h b/src/soc/intel/xeon_sp/cpx/chip.h index 321073b..dd73575 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.h +++ b/src/soc/intel/xeon_sp/cpx/chip.h @@ -7,6 +7,7 @@ #include <intelblocks/cfg.h> #include <soc/acpi.h> #include <soc/irq.h> +#include <southbridge/intel/common/lpc.h> #include <stdint.h> #define MAX_PCH_PCIE_PORT 20 diff --git a/src/soc/intel/xeon_sp/skx/chip.h b/src/soc/intel/xeon_sp/skx/chip.h index 0c05211..74fcd02 100644 --- a/src/soc/intel/xeon_sp/skx/chip.h +++ b/src/soc/intel/xeon_sp/skx/chip.h @@ -7,6 +7,7 @@ #include <intelblocks/cfg.h> #include <soc/acpi.h> #include <soc/irq.h> +#include <southbridge/intel/common/lpc.h> #include <stdint.h> struct soc_intel_xeon_sp_skx_config { diff --git a/src/soc/intel/xeon_sp/spr/chip.h b/src/soc/intel/xeon_sp/spr/chip.h index 28af550..7f45ab7 100644 --- a/src/soc/intel/xeon_sp/spr/chip.h +++ b/src/soc/intel/xeon_sp/spr/chip.h @@ -7,6 +7,7 @@ #include <intelblocks/cfg.h> #include <soc/acpi.h> #include <soc/irq.h> +#include <southbridge/intel/common/lpc.h> #include <stdint.h> #define MAX_PCH_PCIE_PORT 20 diff --git a/src/soc/intel/xeon_sp/spr/chipset.cb b/src/soc/intel/xeon_sp/spr/chipset.cb index a674af9..66675bf 100644 --- a/src/soc/intel/xeon_sp/spr/chipset.cb +++ b/src/soc/intel/xeon_sp/spr/chipset.cb @@ -13,7 +13,7 @@ # configure VT-d register "vtd_support" = "1" - register "gen2_dec" = "0x000c0ca1" # IPMI KCS + register "gen2_dec" = "LPC_IO_DEC(0x0ca0, 0x000c | 0x3)" # IPMI KCS register "cstate_states" = "CSTATES_C1C6" device cpu_cluster 0 on end diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 30c2675..e3b3e16 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -3,6 +3,7 @@ #ifndef SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H #define SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H +#include <southbridge/intel/common/lpc.h> #include <southbridge/intel/common/spi.h> #include <types.h> diff --git a/src/southbridge/intel/common/lpc.h b/src/southbridge/intel/common/lpc.h new file mode 100644 index 0000000..4fc0f4f --- /dev/null +++ b/src/southbridge/intel/common/lpc.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_LPC_H +#define SOUTHBRIDGE_INTEL_LPC_H + +#define DECODE_ENABLE 1 +#define LPC_IO_DEC(base, mask) (((base) & 0xfffc) | ((mask) & 0xfc) | DECODE_ENABLE) + +#endif diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index 04b82d3..10f9182 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -3,6 +3,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82801GX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801GX_CHIP_H +#include <southbridge/intel/common/lpc.h> #include <types.h> enum sata_mode { diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h index ec7b977..fe719c1 100644 --- a/src/southbridge/intel/i82801ix/chip.h +++ b/src/southbridge/intel/i82801ix/chip.h @@ -3,6 +3,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82801IX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801IX_CHIP_H +#include <southbridge/intel/common/lpc.h> #include <stdint.h> enum { diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h index ae31d4f..bbb8446 100644 --- a/src/southbridge/intel/i82801jx/chip.h +++ b/src/southbridge/intel/i82801jx/chip.h @@ -3,6 +3,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82801JX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801JX_CHIP_H +#include <southbridge/intel/common/lpc.h> #include <stdint.h> enum { diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index 12bb401..4c547a2 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -3,6 +3,7 @@ #ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H #define SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H +#include <southbridge/intel/common/lpc.h> #include <stdint.h> struct southbridge_intel_lynxpoint_config { -- To view, visit https://review.coreboot.org/c/coreboot/+/79742?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic05a7b1e6d0bafcd3c376b8f8dc4acce0f2629a7 Gerrit-Change-Number: 79742 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: vendorcode/google/chromeos: Add API to read factory config
by Subrata Banik (Code Review) 28 Dec '23

28 Dec '23

Attention is currently required from: Eric Lai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Shelley Chen, Tim Van Patten. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79737?usp=email ) Change subject: vendorcode/google/chromeos: Add API to read factory config ...................................................................... Patch Set 5: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79737/comment/c7122f97_01916d70 : PS5, Line 7: API to read factory config > Please make it a statement: […] Acknowledged File src/vendorcode/google/chromeos/chromeos.h: https://review.coreboot.org/c/coreboot/+/79737/comment/9ebde590_4260febf : PS5, Line 31: * For the unprovisioned one, the read will be 0x0. > 0 is also returned in the error case? Acknowledged File src/vendorcode/google/chromeos/tpm_factory_config.c: https://review.coreboot.org/c/coreboot/+/79737/comment/e7235644_842b5f83 : PS5, Line 12: printk(BIOS_ERR, "tlcl_lib_init() failed: %#x\n", rc); > As this is an error message, please elaborate for a user reading the log. sorry, unable to follow. done https://review.coreboot.org/c/coreboot/+/79737/comment/16c92220_93fc22a7 : PS5, Line 21: printk(BIOS_ERR, "tlcl_cr50_get_factory_config() failed: %#x\n", rc); > Ditto. Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/79737?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I34f47c9a94972534cda656ef624ef12ed5ddeb06 Gerrit-Change-Number: 79737 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Thu, 28 Dec 2023 15:56:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: vendorcode/google/chromeos: Add API to read factory config
by Subrata Banik (Code Review) 28 Dec '23

28 Dec '23

Attention is currently required from: Eric Lai, Kapil Porwal, Nick Vaccaro, Shelley Chen, Subrata Banik, Tim Van Patten. Hello Eric Lai, Kapil Porwal, Nick Vaccaro, Shelley Chen, Tim Van Patten, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79737?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Code-Review+2 by Eric Lai, Code-Review+2 by Kapil Porwal, Verified+1 by build bot (Jenkins) Change subject: vendorcode/google/chromeos: Add API to read factory config ...................................................................... vendorcode/google/chromeos: Add API to read factory config This code leverages the TPM vendor-specific function tlcl_cr50_get_factory_config() to fetch the device's factory configuration. BUG=b:317880956 TEST=Able to retrieve the factory config from google/screebo. Change-Id: I34f47c9a94972534cda656ef624ef12ed5ddeb06 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/vendorcode/google/chromeos/Makefile.inc M src/vendorcode/google/chromeos/chromeos.h A src/vendorcode/google/chromeos/tpm_factory_config.c 3 files changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/79737/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/79737?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I34f47c9a94972534cda656ef624ef12ed5ddeb06 Gerrit-Change-Number: 79737 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2023