coreboot-gerrit December 2023

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[L] Change in coreboot[main]: mainboard: add Dell Latitude E7240
by Nicholas Chin (Code Review) 28 Dec '23

28 Dec '23

Attention is currently required from: Iru Cai. Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79746?usp=email ) Change subject: mainboard: add Dell Latitude E7240 ...................................................................... Patch Set 2: (12 comments) Patchset: PS2: I noticed that your old MEC5055 patch in CB:44975 which your old E7240 port used sent a 0xAB command to the EC. Do you know what it does? I didn't include it in my MEC5035 code because I found that the 0xC2 command was the only one necessary to prevent the E6400 from shutting down, and I didn't want to include mystery unnamed commands if possible. I do see the 0xAB command in my LPC traces though, but there are also a ton of other commands which I also don't yet know the purpose of. File Documentation/mainboard/dell/e7240.md: https://review.coreboot.org/c/coreboot/+/79746/comment/cff2f650_58698286 : PS2, Line 29: a programmer Maybe make this more clear by using "an external programmer" https://review.coreboot.org/c/coreboot/+/79746/comment/9c2d439e_f936bbb0 : PS2, Line 41: Schematic of this laptop can be found on [Lab One]. The board name is Compal LA-9431P. It's not a formally written policy but it's probably not good idea for coreboot to link to documents that are technically stolen IP. We don't want to give the vendors anything they could use to argue that coreboot infringes on their IP. Just mentioning the board name should be fine, as it's printed on the board itself. https://review.coreboot.org/c/coreboot/+/79746/comment/3e810c45_f88dee01 : PS2, Line 81: : [Lab One]: https://www.laboneinside.com/dell-latitude-e7240-schematic-diagram/ : See prior comment about the schematic link File src/mainboard/dell/e7240/Kconfig: https://review.coreboot.org/c/coreboot/+/79746/comment/4717e9cd_3ccf0e4d : PS2, Line 5: BOARD_ROMSIZE_KB_8192 Is this correct? The E7240 appears to have 2 flash chips, an 8MiB and a 4MiB https://review.coreboot.org/c/coreboot/+/79746/comment/1058617c_3beb1666 : PS2, Line 17: string Not necessary, as the type is already defined in `mb/Kconfig` https://review.coreboot.org/c/coreboot/+/79746/comment/ea57f206_c6159e2d : PS2, Line 21: string Same here, can be removed https://review.coreboot.org/c/coreboot/+/79746/comment/baa4a71b_3e08a61d : PS2, Line 24: config VGA_BIOS_FILE : string : default "pci8086,0a16.rom" Remove, see commit 05ae8f2ff3 (mainboard: Drop invalid `VGA_BIOS_FILE` defaults). https://review.coreboot.org/c/coreboot/+/79746/comment/31ce767c_10cf5a5f : PS2, Line 29: string Can be removed https://review.coreboot.org/c/coreboot/+/79746/comment/f8806cf3_10eb7d6e : PS2, Line 33: int Can be removed File src/mainboard/dell/e7240/Makefile.inc: PS2: Missing SPDX header. See commit 8ebd8cc348 (mainboard: Add SPDX license headers to Makefiles) File src/mainboard/dell/e7240/bootblock.c: https://review.coreboot.org/c/coreboot/+/79746/comment/3f422484_9cfc30eb : PS2, Line 13: pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x007c0901); : mec5035_early_init(); : pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0); Any reason to explicitly set and unset LPC_GEN4_DEC here? The devicetree entries for these are set up in the bootblock (see `sb/intel/bd82x6x/early_pch.c`) and I don't see any harm in just leaving them set up permanently -- To view, visit https://review.coreboot.org/c/coreboot/+/79746?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6933bdbcc8d0bbb85d62657624740266284ac71c Gerrit-Change-Number: 79746 Gerrit-PatchSet: 2 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Comment-Date: Thu, 28 Dec 2023 18:43:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: vendorcode/google/chromeos: Add API for Chromebook Plus check
by Shelley Chen (Code Review) 28 Dec '23

28 Dec '23

Attention is currently required from: Eric Lai, Kapil Porwal, Subrata Banik. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79763?usp=email ) Change subject: vendorcode/google/chromeos: Add API for Chromebook Plus check ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79763?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebaed1c60e34af4cc36316f1f87a89df778b0857 Gerrit-Change-Number: 79763 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 28 Dec 2023 18:39:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: vendorcode/google/chromeos: Add API to read factory config
by Shelley Chen (Code Review) 28 Dec '23

28 Dec '23

Attention is currently required from: Eric Lai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik, Tim Van Patten. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79737?usp=email ) Change subject: vendorcode/google/chromeos: Add API to read factory config ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79737?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I34f47c9a94972534cda656ef624ef12ed5ddeb06 Gerrit-Change-Number: 79737 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Thu, 28 Dec 2023 18:39:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: security/tpm: Retrieve factory configuration for device w/ Google TPM
by Shelley Chen (Code Review) 28 Dec '23

28 Dec '23

Attention is currently required from: Christian Walter, Nick Vaccaro, Paul Menzel, Paz Zcharya, Subrata Banik, Tim Van Patten. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79736?usp=email ) Change subject: security/tpm: Retrieve factory configuration for device w/ Google TPM ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79736?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifd0e850770152a03aa46d7f8bbb76f7520a59081 Gerrit-Change-Number: 79736 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paz Zcharya <pazz(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Thu, 28 Dec 2023 18:39:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: vendorcode/google/chromeos: Add API for Chromebook Plus check
by Subrata Banik (Code Review) 28 Dec '23

28 Dec '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79763?usp=email ) Change subject: vendorcode/google/chromeos: Add API for Chromebook Plus check ...................................................................... vendorcode/google/chromeos: Add API for Chromebook Plus check This patch implements an API which relies on the chromeos_get_factory_config() function to retrieve the factory config value. This information is useful to determine whether a ChromeOS device is branded as a Chromebook Plus based on specific bit flags: - Bit 4 (0x10): Indicates whether the device chassis has the "chromebook-plus" branding. - Bits 3-0 (0x1): Must be 0x1 to signify compliance with Chromebook Plus hardware specifications. BUG=b:317880956 TEST=Able to verify that google/screebo is branced as Chromebook Plus. Change-Id: Iebaed1c60e34af4cc36316f1f87a89df778b0857 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/vendorcode/google/chromeos/chromeos.h M src/vendorcode/google/chromeos/tpm_factory_config.c 2 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/79763/1 diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index c14af31..04d2f81 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -32,6 +32,18 @@ * Return `-1` in case of error. */ int64_t chromeos_get_factory_config(void); +/* + * Determines whether a ChromeOS device is branded as a Chromebook Plus + * based on specific bit flags: + * + * - Bit 4 (0x10): Indicates whether the device chassis has the + * "chromebook-plus" branding. + * - Bits 3-0 (0x1): Must be 0x1 to signify compliance with Chromebook Plus + * hardware specifications. + * + * To be considered a Chromebook Plus, BOTH of these conditions must be met. + */ +bool chromeos_device_branded_plus(void); /* * Declaration for mainboards to use to generate ACPI-specific ChromeOS needs. diff --git a/src/vendorcode/google/chromeos/tpm_factory_config.c b/src/vendorcode/google/chromeos/tpm_factory_config.c index afb4ade..ced96d2 100644 --- a/src/vendorcode/google/chromeos/tpm_factory_config.c +++ b/src/vendorcode/google/chromeos/tpm_factory_config.c @@ -2,8 +2,13 @@ #include <console/console.h> #include <security/tpm/tss.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> +#define CHROMEBOOK_PLUS_HARD_BRANDED BIT(4) +#define CHROMEBOOK_PLUS_SOFT_BRANDED BIT(0) +#define CHROMEBOOK_PLUS_DEVICE (CHROMEBOOK_PLUS_HARD_BRANDED | CHROMEBOOK_PLUS_SOFT_BRANDED) + int64_t chromeos_get_factory_config(void) { /* Initialize TPM driver. */ @@ -26,3 +31,19 @@ return factory_config; } + +/* + * Determines whether a ChromeOS device is branded as a Chromebook Plus + * based on specific bit flags: + * + * - Bit 4 (0x10): Indicates whether the device chassis has the + * "chromebook-plus" branding. + * - Bits 3-0 (0x1): Must be 0x1 to signify compliance with Chromebook Plus + * hardware specifications. + * + * To be considered a Chromebook Plus, BOTH of these conditions must be met. + */ +bool chromeos_device_branded_plus(void) +{ + return chromeos_get_factory_config() & CHROMEBOOK_PLUS_DEVICE; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/79763?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebaed1c60e34af4cc36316f1f87a89df778b0857 Gerrit-Change-Number: 79763 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: vboot: Add firmware PCR support
by Julius Werner (Code Review) 28 Dec '23

28 Dec '23

Attention is currently required from: Christian Walter, Paul Menzel, Yi Chou, Yu-Ping Wu. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79437?usp=email ) Change subject: vboot: Add firmware PCR support ...................................................................... Patch Set 6: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79437/comment/32e17552_930147fc : PS6, Line 24: to 10 (and we plan to use PCR 12 for kernel version). Wait what? I thought we were planning to mix both versions into one PCR? Was there a specific reason to separate them or was that just a misunderstanding about how the proposed design should be implemented? There were already concerns about wasting PCRs and maybe eventually running out for using just one, which I personally think is unlikely, but we should still make sure we don't use up more than we need. There's no reason for the GSC to be able to attest both of these versions separately, so I think we should be frugal and mix them together. Patchset: PS6: This patch itself looks good to me but it sounds like we still have some separate issues to sort out about the larger design. -- To view, visit https://review.coreboot.org/c/coreboot/+/79437?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I601ad31e8c893a8e9ae1a9cdd27193edce10ec61 Gerrit-Change-Number: 79437 Gerrit-PatchSet: 6 Gerrit-Owner: Yi Chou <yich(a)google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Yi Chou <yich(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 28 Dec 2023 17:44:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: add hook for WiFi SAR table
by Shelley Chen (Code Review) 28 Dec '23

28 Dec '23

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79730?usp=email ) Change subject: mb/google/nissa/var/anraggar: add hook for WiFi SAR table ...................................................................... mb/google/nissa/var/anraggar: add hook for WiFi SAR table As a preparation for WiFi SAR table addition, adding hook for it. BRANCH=nissa BUG=b:315418153 TEST=emerge-nissa coreboot Cq-Depend: chrome-internal:6790137 Change-Id: Idb200699bb8c8581b9512ec8ec9442f65f8822b3 Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79730 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/anraggar/Makefile.inc A src/mainboard/google/brya/variants/anraggar/variant.c 3 files changed, 11 insertions(+), 0 deletions(-) Approvals: Jianeng Ceng: Looks good to me, but someone else must approve build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index fb62880..be4e694 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -508,6 +508,7 @@ select DRIVERS_INTEL_MIPI_CAMERA select HAVE_WWAN_POWER_SEQUENCE select DRIVERS_GFX_GENERIC + select CHROMEOS_WIFI_SAR if CHROMEOS if BOARD_GOOGLE_BRYA_COMMON diff --git a/src/mainboard/google/brya/variants/anraggar/Makefile.inc b/src/mainboard/google/brya/variants/anraggar/Makefile.inc index d38141c..f41cdfd 100644 --- a/src/mainboard/google/brya/variants/anraggar/Makefile.inc +++ b/src/mainboard/google/brya/variants/anraggar/Makefile.inc @@ -4,3 +4,5 @@ romstage-y += gpio.c ramstage-y += gpio.c + +ramstage-y += variant.c diff --git a/src/mainboard/google/brya/variants/anraggar/variant.c b/src/mainboard/google/brya/variants/anraggar/variant.c new file mode 100644 index 0000000..4f44c38 --- /dev/null +++ b/src/mainboard/google/brya/variants/anraggar/variant.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + return "wifi_sar_2.hex"; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/79730?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb200699bb8c8581b9512ec8ec9442f65f8822b3 Gerrit-Change-Number: 79730 Gerrit-PatchSet: 6 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tao Yang <yangtao6(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: devicetree.cb: Use a macro to make IO genx_dec more comprehensible
by Nicholas Chin (Code Review) 28 Dec '23

28 Dec '23

Attention is currently required from: Alexander Couzens, Angel Pons, Arthur Heymans, Christian Walter, Dinesh Gehlot, Eran Mitrani, Eric Lai, Erik van den Bogaert, Evgeny Sorokin, Frans Hendriks, Jakub Czapiga, Jeremy Soller, Johnny Lin, Jonathon Hall, Kapil Porwal, Kevin Keijzer, Lean Sheng Tan, Michael Niewöhner, Michał Kopeć, Michał Żygowski, Morgan Jang, Nick Vaccaro, Nico Huber, Piotr Król, Sean Rhodes, Stefan Ott, Subrata Banik, Tarun, Tim Chu, Tim Crawford, Werner Zeh. Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79742?usp=email ) Change subject: devicetree.cb: Use a macro to make IO genx_dec more comprehensible ...................................................................... Patch Set 3: (2 comments) Commit Message: PS3: > Are there any cases where the lower nibble is 0xd or 0x5? These two commands only seem to account fo […] `grep -E "\"gen[1-4]_dec\" = \"0x[0-9a-fA-F][d5]\"" $(find -name "*.cb")` returns some results https://review.coreboot.org/c/coreboot/+/79742/comment/8a968f74_bed8673c : PS3, Line 13: 0x00 Based on a quick skim of the output of `grep -E "gen[1-4]_dec" $(find -name "*.cb")`, there seem to be a few cases where the leading 00 isn't present, such as the x230, -- To view, visit https://review.coreboot.org/c/coreboot/+/79742?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic05a7b1e6d0bafcd3c376b8f8dc4acce0f2629a7 Gerrit-Change-Number: 79742 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Evgeny Sorokin <me(a)ch1p.io> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Evgeny Sorokin <me(a)ch1p.io> Gerrit-Comment-Date: Thu, 28 Dec 2023 16:58:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/pcengines/apu2/mainboard: add/fix comments on PIRQ table
by Felix Held (Code Review) 28 Dec '23

28 Dec '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79676?usp=email ) Change subject: mb/pcengines/apu2/mainboard: add/fix comments on PIRQ table ...................................................................... mb/pcengines/apu2/mainboard: add/fix comments on PIRQ table Align the comments on the PIRQ table entries for the PCI bridge devices to the external PCIe ports with the devicetrees of the different APU boards. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id25ae8422c7c5c79dc8666a28a8219c77af324da Reviewed-on: https://review.coreboot.org/c/coreboot/+/79676 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/pcengines/apu2/mainboard.c 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 4fe1a12..a09fa66 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -95,11 +95,11 @@ /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ {ACTL_DEVFN, {PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */ - {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */ - {NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe: 02.2 */ + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* mPCIe/NIC: 02.1 */ + {NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* NIC: 02.2 */ {NB_PCIE_PORT3_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}}, /* NIC: 02.3 */ - {NB_PCIE_PORT4_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C}}, /* 02.4 */ - {NB_PCIE_PORT5_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* 02.5 */ + {NB_PCIE_PORT4_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C}}, /* NIC: 02.4 */ + {NB_PCIE_PORT5_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* mPCIe: 02.5 */ {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */ {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/79676?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id25ae8422c7c5c79dc8666a28a8219c77af324da Gerrit-Change-Number: 79676 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/pcengines/apu2/mainboard: improve alignment in PIRQ table entries
by Felix Held (Code Review) 28 Dec '23

28 Dec '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79675?usp=email ) Change subject: mb/pcengines/apu2/mainboard: improve alignment in PIRQ table entries ...................................................................... mb/pcengines/apu2/mainboard: improve alignment in PIRQ table entries Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If08f7674509c953cf46c4e0d280edc9f863ef2d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79675 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/pcengines/apu2/mainboard.c 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 9d218e6..4fe1a12 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -93,8 +93,8 @@ */ static const struct pirq_struct mainboard_pirq_data[] = { /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ - {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ - {ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */ + {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ + {ACTL_DEVFN, {PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */ {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */ {NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe: 02.2 */ {NB_PCIE_PORT3_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}}, /* NIC: 02.3 */ @@ -107,8 +107,8 @@ {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ - {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ - {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ + {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */ {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 (same device as xHCI 10.0) */ {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 (same device as xHCI 10.1) */ }; -- To view, visit https://review.coreboot.org/c/coreboot/+/79675?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If08f7674509c953cf46c4e0d280edc9f863ef2d8 Gerrit-Change-Number: 79675 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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