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Change subject: mb/intel/mtlrvp: define a new config for Chrome EC.
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
PS2:
> Please see similar comments as in Change-Id I788dbeaad05e5d6904fb2c7c681a0bf653dc7d84.
Acknowledged
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Change subject: mb/intel/mtlrvp: add 512KB SI_EC FMAP region
......................................................................
Patch Set 5:
(10 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79209/comment/270f7478_2cecf17a :
PS4, Line 7: add SI_EC region in flash map
> Add 512 kB SI_EC FMAP region fo MEC1723
change is applicable for all MTLRVP variants, hence removing MEC1723
https://review.coreboot.org/c/coreboot/+/79209/comment/02cd2fe6_9aa2e593 :
PS4, Line 7: mtlrvp
> Please extend the prefix: mb/intel/mtlrvp.
Done
https://review.coreboot.org/c/coreboot/+/79209/comment/94d769e9_d26fff89 :
PS4, Line 9: booted with
> “booted with”? What do you mean?
i have updated the commit message to provide clear details.
https://review.coreboot.org/c/coreboot/+/79209/comment/96792905_418058e4 :
PS4, Line 9: do
> does
Acknowledged
https://review.coreboot.org/c/coreboot/+/79209/comment/610d70d0_9b38da27 :
PS4, Line 9: microchip
> Microship
Microship is right
https://review.coreboot.org/c/coreboot/+/79209/comment/3c90fbbf_a7671cae :
PS4, Line 9: MTLRVP
> Use “MTLRVP for Chrome OS”?
Acknowledged
https://review.coreboot.org/c/coreboot/+/79209/comment/890f7f27_851caf37 :
PS4, Line 11: Using MEC1723 for chrome helps in RVP BOM convergence.
> Sorry, I do not understand what you mean.
I have updated the commit message, kindly check.
https://review.coreboot.org/c/coreboot/+/79209/comment/00c6c75e_1d5f1ed7 :
PS4, Line 16: This patch adds SI_EC region similar to windows.
> Please add a blank line above to separate paragraphs.
Done
https://review.coreboot.org/c/coreboot/+/79209/comment/b01a4f3b_c9113c74 :
PS4, Line 9: MTLRVP booted with microchip EC1723 which do not have an
: internal flash memory similar to the windows RVP designs.
: Using MEC1723 for chrome helps in RVP BOM convergence.
:
: EC, AP shares the same external SPI flash. EC ROM will
: download the EC firmware from external SPI to internal SRAM
: for execution.
: This patch adds SI_EC region similar to windows.
> Please reflow to use all of the allowed text width of 72 characters per line.
Done
https://review.coreboot.org/c/coreboot/+/79209/comment/e2bd99aa_6d65a879 :
PS4, Line 16: This patch adds SI_EC region similar to windows.
> “This patch adds” is redundant in a commit message. Maybe use imperative mood: […]
No, Coreboot firmware is exclusive to Chrome OS.
In this context, Windows designs employ embedded controllers without built-in flash memory.
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I'd like you to reexamine a change. Please visit
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Change subject: mb/intel/mtlrvp: define a new config for Chrome EC.
......................................................................
mb/intel/mtlrvp: define a new config for Chrome EC.
Introduce new config MTL_CHROME_EC_SHARED_SPI, tailored for
Chrome ECs utilizing an external shared SPI flash.
BUG=b:289783489
TEST=emerge-rex coreboot chromeos-bootimage is successful
Change-Id: I0b85cc48d5cefadb52edbb27bf6cf370b27c395f
Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com>
---
M src/mainboard/intel/mtlrvp/Kconfig
1 file changed, 11 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/79211/3
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Change subject: mb/intel/mtlrvp: add 512KB SI_EC FMAP region
......................................................................
mb/intel/mtlrvp: add 512KB SI_EC FMAP region
This patch introduces the 512KB SI_EC FMAP region for storing the EC
firmware, a necessary addition to support EC chips without internal
flash memory.
As a testing platform, the MTLRVP Chrome SKU is utilized in conjunction
with the Microchip EC1723, and the changes are verified.
BUG=b:289783489
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---
M src/mainboard/intel/mtlrvp/chromeos.fmd
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git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/79209/5
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Change subject: acpi: Enable 64bit ECAM resource
......................................................................
Patch Set 1:
(1 comment)
File src/acpi/dsdt_top.asl:
https://review.coreboot.org/c/coreboot/+/79096/comment/5c4688ff_cc22d526 :
PS1, Line 64: ResourceProducer
If you look at the ACPI spec, it *seems* to suggest that "Producer" is the right thing: https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/19_ASL_Reference/ACPI_Source_…
> ResourceUsage specifies whether the Memory range is consumed by this device (ResourceConsumer) or passed on to child devices (ResourceProducer). If nothing is specified, then ResourceConsumer is assumed.
But the Linux doc linked in the comment (https://www.kernel.org/doc/Documentation/PCI/acpi-info.rst) says the following:
> ACPI defines a Consumer/Producer bit to distinguish the bridge registers
("Consumer") from the bridge apertures ("Producer") [4, 5], but early
BIOSes didn't use that bit correctly. The result is that the current ACPI
spec defines Consumer/Producer only for the Extended Address Space
descriptors; the bit should be ignored in the older QWord/DWord/Word
Address Space descriptors. Consequently, OSes have to assume all
QWord/DWord/Word descriptors are windows.
Which suggests that this distinction is irrelevant, and:
> PNP0C02 "motherboard" devices are basically a catch-all. There's no
programming model for them other than "don't use these resources for
anything else." So a PNP0C02 _CRS should claim any address space that is
(1) not claimed by _CRS under any other device object in the ACPI namespace
and (2) should not be assigned by the OS to something else.
Which says this is just a catch-all in the form of a motherboard resource.
TL;DR I think ResourceConsumer may be more accurate.
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Change subject: arch/x86/mmu: Port armv8 MMU to x86_64
......................................................................
Patch Set 18:
(2 comments)
Patchset:
PS18:
I've updated this + made the tree use dynamic page tables, when there are and have support for SMM to add in a follow-up. I'll push those as follow-ups after I do some debugging: QEMU Q35 seems to overflow SMRAM, it seems to triple fault when jumping to the entrypoint which is outside SMRAM and therefore, unmapped
File src/arch/x86/mmu.c:
https://review.coreboot.org/c/coreboot/+/30119/comment/bf1c8020_1600e1f8 :
PS16, Line 335: (uint64_t *)cbmem_add(CBMEM_ID_PAGE, pages * 4 * KiB);
> > It might be even better to have page tables in heap. […]
romstage generates only if necessary. ramstage's tables are the primary ones used.
Even assuming that SMM can read CBMEM (I looked briefly and I couldn't see it compiled in), we've discussed this off Gerrit and I agree it's not safe. Allowing ring-0 to control SMM's memory access doesn't sound good to me. Unless I misunderstood, I believe we've decided SMM needs different page tables?
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Change subject: acpi.c: Fix generating pointer to cb_tables located >4G
......................................................................
Patch Set 7:
(2 comments)
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/76181/comment/418fcebd_0227e18c :
PS7, Line 301: base + size
`base + size - 1` because UINT32_MAX is also `4G - 1`.
https://review.coreboot.org/c/coreboot/+/76181/comment/70bb9286_3771461a :
PS7, Line 304: producer
Shouldn't this be a 'consumer'? AIUI, `ResourceProducer` is meant for
parent devices that make a resource range available to their children.
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