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Change subject: mb/google/nissa/var/anraggar: Add OV13B10 MIPI camera device
......................................................................
Patch Set 3: Code-Review+1
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Hello Eric Lai, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/79102?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Code-Review+1 by Eric Lai, Verified+1 by build bot (Jenkins)
Change subject: mb/google/brox: Fix configuration for TPM in Kconfig
......................................................................
mb/google/brox: Fix configuration for TPM in Kconfig
On Brox, TPM is using i2c1 and GPP_E1, so modifying the Kconfig to
reflect this.
BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: I0ecaa6fcfc05c3c2e55f857d7a4e59fe46096bb5
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
M src/mainboard/google/brox/Kconfig
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/79102/2
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Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79293?usp=email )
Change subject: Update cmocka submodule to upstream master
......................................................................
Update cmocka submodule to upstream master
Updating from commit id a01cc69:
2023-02-23 15:04:02 +0100 - (Bump version to 1.1.7)
to commit id 109645a:
2023-08-01 11:47:11 +0200 - (include: Remove old MVSC prototype)
This brings in 170 new commits.
Change-Id: I89890a247b49da1f203736dc42bdb5d249b54399
Signed-off-by: Yidi Lin <yidilin(a)chromium.org>
---
M 3rdparty/cmocka
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git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/79293/1
diff --git a/3rdparty/cmocka b/3rdparty/cmocka
index 8931845..109645a 160000
--- a/3rdparty/cmocka
+++ b/3rdparty/cmocka
@@ -1 +1 @@
-Subproject commit 8931845c35e78b5123d73430b071affd537d5935
+Subproject commit 109645a20fe2983f54e318c23575e39cdb8b1d0a
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Change subject: mb/google/nissa/var/anraggar: Enable ILITEK touchscreen
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Patch Set 4: Code-Review+1
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Change subject: vc/intel/fsp/mtl: Export pre-memory graphics FSP-M UPDs
......................................................................
Patch Set 11:
(1 comment)
Patchset:
PS3:
> as mentioned earlier, please file a bug to capture all newly added UPD into FSP partial header. […]
Done
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Change subject: arch/arm64: Add EL1/EL2/EL3 support for arm64
......................................................................
Patch Set 9:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74798/comment/222b419e_0bb54c66 :
PS5, Line 11: one boots into TF-A first and drops into EL2 for coreboot afterwards.
> So, if we shut ourselves off to even make it possible to enable major Arm SoC platforms today, and don’t even have the patience to start the journey to build the coreboot ecosystem for arm
I don't want to add much more to this discussion than I already have, but please don't present this as if you were only just now trying to bring coreboot to the Arm world. We have been supporting real, physical Arm hardware for over a decade, including commercial products numbering millions of devices. In fact some of the most FOSS / blobless platforms in all of coreboot are Arm devices.
I appreciate that your particular platform for the vendor you're trying to add is stuck on this problem, and that's a fair concern since we generally want to try to support as many platforms as possible, but it's also not more than that. And as far as I understand the problem with that platform is also less of a "we really need this SoC vendor secret sauce to initialize the platform which they are absolutely adamant they can't open-source or let us reimplement", as it is often with Intel (at least as far as they present it), for you it's more just a matter of "we only have existing closed source code for this right now and we don't have the time/manpower to port our silicon init to coreboot at the moment".
Patchset:
PS9:
> Maybe to differentiate this, we can go further than just making it a Kconfig option and actually add a new makefile target. That would make it even more plain that this isn't the full coreboot build.
I don't really see what that would give us other than a big maintenance nightmare to be honest. I think we should decouple the technical implementation details from the philosophical question here. From the technical side, I think the patch as proposed is pretty much the right way to implement this if we want to implement it at all.
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Change subject: Update vboot submodule to upstream main
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> Sorry for the late Answer (I'm working with partly time). We use red hat 8. […]
We've already landed dependencies on this now, so let me just try to forward fix. It looks like we're all pretty much in agreement that just adding `-ldl` is the right thing anyway. I've uploaded CL:5062277, it would be good if you could cherry-pick that locally and confirm that it works to fix the problem in your environment.
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Change subject: soc/amd/mendocino: Add DBG2 ACPI table
......................................................................
Patch Set 6:
(1 comment)
File src/soc/amd/mendocino/agesa_acpi.c:
https://review.coreboot.org/c/coreboot/+/79174/comment/5c41f402_a4c2a304 :
PS6, Line 33: current = acpi_16550_write_dbg2_uart(rsdp, current,
: uart_platform_base(get_uart_for_console()), NULL);
> Can we do this in soc/common instead? All AMD boards should have this generated.
also, the DBG2 table has nothing to do with AGESA
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