coreboot-gerrit November 2023

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[XS] Change in coreboot[main]: mb/google/nissa/var/quandiso: Add LTE only daughterboard support
by Robert Chen (Code Review) 28 Nov '23

28 Nov '23

Robert Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79297?usp=email ) Change subject: mb/google/nissa/var/quandiso: Add LTE only daughterboard support ...................................................................... mb/google/nissa/var/quandiso: Add LTE only daughterboard support Quandiso did not use DB_1C, replace the fw_config with LTE only daughterboard. BUG=b:312094048 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Id7129e52d3733f62405f9d766f08563f05016c69 Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/quandiso/fw_config.c M src/mainboard/google/brya/variants/quandiso/overridetree.cb 2 files changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/79297/1 diff --git a/src/mainboard/google/brya/variants/quandiso/fw_config.c b/src/mainboard/google/brya/variants/quandiso/fw_config.c index c5ac0d2..3d0bbd2 100644 --- a/src/mainboard/google/brya/variants/quandiso/fw_config.c +++ b/src/mainboard/google/brya/variants/quandiso/fw_config.c @@ -75,7 +75,7 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { - if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { + if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE)) && !fw_config_probe(FW_CONFIG(DB_USB, DB_LTE))){ printk(BIOS_INFO, "Disable LTE-related GPIO pins.\n"); gpio_padbased_override(padbased_table, lte_disable_pads, ARRAY_SIZE(lte_disable_pads)); diff --git a/src/mainboard/google/brya/variants/quandiso/overridetree.cb b/src/mainboard/google/brya/variants/quandiso/overridetree.cb index 29a4cee..205fd2b 100644 --- a/src/mainboard/google/brya/variants/quandiso/overridetree.cb +++ b/src/mainboard/google/brya/variants/quandiso/overridetree.cb @@ -2,7 +2,7 @@ field DB_USB 0 1 option DB_NONE 0 option DB_1C_1A 1 - option DB_1C 2 + option DB_LTE 2 option DB_1C_LTE 3 end field WIFI_SAR_ID 2 3 @@ -333,6 +333,7 @@ register "reg_adv_ctrl19" = "0xf0" register "reg_adv_ctrl20" = "0xf0" device i2c 28 on + probe DB_USB DB_LTE probe DB_USB DB_1C_LTE end end @@ -444,7 +445,6 @@ use tcss_usb3_port2 as usb3_port device generic 1 alias conn1 on probe DB_USB DB_1C_1A - probe DB_USB DB_1C probe DB_USB DB_1C_LTE end end @@ -468,7 +468,6 @@ register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port2 on probe DB_USB DB_1C_1A - probe DB_USB DB_1C probe DB_USB DB_1C_LTE end end @@ -492,7 +491,6 @@ register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port2 on probe DB_USB DB_1C_1A - probe DB_USB DB_1C probe DB_USB DB_1C_LTE end end @@ -565,6 +563,7 @@ register "desc" = ""USB3 WWAN"" register "type" = "UPC_TYPE_INTERNAL" device ref usb3_port2 on + probe DB_USB DB_LTE probe DB_USB DB_1C_LTE end end -- To view, visit https://review.coreboot.org/c/coreboot/+/79297?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id7129e52d3733f62405f9d766f08563f05016c69 Gerrit-Change-Number: 79297 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: Dochi: Update Touchscreen and Touchpad setting
by Morris Hsu (Code Review) 28 Nov '23

28 Nov '23

Morris Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79296?usp=email ) Change subject: Dochi: Update Touchscreen and Touchpad setting ...................................................................... Dochi: Update Touchscreen and Touchpad setting Update Touchscreen and Touchpad setting in overridetree to be detected in acpi. Change-Id: I807b9c0d05648b7895b1ff3a205878028f65e649 Signed-off-by: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/dochi/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/79296/1 diff --git a/src/mainboard/google/brya/variants/dochi/overridetree.cb b/src/mainboard/google/brya/variants/dochi/overridetree.cb index cc74f8d..19fec5c 100644 --- a/src/mainboard/google/brya/variants/dochi/overridetree.cb +++ b/src/mainboard/google/brya/variants/dochi/overridetree.cb @@ -251,7 +251,7 @@ register "generic.hid" = ""ILTK0001"" register "generic.desc" = ""ILITEK Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" - register "generic.detect" = "1" + register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" register "generic.reset_delay_ms" = "200" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" @@ -264,7 +264,7 @@ register "generic.hid" = ""ELAN9004"" register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" - register "generic.detect" = "1" + register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" register "generic.reset_delay_ms" = "20" register "generic.reset_off_delay_ms" = "2" @@ -284,7 +284,7 @@ register "desc" = ""ELAN Touchpad"" register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" register "wake" = "GPE0_DW2_14" - register "detect" = "1" + register "probed" = "1" device i2c 15 on end end chip drivers/i2c/hid @@ -293,7 +293,7 @@ register "generic.desc" = ""Synaptics Touchpad"" register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" register "generic.wake" = "GPE0_DW2_14" - register "generic.detect" = "1" + register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 0x2c on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/79296?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I807b9c0d05648b7895b1ff3a205878028f65e649 Gerrit-Change-Number: 79296 Gerrit-PatchSet: 1 Gerrit-Owner: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: mb/google/brox: Update storage settings for SSD and UFS
by Ivy Jian (Code Review) 28 Nov '23

28 Nov '23

Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79295?usp=email ) Change subject: mb/google/brox: Update storage settings for SSD and UFS ...................................................................... mb/google/brox: Update storage settings for SSD and UFS Brox has SSD and UFS storage per different SKU. 1. Set SSD on CPU PCIe port (PCIEX4_A) and configured related gpio settings. 2. Enable UFS, also enable ISH since it is PCI function 0, required for UFS function 7 to be enabled. 3. Set unused SRCCLKREQ signals to NC. 4. Remove unused gpio settings in variant gpio table to prevent unexpect overrided. BUG=b:311450057 BRANCH=None TEST=emerge-brox coreboot Change-Id: I88922bcfa13652006aa10078c3c444624fd4575e Signed-off-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brox/Kconfig M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb M src/mainboard/google/brox/variants/baseboard/brox/gpio.c M src/mainboard/google/brox/variants/brox/gpio.c 4 files changed, 38 insertions(+), 220 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/79295/1 diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index 08a0656..806014a 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -47,6 +47,7 @@ select SOC_INTEL_CRASHLOG select SOC_INTEL_RAPTORLAKE select SOC_INTEL_ALDERLAKE_PCH_P + select DRIVERS_INTEL_ISH select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_TI50 diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index 2b73ad2..c50b8e6 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -170,22 +170,21 @@ device ref i2c3 on end device ref heci1 on end device ref sata on end - device ref pcie_rp8 on - # Enable SD Card PCIE 8 using clk 3 - register "pch_pcie_rp[PCH_RP(8)]" = "{ - .clk_src = 3, + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 3 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_req = 3, - .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, - }" - end #PCIE8 SD card - device ref pcie_rp9 on - # Enable NVMe PCIE 9 using clk 1 - register "pch_pcie_rp[PCH_RP(9)]" = "{ - .clk_src = 1, - .clk_req = 1, + .clk_src = 3, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" - end #PCIE9-12 SSD + end + device ref ish on + chip drivers/intel/ish + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end + device ref ufs on end device ref uart0 on end device ref gspi1 on end device ref pch_espi on diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c index daf1b96..5e760c0 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c @@ -145,12 +145,12 @@ PAD_CFG_GPI_INT(GPP_D3, NONE, PLTRST, LEVEL), /* GPP_D4 : [NF1: IMGCLKOUT0 NF2: BK4 NF5: SBK4 NF6: USB_C_GPP_D4] ==> SOC_GPP_D4 */ PAD_NC(GPP_D4, NONE), - /* GPP_D5 : SRCCLKREQ0_L ==> PCIE_CLKREQ0_ODL */ - PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* GPP_D5 : SRCCLKREQ0_L ==> NC */ + PAD_NC(GPP_D5, NONE), /* GPP_D6 : [NF1: SRCCLKREQ1# NF6: USB_C_GPP_D6] ==> WLAN_CLKREQ_ODL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), - /* GPP_D7 : SRCCLKREQ2_L ==> PCIE_CLKREQ2_ODL */ - PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* GPP_D7 : SRCCLKREQ2_L ==> NC */ + PAD_NC(GPP_D7, NONE), /* GPP_D8 : [NF1: SRCCLKREQ3# NF6: USB_C_GPP_D8] ==> SSD_CLKREQ_ODL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* GPP_D9 : [NF1: ISH_SPI_CS# NF2: DDP3_CTRLCLK NF4: TBT_LSX2_TXD NF5: BSSB_LS2_RX NF6: USB_C_GPP_D9 NF7: GSPI2_CS0#] ==> USB_C2_LSX_TX */ @@ -158,7 +158,7 @@ /* GPP_D10 : [NF1: ISH_SPI_CLK NF2: DDP3_CTRLDATA NF4: TBT_LSX2_RXD NF5: BSSB_LS2_TX NF6: USB_C_GPP_D10 NF7: GSPI2_CLK] ==> USB_C2_LSX_RX_STRAP */ PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4), /* GPP_D11 : [] ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_D11, 0, DEEP), + PAD_CFG_GPO(GPP_D11, 1, DEEP), /* GPP_D12 : [NF1: ISH_SPI_MOSI NF2: DDP4_CTRLDATA NF4: TBT_LSX3_RXD NF5: BSSB_LS3_TX NF6: USB_C_GPP_D12 NF7: GSPI2_MOSI] ==> SOC_GPP_D12 */ PAD_NC(GPP_D12, DN_20K), /* GPP_D13 : [NF1: ISH_UART0_RXD NF3: I2C6_SDA NF6: USB_C_GPP_D13] ==> UART0_ISH_RX_DBG_TX */ @@ -261,8 +261,8 @@ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF3), /* GPP_F18 : [NF3: THC1_SPI2_INT# NF6: USB_C_GPP_F18] ==> TCHSCR_INT_ODL */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF3), - /* GPP_F19 : SRCCLKREQ6 ==> PCIE_CLKREQ5_ODL */ - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* GPP_F19 : SRCCLKREQ6 ==> NC */ + PAD_NC(GPP_F19, NONE), /* GPP_F20 : [NF1: Reserved NF6: USB_C_GPP_F20] ==> SOC_GPP_F20 */ PAD_NC(GPP_F20, NONE), /* GPP_F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> SOC_GPP_F21 */ @@ -306,16 +306,16 @@ PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* GPP_H18 : [NF1: PROC_C10_GATE# NF6: USB_C_GPP_H18] ==> CPU_C10_GATE_L */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), - /* GPP_H19 : SRCCLKREQ4_L ==> PCIE_CLKREQ4_ODL */ - PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + /* GPP_H19 : SRCCLKREQ4_L ==> NC */ + PAD_NC(GPP_H19, NONE), /* GPP_H20 : IMGCLKOUT1 ==> BOARD_ID7 */ PAD_CFG_GPI(GPP_H20, NONE, DEEP), /* GPP_H21 : [NF1: IMGCLKOUT2 NF6: USB_C_GPP_H21] ==> SOC_GPP_H21 */ PAD_NC(GPP_H21, NONE), /* GPP_H22 : IMGCLKOUT3 ==> BOARD_ID8 */ PAD_CFG_GPI(GPP_H22, NONE, DEEP), - /* GPP_H23 : SRCCLKREQ5_L ==> PCIE_CLKREQ5_ODL */ - PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1), + /* GPP_H23 : SRCCLKREQ5_L ==> NC */ + PAD_NC(GPP_H23, NONE), /* GPP_R0 : [NF1: HDA_BCLK NF2: I2S0_SCLK NF3: DMIC_CLK_B0 NF4: HDAPROC_BCLK] ==> HDA_HP_BCLK_R */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), @@ -379,6 +379,18 @@ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_F9, 0, DEEP), + /* GPP_D11 : [] ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_S0, NONE, DEEP), + /* F21 : EXT_PWR_GATE2# ==> NC */ + PAD_NC(GPP_F21, NONE), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), }; const struct pad_config *__weak variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/google/brox/variants/brox/gpio.c b/src/mainboard/google/brox/variants/brox/gpio.c index 444adc4..5805bee 100644 --- a/src/mainboard/google/brox/variants/brox/gpio.c +++ b/src/mainboard/google/brox/variants/brox/gpio.c @@ -4,213 +4,19 @@ #include <boardid.h> #include <soc/gpio.h> -static const struct pad_config board_id0_1_overrides[] = { - /* B2 : VRALERT# ==> NC */ - PAD_NC(GPP_B2, NONE), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), - /* B15 : TIME_SYNC0 ==> NC */ - PAD_NC(GPP_B15, NONE), - /* C3 : SML0CLK ==> NC */ - PAD_NC(GPP_C3, NONE), - /* C4 : SML0DATA ==> NC */ - PAD_NC(GPP_C4, NONE), - /* D13 : ISH_UART0_RXD ==> PCH_I2C_CAM_SDA */ - PAD_CFG_NF(GPP_D13, NONE, DEEP, NF3), - /* D14 : ISH_UART0_TXD ==> PCH_I2C_CAM_SCL */ - PAD_CFG_NF(GPP_D14, NONE, DEEP, NF3), - /* F19 : SRCCLKREQ6# ==> WWAN_SIM1_DET_OD */ - PAD_CFG_GPI(GPP_F19, UP_20K, DEEP), - /* F20 : EXT_PWR_GATE# ==> HPS_RST_R */ - PAD_CFG_GPO(GPP_F20, 0, DEEP), - /* F21 : EXT_PWR_GATE2# ==> WAKE_ON_WWAN_ODL */ - PAD_NC(GPP_F21, NONE), - /* H13 : I2C7_SCL ==> EN_PP3300_SD */ - PAD_CFG_GPO(GPP_H13, 1, DEEP), - /* H21 : IMGCLKOUT2 ==> WLAN_INT_L */ - PAD_CFG_GPI_APIC(GPP_H21, NONE, DEEP, EDGE_SINGLE, NONE), - /* GPD2: LAN_WAKE# ==> NC */ - PAD_NC(GPD2, NONE), -}; - -/* Early pad configuration in bootblock for board id < 2 */ -static const struct pad_config early_gpio_table[] = { - /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), - /* - * D1 : ISH_GP1 ==> FP_RST_ODL - * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. - * To ensure proper power sequencing for the FPMCU device, reset signal is driven low - * early on in bootblock, followed by enabling of power. Reset signal is deasserted - * later on in ramstage. Since reset signal is asserted in bootblock, it results in - * FPMCU not working after a S3 resume. This is a known issue. - */ - PAD_CFG_GPO(GPP_D1, 0, DEEP), - /* D2 : ISH_GP2 ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_D2, 1, DEEP), - /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */ - PAD_CFG_GPO(GPP_E0, 0, DEEP), - /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ - PAD_CFG_GPI(GPP_E13, NONE, DEEP), - /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */ - PAD_CFG_GPO(GPP_E16, 0, DEEP), - /* E15 : RSVD_TP ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), - /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_F18, NONE, DEEP), - /* F21 : EXT_PWR_GATE2# ==> NC */ - PAD_NC(GPP_F21, NONE), - /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), - /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), - /* H13 : I2C7_SCL ==> EN_PP3300_SD */ - PAD_CFG_GPO(GPP_H13, 1, DEEP), -}; - -/* Early pad configuration in bootblock for board id 2 */ -static const struct pad_config early_gpio_table_id2[] = { - /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */ - PAD_CFG_GPO(GPP_A12, 1, DEEP), - /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), - /* B4 : PROC_GP3 ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_B4, 0, DEEP), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), - /* - * D1 : ISH_GP1 ==> FP_RST_ODL - * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. - * To ensure proper power sequencing for the FPMCU device, reset signal is driven low - * early on in bootblock, followed by enabling of power. Reset signal is deasserted - * later on in ramstage. Since reset signal is asserted in bootblock, it results in - * FPMCU not working after a S3 resume. This is a known issue. - */ - PAD_CFG_GPO(GPP_D1, 0, DEEP), - /* D2 : ISH_GP2 ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_D2, 1, DEEP), - /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_D11, 1, DEEP), - /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */ - PAD_CFG_GPO(GPP_E0, 0, DEEP), - /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ - PAD_CFG_GPI(GPP_E13, NONE, DEEP), - /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */ - PAD_CFG_GPO(GPP_E16, 0, DEEP), - /* E15 : RSVD_TP ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), - /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_F18, NONE, DEEP), - /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */ - PAD_CFG_GPO(GPP_F21, 0, DEEP), - /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), - /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), - /* H13 : I2C7_SCL ==> EN_PP3300_SD */ - PAD_NC(GPP_H13, UP_20K), -}; - -/* Early pad configuration in bootblock for board id 4 */ -static const struct pad_config early_gpio_table_id4[] = { - /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */ - PAD_CFG_GPO(GPP_A12, 1, DEEP), - /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), - /* B4 : PROC_GP3 ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_B4, 0, DEEP), - /* H6 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), - /* H7 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), - /* - * D1 : ISH_GP1 ==> FP_RST_ODL - * FP_RST_ODL comes out of reset as hi-z and does not have an external - * pull-down. To ensure proper power sequencing for the FPMCU device, - * reset signal is driven low early on in bootblock, followed by - * enabling of power. Reset signal is deasserted later on in ramstage. - * Since reset signal is asserted in bootblock, it results in FPMCU not - * working after a S3 resume. This is a known issue. - */ - PAD_CFG_GPO(GPP_D1, 0, DEEP), - /* D2 : ISH_GP2 ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_D2, 1, DEEP), - /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_D11, 1, DEEP), - /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */ - PAD_CFG_GPO(GPP_E0, 0, DEEP), - /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ - PAD_CFG_GPI(GPP_E13, NONE, DEEP), - /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */ - PAD_CFG_GPO(GPP_E16, 0, DEEP), - /* E15 : RSVD_TP ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), - /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_F18, NONE, DEEP), - /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */ - PAD_CFG_GPO(GPP_F21, 0, DEEP), - /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), - /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), - /* H13 : I2C7_SCL ==> EN_PP3300_SD */ - PAD_NC(GPP_H13, UP_20K), -}; static const struct pad_config romstage_gpio_table[] = { - /* B4 : PROC_GP3 ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_B4, 1, DEEP), - /* Enable touchscreen, hold in reset */ - /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ - PAD_CFG_GPO(GPP_C0, 1, DEEP), - /* C1 : SMBDATA ==> USI_RST_L */ - PAD_CFG_GPO(GPP_C1, 0, DEEP), - - /* D1 : ISH_GP1 ==> FP_RST_ODL */ - PAD_CFG_GPO(GPP_D1, 0, DEEP), - /* D2 : ISH_GP2 ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_D2, 0, DEEP), - - /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ - PAD_CFG_GPO(GPP_F21, 1, DEEP), + /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_F9, 1, DEEP), }; const struct pad_config *variant_gpio_override_table(size_t *num) { - const uint32_t id = board_id(); - if (id == BOARD_ID_UNKNOWN || id < 2) { - *num = ARRAY_SIZE(board_id0_1_overrides); - return board_id0_1_overrides; - } - *num = 0; return NULL; } -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - const uint32_t id = board_id(); - if (id == BOARD_ID_UNKNOWN || id < 2) { - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; - } else if (id >= 4) { - *num = ARRAY_SIZE(early_gpio_table_id4); - return early_gpio_table_id4; - } - - *num = ARRAY_SIZE(early_gpio_table_id2); - return early_gpio_table_id2; -} - const struct pad_config *variant_romstage_gpio_table(size_t *num) { *num = ARRAY_SIZE(romstage_gpio_table); -- To view, visit https://review.coreboot.org/c/coreboot/+/79295?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I88922bcfa13652006aa10078c3c444624fd4575e Gerrit-Change-Number: 79295 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: mb/google/brox: Set TPM i2c config in device tree
by Shelley Chen (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Eric Lai, Ivy Jian, Nick Vaccaro. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79101?usp=email ) Change subject: mb/google/brox: Set TPM i2c config in device tree ...................................................................... Patch Set 2: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79101/comment/94c42015_6ce703ea : PS1, Line 7: Set ic2 configs in device tree > nit: mb/google/brox: Done File src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb: https://review.coreboot.org/c/coreboot/+/79101/comment/15910bfe_83439380 : PS1, Line 88: .i2c[0] = { : .speed = I2C_SPEED_FAST, : .rise_time_ns = 650, : .fall_time_ns = 400, : .data_hold_time_ns = 50, : }, : .i2c[1] = { : .speed = I2C_SPEED_FAST, : .rise_time_ns = 650, : .fall_time_ns = 400, : .data_hold_time_ns = 50, : }, : .i2c[2] = { : .speed = I2C_SPEED_FAST, : .rise_time_ns = 900, : .fall_time_ns = 400, : .data_hold_time_ns = 50, : }, : .i2c[3] = { : .early_init = 1, : .speed = I2C_SPEED_FAST, : .rise_time_ns = 600, : .fall_time_ns = 400, : .data_hold_time_ns = 50, : }, : .i2c[5] = { : .speed = I2C_SPEED_FAST, : .rise_time_ns = 650, : .fall_time_ns = 400, : .data_hold_time_ns = 50, : }, : > These need to change appropriately. Hey Nick, in the past we could set these with through tuning with the help of a hw engineer. Can you help advise me on how we can do this before we get the actual hardware? https://review.coreboot.org/c/coreboot/+/79101/comment/534fec9a_0d834bc5 : PS1, Line 169: device ref i2c1 on > i2c4 Done https://review.coreboot.org/c/coreboot/+/79101/comment/2dacdfda_6aecd198 : PS1, Line 172: register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D1_IRQ)" > should it be GPP_E2_IRQ? I see GPP_E2 for GSC_PCH_INT_ODL in gpio. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10a7463effd85aec4551385963197bc1021319fe Gerrit-Change-Number: 79101 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-CC: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 28 Nov 2023 06:48:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/brox: Set TPM i2c config in device tree
by Shelley Chen (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Shelley Chen. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79101?usp=email to look at the new patch set (#3). Change subject: mb/google/brox: Set TPM i2c config in device tree ...................................................................... mb/google/brox: Set TPM i2c config in device tree Insert TPM device into i2c4 slot in the device tree. Also make sure the GPIO for GSC_PCH_INT_ODL is set correctly. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I10a7463effd85aec4551385963197bc1021319fe Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb 1 file changed, 11 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/79101/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10a7463effd85aec4551385963197bc1021319fe Gerrit-Change-Number: 79101 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-CC: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: Update vboot submodule to upstream main
by Uwe Poeche (Code Review) 28 Nov '23

28 Nov '23

Uwe Poeche has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78865?usp=email ) Change subject: Update vboot submodule to upstream main ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > We've already landed dependencies on this now, so let me just try to forward fix. […] done; it works -- To view, visit https://review.coreboot.org/c/coreboot/+/78865?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic7ecdabcdd26df349b8abf1c5a77c806facfe1d8 Gerrit-Change-Number: 78865 Gerrit-PatchSet: 4 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Comment-Date: Tue, 28 Nov 2023 06:42:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/brox: Set TPM i2c config in device tree
by Shelley Chen (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Shelley Chen. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79101?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/brox: Set TPM i2c config in device tree ...................................................................... mb/google/brox: Set TPM i2c config in device tree Insert TPM device into i2c4 slot in the device tree. Also make sure the GPIO for GSC_PCH_INT_ODL is set correctly. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I10a7463effd85aec4551385963197bc1021319fe Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb 1 file changed, 11 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/79101/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10a7463effd85aec4551385963197bc1021319fe Gerrit-Change-Number: 79101 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-CC: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/brox: Fix configuration for TPM in Kconfig
by Shelley Chen (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Ivy Jian, Karthik Ramasubramanian, Nick Vaccaro, Paul Menzel, Shelley Chen. Hello Eric Lai, Karthik Ramasubramanian, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79102?usp=email to look at the new patch set (#3). Change subject: mb/google/brox: Fix configuration for TPM in Kconfig ...................................................................... mb/google/brox: Fix configuration for TPM in Kconfig On Brox, TPM is using i2c4 and GPP_E1, so modifying the Kconfig to reflect this. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I0ecaa6fcfc05c3c2e55f857d7a4e59fe46096bb5 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/brox/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/79102/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79102?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ecaa6fcfc05c3c2e55f857d7a4e59fe46096bb5 Gerrit-Change-Number: 79102 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/brox: Fix configuration for TPM in Kconfig
by Eric Lai (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Ivy Jian, Karthik Ramasubramanian, Nick Vaccaro, Paul Menzel, Shelley Chen. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79102?usp=email ) Change subject: mb/google/brox: Fix configuration for TPM in Kconfig ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79102?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ecaa6fcfc05c3c2e55f857d7a4e59fe46096bb5 Gerrit-Change-Number: 79102 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 28 Nov 2023 06:34:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brox: Fix configuration for TPM in Kconfig
by Shelley Chen (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Eric Lai, Ivy Jian, Nick Vaccaro, Paul Menzel. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79102?usp=email ) Change subject: mb/google/brox: Fix configuration for TPM in Kconfig ...................................................................... Patch Set 2: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79102/comment/d49928c7_feba9572 : PS1, Line 7: Fix configuration for TPM in Kconfig > If possible, please be more specific. Acknowledged. Added description. https://review.coreboot.org/c/coreboot/+/79102/comment/7335ef60_77d8b093 : PS1, Line 7: Fix configuration for TPM in Kconfig > nit:mb/google/brox: Done https://review.coreboot.org/c/coreboot/+/79102/comment/19aa1a33_6377c0a4 : PS1, Line 8: > Please elaborate. Done File src/mainboard/google/brox/Kconfig: https://review.coreboot.org/c/coreboot/+/79102/comment/d90f7d74_291a5fd4 : PS1, Line 90: 33 > Hi Nick, […] Done https://review.coreboot.org/c/coreboot/+/79102/comment/c547d2e6_a2da8ca1 : PS1, Line 90: default 33 # GPE0_DW1_01 (GPP_D01) > should it be 66 #GPE0_DW2_02 (GPP_E2)? I see GPP_E2 for GSC_PCH_INT_ODL in gpio. […] You are 100% correct. Thanks for catching this. -- To view, visit https://review.coreboot.org/c/coreboot/+/79102?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ecaa6fcfc05c3c2e55f857d7a4e59fe46096bb5 Gerrit-Change-Number: 79102 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 28 Nov 2023 06:26:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2023