coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

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[NoOp] Change in coreboot[main]: mb/apple/macbookair4_2: Drop obsolete spd.bin file
by Felix Held (Code Review) 14 Nov '23

14 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78784?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/apple/macbookair4_2: Drop obsolete spd.bin file ...................................................................... mb/apple/macbookair4_2: Drop obsolete spd.bin file After commit 940fe080bf1e (mb/apple/macbookair4_2: Correctly implement SPD mapping the Haswell way), this file is obsolete and can be removed. Change-Id: I5afe6809c7097ab8529a3c1ec7befbd0d6f01c5f Signed-off-by: Keith Hui <buurin(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78784 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- D src/mainboard/apple/macbookair4_2/spd.bin 1 file changed, 0 insertions(+), 0 deletions(-) Approvals: Martin L Roth: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/apple/macbookair4_2/spd.bin b/src/mainboard/apple/macbookair4_2/spd.bin deleted file mode 100644 index 6e2738f..0000000 --- a/src/mainboard/apple/macbookair4_2/spd.bin +++ /dev/null Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/78784?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5afe6809c7097ab8529a3c1ec7befbd0d6f01c5f Gerrit-Change-Number: 78784 Gerrit-PatchSet: 4 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Evgeny Sorokin <me(a)ch1p.io> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/lenovo/t530/early_init.c: Drop unused and revise used includes
by Felix Held (Code Review) 14 Nov '23

14 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78783?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/lenovo/t530/early_init.c: Drop unused and revise used includes ...................................................................... mb/lenovo/t530/early_init.c: Drop unused and revise used includes With commit adaeb1102186 (nb/intel/sandybridge: Clean up post Haswell SPD mapping API migration), raminit_native.h now only includes 4 other headers and offers no original content. Based on the idea that all source files should include what they use directly, drop it in favor of sandybridge.h (which it already includes anyway) and types.h (replacing stdint.h because it also uses boolean constructs). Board appears to not use anything sb/intel/bd82x6x/pch.h provides. And the board still builds after dropping it. Change-Id: I1b201fe4dd29bac5feb08f372d1e36353eac161d Signed-off-by: Keith Hui <buurin(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78783 Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/lenovo/t530/early_init.c 1 file changed, 1 insertion(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/mainboard/lenovo/t530/early_init.c b/src/mainboard/lenovo/t530/early_init.c index 4983410..b6bfa5f 100644 --- a/src/mainboard/lenovo/t530/early_init.c +++ b/src/mainboard/lenovo/t530/early_init.c @@ -1,10 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <types.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/bd82x6x/pch.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <device/device.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/78783?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1b201fe4dd29bac5feb08f372d1e36353eac161d Gerrit-Change-Number: 78783 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: intelmetool: Add PCI ID for TGL-U, ADL-P, ADL-S
by Maciej Pijanowski (Code Review) 14 Nov '23

14 Nov '23

Attention is currently required from: Christian Walter, Michał Żygowski. Maciej Pijanowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73972?usp=email ) Change subject: intelmetool: Add PCI ID for TGL-U, ADL-P, ADL-S ...................................................................... Patch Set 3: (1 comment) File util/intelmetool/intelmetool.h: https://review.coreboot.org/c/coreboot/+/73972/comment/a9663761_23ce2775 : PS1, Line 441: #define PCI_DEVICE_ID_INTEL_TIGERLAKE 0xA0E0 /* Tiger Lake */ : #define PCI_DEVICE_ID_INTEL_ALDERLAKE_P 0x51E0 /* Alder Lake P */ : #define PCI_DEVICE_ID_INTEL_ALDERLAKE_S 0x7AE8 /* Alder Lake S */ > I would add all CSE IDs from src/include/device/pci_ids.h for the respective microarchitectures. […] I think that was fixed, would you like to take a look again? -- To view, visit https://review.coreboot.org/c/coreboot/+/73972?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c2617a8e2f77f322f43b93ef1083576faaa42a8 Gerrit-Change-Number: 73972 Gerrit-PatchSet: 3 Gerrit-Owner: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Comment-Date: Tue, 14 Nov 2023 21:49:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/system76/rpl: Allow 5600 MT/s memory for RPL-HX
by Matt DeVillier (Code Review) 14 Nov '23

14 Nov '23

Attention is currently required from: Jeremy Soller, Tim Crawford. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78912?usp=email ) Change subject: mb/system76/rpl: Allow 5600 MT/s memory for RPL-HX ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78912?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9bb0435769c70c1db06d2c5cca2dd28eb5331f49 Gerrit-Change-Number: 78912 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ilikenwf <mparnell(a)gmail.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Tue, 14 Nov 2023 21:43:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/brox: Set unstuffed straps to NC
by Shelley Chen (Code Review) 14 Nov '23

14 Nov '23

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78951?usp=email ) Change subject: mb/google/brox: Set unstuffed straps to NC ...................................................................... mb/google/brox: Set unstuffed straps to NC All of these signals have net names, but are actually unstuffed, so we have to set them to NC. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I27d8b7cd02aefb49a2dc031a30eb0d1e8aa9faa9 Signed-off-by: Shelley Chen <shchen(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78951 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/gpio.c 1 file changed, 15 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c index 886fdf2..daf1b96 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c @@ -19,8 +19,8 @@ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* GPD1 : [NF1: ACPRESENT] ==> ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), - /* GPD2 : [NF1: LAN_WAKE#] ==> PCH_WAKE_ODL */ - PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + /* GPD2 : [NF1: LAN_WAKE#] ==> SOC_GPD2 */ + PAD_NC(GPD2, NONE), /* GPD3 : [NF1: PWRBTN#] ==> EC_PCH_PWR_BTN_ODL */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* GPD4 : [NF1: SLP_S3#] ==> SLP_S3_R_L */ @@ -29,8 +29,8 @@ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* GPD6 : [NF1: SLP_A#] ==> SLP_A_L_CAP_SITE */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), - /* GPD7 : GPD7_STRAP ==> Component NC */ - PAD_NC(GPD7, NONE), + /* GPD7 : GPD7_STRAP ==> SOC_GPD7_STRAP */ + PAD_NC(GPD7, DN_20K), /* GPD8 : [NF1: SUSCLK] ==> PCH_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9 : [NF1: SLP_WLAN#] ==> SLP_WLAN_L_CAP_SITE */ @@ -96,9 +96,9 @@ /* GPP_B6 : [NF1: ISH_I2C0_SCL NF2: I2C2_SCL NF6: USB_C_GPP_B6] ==> ISH_I2C_SENSOR_SCL */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), /* GPP_B7 : [NF1: ISH_I2C1_SDA NF2: I2C3_SDA NF6: USB_C_GPP_B7] ==> SOC_I2C3_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + PAD_NC(GPP_B7, NONE), /* GPP_B8 : [NF1: ISH_I2C1_SCL NF2: I2C3_SCL NF6: USB_C_GPP_B8] ==> SOC_I2C3_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + PAD_NC(GPP_B8, NONE), /* GPP_B11 : [NF1: PMCALERT# NF6: USB_C_GPP_B11] ==> SOC_I2C_PD_INT_ODL */ PAD_CFG_GPI_APIC_LOCK(GPP_B11, NONE, LEVEL, INVERT, LOCK_CONFIG), /* GPP_B12 : [NF1: SLP_S0# NF6: USB_C_GPP_B12] ==> SLP_S0_R_L */ @@ -113,8 +113,8 @@ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), /* GPP_B17 : [NF2: I2C5_SCL NF4: ISH_I2C2_SCL NF6: USB_C_GPP_B17] ==> ISH_I2C_EC_SCL */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), - /* GPP_B18 : GPP_B18_STRAP ==> Component NC */ - PAD_CFG_GPI(GPP_B18, DN_20K, DEEP), + /* GPP_B18 : GPP_B18 ==> GPP_B18_STRAP */ + PAD_NC(GPP_B18, DN_20K), /* GPP_B23 : SML1ALERT_L/PCHHOT_L ==> PCHHOT_ODL_STRAP */ PAD_CFG_GPI(GPP_B23, DN_20K, DEEP), @@ -123,7 +123,7 @@ /* GPP_C1 : [NF1: SMBDATA NF6: USB_C_GPP_C1] ==> SOC_GPP_C1 */ PAD_NC(GPP_C1, NONE), /* GPP_C2 : SMBALAERT_L ==> SOC_GPP_C2_STRAP */ - PAD_CFG_GPI(GPP_C2, DN_20K, DEEP), + PAD_NC(GPP_C2, DN_20K), /* GPP_C3 : [NF1: SML0CLK NF6: USB_C_GPP_C3] ==> SMB_SML0_CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* GPP_C4 : [NF1: SML0DATA NF6: USB_C_GPP_C4] ==> SMB_SML0_DAT */ @@ -160,7 +160,7 @@ /* GPP_D11 : [] ==> EN_PP3300_SSD */ PAD_CFG_GPO(GPP_D11, 0, DEEP), /* GPP_D12 : [NF1: ISH_SPI_MOSI NF2: DDP4_CTRLDATA NF4: TBT_LSX3_RXD NF5: BSSB_LS3_TX NF6: USB_C_GPP_D12 NF7: GSPI2_MOSI] ==> SOC_GPP_D12 */ - PAD_CFG_NF(GPP_D12, NONE, DEEP, NF6), + PAD_NC(GPP_D12, DN_20K), /* GPP_D13 : [NF1: ISH_UART0_RXD NF3: I2C6_SDA NF6: USB_C_GPP_D13] ==> UART0_ISH_RX_DBG_TX */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), /* GPP_D14 : [NF1: ISH_UART0_TXD NF3: I2C6_SCL NF6: USB_C_GPP_D14] ==> UART0_ISH_TX_DBG_RX */ @@ -219,9 +219,9 @@ /* GPP_E20 : [NF1: DDP2_CTRLCLK NF4: TBT_LSX1_TXD NF5: BSSB_LS1_RX NF6: USB_C_GPP_E20] ==> SOC_GPP_E20 */ PAD_NC(GPP_E20, NONE), /* GPP_E21 : DDP2_CTRLDATA/TBT_LSX1_RXD/BSSB_LS1_TX ==> USB_C1_LSX_RX_STRAP */ - PAD_CFG_GPI(GPP_E21, NONE, DEEP), + PAD_NC(GPP_E21, DN_20K), /* GPP_E22 : DDPA_CTRLCLK/DNX_FORCE_RELOAD ==> USB_C0_AUX_DC_STRAP_P */ - PAD_CFG_GPO(GPP_E22, 0, DEEP), + PAD_NC(GPP_E22, DN_20K), /* GPP_E23 : [NF1: DDPA_CTRLDATA] ==> USB_C0_AUX_DC_N */ PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6), @@ -244,7 +244,7 @@ /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_F9, 1, PLTRST), /* GPP_F10 : GPP_F10 ==> GPP_F10_STRAP */ - PAD_CFG_GPI(GPP_F10, DN_20K, DEEP), + PAD_NC(GPP_F10, DN_20K), /* GPP_F11 : [NF3: THC1_SPI2_CLK NF4: GSPI1_CLK NF6: USB_C_GPP_F11] ==> SOC_GPP_F11 */ PAD_NC(GPP_F11, NONE), /* GPP_F12 : [NF1: GSXDOUT NF3: THC1_SPI2_IO0 NF4: GSPI1_MOSI NF5: I2C1A_SCL NF6: USB_C_GPP_F12] ==> SOC_GPP_F12 */ @@ -273,9 +273,9 @@ PAD_NC(GPP_F23, NONE), /* GPP_H0 : [NF6: USB_C_GPP_H0] ==> GPP_H0_BOOT_STRAP1 */ - PAD_CFG_GPI(GPP_H0, NONE, DEEP), + PAD_NC(GPP_H0, DN_20K), /* GPP_H1 : [NF6: USB_C_GPP_H1] ==> GPP_H1_BOOT_STRAP2 */ - PAD_CFG_GPI(GPP_H1, NONE, DEEP), + PAD_NC(GPP_H1, DN_20K), /* GPP_H2 : [NF6: USB_C_GPP_H2] ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_H2, 1, DEEP), /* GPP_H3 : [NF1: SX_EXIT_HOLDOFF# NF6: USB_C_GPP_H3] ==> WLAN_PCIE_WAKE_ODL */ -- To view, visit https://review.coreboot.org/c/coreboot/+/78951?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I27d8b7cd02aefb49a2dc031a30eb0d1e8aa9faa9 Gerrit-Change-Number: 78951 Gerrit-PatchSet: 4 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[NoOp] Change in coreboot[main]: mb/prodrive/atlas: Update the VBT blob for ADL-P MR5 FSP
by Maximilian Brune (Code Review) 14 Nov '23

14 Nov '23

Attention is currently required from: Angel Pons, Christian Walter, Lean Sheng Tan, Paul Menzel. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79020?usp=email ) Change subject: mb/prodrive/atlas: Update the VBT blob for ADL-P MR5 FSP ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79020?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64229da1cb438de826e54dfc97d47d145fb4f0c9 Gerrit-Change-Number: 79020 Gerrit-PatchSet: 2 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Tue, 14 Nov 2023 21:31:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/prodrive/atlas: Remove the workaround for CLKREQ pins
by Maximilian Brune (Code Review) 14 Nov '23

14 Nov '23

Attention is currently required from: Angel Pons, Christian Walter, Lean Sheng Tan. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79021?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/prodrive/atlas: Remove the workaround for CLKREQ pins ...................................................................... Patch Set 3: (1 comment) File src/mainboard/prodrive/atlas/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/79021/comment/217dc124_dc5041a6 : PS3, Line 75: mcfg->CpuPcieRpClockReqMsgEnable[2] = 0; can you test if the ones for CPU are also still needed? wouldn't be surprised if they now magically worked too. -- To view, visit https://review.coreboot.org/c/coreboot/+/79021?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icbab617428551accda66499b7c2a32b2fa8c1689 Gerrit-Change-Number: 79021 Gerrit-PatchSet: 3 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Tue, 14 Nov 2023 21:30:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: nb/intel/sandybridge: Use SA devid to identify PC type
by Matt DeVillier (Code Review) 14 Nov '23

14 Nov '23

Attention is currently required from: Angel Pons, Arthur Heymans, Keith Hui, Patrick Rudolph. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78826?usp=email ) Change subject: nb/intel/sandybridge: Use SA devid to identify PC type ...................................................................... Patch Set 5: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78826/comment/0e642fe6_6c53c9a0 : PS5, Line 9: or of -- To view, visit https://review.coreboot.org/c/coreboot/+/78826?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibddf6c75d15ca7a99758c377ed956d483abe7ec1 Gerrit-Change-Number: 78826 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 14 Nov 2023 21:23:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: acpi: Add PPTT support
by David Milosevic (Code Review) 14 Nov '23

14 Nov '23

Attention is currently required from: Arthur Heymans, Cliff Huang, Lance Zhao, Martin L Roth, Maximilian Brune, Nico Huber, Patrick Rudolph, Tim Wawrzynczak. David Milosevic has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78071?usp=email ) Change subject: acpi: Add PPTT support ...................................................................... Patch Set 16: (1 comment) File src/acpi/acpi_pptt.c: https://review.coreboot.org/c/coreboot/+/78071/comment/391fa29f_199c5c4f : PS16, Line 79: > I guess now that we removed the other empty line, we should be consistent. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Gerrit-Change-Number: 78071 Gerrit-PatchSet: 16 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 14 Nov 2023 21:18:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: acpi: Add PPTT support
by David Milosevic (Code Review) 14 Nov '23

14 Nov '23

Attention is currently required from: Arthur Heymans, Cliff Huang, David Milosevic, Lance Zhao, Martin L Roth, Maximilian Brune, Patrick Rudolph, Tim Wawrzynczak. Hello Arthur Heymans, Cliff Huang, Lance Zhao, Maximilian Brune, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78071?usp=email to look at the new patch set (#17). Change subject: acpi: Add PPTT support ...................................................................... acpi: Add PPTT support This patch adds code to generate Processor Properties Topology Tables (PPTT) compliant to the ACPI 6.4 specification. - The 'acpi_get_pptt_topology' hook is mandatory once ACPI_PPTT is selected. Its purpose is to return a pointer to a topology tree, which describes the relationship between CPUs and caches. The hook can be provided by, for example, mainboard code. Background: We are currently working on mainboard code for qemu-sbsa and Neoverse N2. Both require a valid PPTT table. Patch was tested against the qemu-sbsa board. Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> --- M src/acpi/Kconfig M src/acpi/Makefile.inc M src/acpi/acpi.c A src/acpi/acpi_pptt.c M src/include/acpi/acpi.h 5 files changed, 312 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/78071/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/78071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Gerrit-Change-Number: 78071 Gerrit-PatchSet: 17 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2023