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Change subject: Documentation: add Nitrokey to distributions
......................................................................
Patch Set 4:
(1 comment)
File Documentation/distributions.md:
PS4:
> Please restore the original order. […]
okok, will do
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Change subject: drivers/intel/gma/opregion: Use CBFS cache to load VBT
......................................................................
Patch Set 33: Code-Review+2
(1 comment)
File src/drivers/intel/gma/opregion.c:
https://review.coreboot.org/c/coreboot/+/77886/comment/3a6dffda_c5f8f029 :
PS4, Line 27: cbfs_map
> According to cscope, `local_vbt()` is called before but also after FSP-S (during GMA initialization) […]
Yes, it's pretty common practice to leak when necessary (e.g. if the file needs to stay around for later like in this case). It's just a memory allocator, and things like this are exactly what it was meant for (as opposed to needing to manually create scratch buffer arrays everywhere like this file did before).
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Change subject: drivers/intel/gma/opregion: Use CBFS cache to load VBT
......................................................................
Patch Set 33:
(1 comment)
File src/drivers/intel/gma/opregion.c:
https://review.coreboot.org/c/coreboot/+/77886/comment/e1976240_10d04f38 :
PS4, Line 27: cbfs_map
> IIRC, locate_vbt() is called rather early in ramstage. Doesn't this mean […]
According to cscope, `local_vbt()` is called before but also after FSP-S (during GMA initialization). IMO, considering that CBFS cache is just a scratchpad (not a cache) and that `vbt.bin` is relatively small the only thing that really matters is that we do not call cbfs_map() multiple times. Also to my understanding, `cbfs_unmap()` can only unmap the latest mapped CBFS file. Therefor, if I add code to unmap it and some other CBFS files got loaded in between then unmap will silently fail.
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Hello Arthur Heymans, Eran Mitrani, Jakub Czapiga, Julius Werner, Kapil Porwal, Nick Vaccaro, Subrata Banik, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: drivers/intel/gma/opregion: Use CBFS cache to load VBT
......................................................................
drivers/intel/gma/opregion: Use CBFS cache to load VBT
Thanks to x86 CBFS cache support, we can leverage cbfs_map() function
to load the VBT binary regardless of if it is compressed or not.
Change-Id: I1e37e718a71bd85b0d7dee1efc4c0391798f16f7
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/drivers/intel/gma/Kconfig
M src/drivers/intel/gma/opregion.c
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/jasperlake/Kconfig
M src/soc/intel/meteorlake/Kconfig
M src/soc/intel/tigerlake/Kconfig
6 files changed, 25 insertions(+), 46 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/77886/33
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Change subject: soc/intel/cse: Add API to check if CSE Firmware update is required
......................................................................
Patch Set 14:
(1 comment)
Patchset:
PS14:
> Subrata, we rechecked this on a non serial image with GBB flags = 0 […]
Done
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Change subject: arch/x86/memcpy.c: Optimize code for 64bit
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/amd/mendocino: Update FSP-S UPD to pass boot logo
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Yes, it is coming next. I am setting up the individual pieces for this feature before enabling it.
Acknowledged
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Change subject: mb/google/guybrush: Set PS2K_IRQ to level/low
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/78137/comment/6411c0a5_d53ab058 :
PS3, Line 12: From https://review.coreboot.org/c/coreboot/+/54924:
git operates with the hashes (74bce48f1d445053b217913df79a77dfe286e893), so I’d use that.
https://review.coreboot.org/c/coreboot/+/78137/comment/29677777_e0ddd6c5 :
PS3, Line 13: > The default state for the IRQ lines when the eSPI controller comes
: > out of reset is high. This is because the IRQ lines are shared with
: > the other IRQ sources using AND gates. This means that in order to
: > not cause any spurious interrupts or miss any interrupts, the
: > IO-APIC must use a low polarity trigger.
Remove the trailing two spaces?
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Hello Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/78826?usp=email
to look at the new patch set (#2).
Change subject: nb/intel/sandybridge: Use SA devid to identify PC type
......................................................................
nb/intel/sandybridge: Use SA devid to identify PC type
Instead or using MSR IA32_PLATFORM_ID read the SystemAgent device id
to figure out the PC type. This follows the BWG which suggest to not
use MSR IA32_PLATFORM_ID for system identification.
Change-Id: Ibddf6c75d15ca7a99758c377ed956d483abe7ec1
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/cpu/intel/model_206ax/Makefile.inc
D src/cpu/intel/model_206ax/common.c
M src/northbridge/intel/sandybridge/common.c
3 files changed, 11 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/78826/2
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Change subject: soc/intel/cse: Add API to check if CSE Firmware update is required
......................................................................
Patch Set 14:
(1 comment)
Patchset:
PS14:
> > As I was testing this feature, I added timestamps around this function call and it takes about 17 […]
Subrata, we rechecked this on a non serial image with GBB flags = 0
The measured time is negligible around 14 microseconds.
980:<unknown> 555,796 (15,690)
981:<unknown> 555,811 (14)
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