Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78821?usp=email )
Change subject: vboot: Add catchall recovery reason for unspecified phase 4 errors
......................................................................
vboot: Add catchall recovery reason for unspecified phase 4 errors
The code for "phase 4" of firmware verification currently only sets a
recovery reason when there's an actual hash mismatch detected in
vb2api_check_hash_get_digest(). This is the most likely way how this
section of code can fail but not the only one. If any other unexpected
issue occurs, we should still set a recovery reason rather than just
reboot and risk an infinite boot loop.
This patch adds a catchall recovery reason for any error code that falls
out of this block of code. If a more specific recovery reason had
already been set beforehand, we'll continue to use that -- if not, we'll
set VB2_RECOVERY_FW_GET_FW_BODY.
Change-Id: If00f8f8a5d17aa113e0325aad58d367f244aca49
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78821
Reviewed-by: Yu-Ping Wu <yupingso(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/security/vboot/vboot_logic.c
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Yu-Ping Wu: Looks good to me, approved
diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c
index 11983b9..93a188c 100644
--- a/src/security/vboot/vboot_logic.c
+++ b/src/security/vboot/vboot_logic.c
@@ -374,7 +374,7 @@
}
if (rv)
- vboot_save_and_reboot(ctx, rv);
+ vboot_fail_and_reboot(ctx, VB2_RECOVERY_FW_GET_FW_BODY, rv);
vboot_save_data(ctx);
/* Only extend PCRs once on boot. */
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Gerrit-Change-Id: If00f8f8a5d17aa113e0325aad58d367f244aca49
Gerrit-Change-Number: 78821
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Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>
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Gerrit-MessageType: merged
Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78820?usp=email )
Change subject: Update vboot submodule to upstream main
......................................................................
Update vboot submodule to upstream main
Updating from commit id 24cb127a:
2023-08-21 Nicholas Bishop sign_uefi_unittest.py: Fix long-line lint
to commit id f2b01bf0:
2023-10-27 Julius Werner firmware: Undeprecate VB2_RECOVERY_FW_GET_FW_BODY
This brings in 47 new commits:
f2b01bf0 firmware: Undeprecate VB2_RECOVERY_FW_GET_FW_BODY
ef6d02df futility/vb2_helper: Add missing newline for error messages
886d13d7 PRESUBMIT: switch to cros format
ac2e1a75 host/lib: Decouple openssl headers from HOSTLIB
86ec05f7 futility: updater: Add help info for --quirks
2850244e futility: updater: Abort if the unlock_csme_* is used on a locked device
f1b5c88d devkeys: delete old unused firmware_bmpfv.bin
4444c5fe crossystem: Fix tpm_fwver for fwid < 12935
98ef339f 2lib: Prevent overwriting the value of fw_vboot2
c7517eb4 make_dev_ssd: support ChromeOS Kdump
8e3462cc tlcl: Increase the TPM_BUFFER_SIZE
740a2966 vboot_reference: Drop 'host' usage for 'internal' in flashrom.h
57877a44 vboot: Remove comments about physical dev switch
3401d16c 2lib: Fix typos, comments and formats
fdf52d45 scripts/: Drop deprecated {g,s}et_gbb_flags.sh scripts
bf76e9ee 2lib: Output the correct kernel_version
1ac4663e make_dev_firmware.sh: update pattern for matching wp status
c57ab9f7 2lib: Add recovery reason VB2_RECOVERY_WIDEVINE_PREPARE
e094ba31 tlcl: Reduce the variants of TPM2B
b047600d sign_official_build: support key config for pkcs11
f8712b73 vboot: support signing with pkcs11 private key
17fe786f strip_boot_from_image.sh: sfill fast
6c856cd3 futility/updater: Fix EC software write protection logic
1dc5a421 futility: update: Deprecate --unlock_me by --quirk unlock_csme_nissa
f0d88587 futility: update: Refactor the 'unlock ME' quirk(s)
81429ee9 futility: update: Do not update RO when the AP RO is locked
a3beb737 futility: update: Revise the ordering or quirks
2c1844fa futility: update: Remove unused quirk 'unlock_wilco_me_for_update'
75530d32 tests/futility: Test with new signer_config.csv based firmware updater
cba649fa 2lib: Expose 2hmac
ab015448 2lib: Refactor hmac to vb2_hmac_calculate
3545f8b4 Revert "sign_uefi: Remove exception catching"
55f625a9 dump_fmap: Add offset and size to flash_ec format output
a27ee336 keygeneration: add shellcheck source statements to help linting
055f9aa2 keygeneration: replace_recovery_key.sh: make minios key optional
6cb8ab60 scripts: delete unused values kernel command line
1f76c38b vboot: Drop phone recovery support
ccf6b037 scripts: Legacy fix for set_gbb_flags.sh
8f03069e futility: Add basic README.md
88963df8 utility: Query platform wp status with futility
6c3817d2 utility: Drop cros_alias technical debt in dev_debug_vboot
df85f512 scripts: Drop cros_alias technical debt in make_dev_firmware.sh
7395cd68 futility/updater_utils.c: Match on EC path to prepare for split
52518415 crossystem: Recover corrupted RW_NVRAM on flash writes
81f9ddaf futility/cmd_gbb_utility.md: Add basic GBB subcmd doc
c4995268 futility/: Fix define confusion
69dab5a6 crossystem: Avoid writing duplicate entries to RW_NVRAM
6c37b520 Revert "crossystem: stop supporting legacy chromeos_acpi driver"
Change-Id: Ic7ecd1755d26df349b8abf1c5a77c806facfe1d8
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78820
Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Reviewed-by: Eric Lai <ericllai(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso(a)google.com>
---
M 3rdparty/vboot
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Yu-Ping Wu: Looks good to me, approved
Eric Lai: Looks good to me, approved
Felix Singer: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/3rdparty/vboot b/3rdparty/vboot
index 24cb127..f2b01bf 160000
--- a/3rdparty/vboot
+++ b/3rdparty/vboot
@@ -1 +1 @@
-Subproject commit 24cb127a5e83a713131ab75cc39b11336019443c
+Subproject commit f2b01bf08a813fb3035102c7c948b78fa191e544
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78800?usp=email )
Change subject: arch/arm64/arch_timer: Fix possible overflow in multiplication
......................................................................
Patch Set 2:
(3 comments)
File src/arch/arm64/arch_timer.c:
https://review.coreboot.org/c/coreboot/+/78800/comment/eea52878_ae8cb645 :
PS2, Line 16: assert(tfreq > 0)
Missing semicolon (also, this is probably not necessary, you'll get a pretty obvious division-by-zero exception when this is not initialized anyway).
https://review.coreboot.org/c/coreboot/+/78800/comment/088f888b_eaa045be :
PS2, Line 18: div = gcd(mult, tfreq);
nit: depending on the GCD implementation you'll probably want to write it as `gcd(tfreq, mult)` to help it terminate a little faster (in the common case where tfreq is a multiple of mult).
https://review.coreboot.org/c/coreboot/+/78800/comment/107e6c51_75e29c0f :
PS2, Line 11: static uint32_t tfreq, mult;
: uint32_t div;
:
: if (tfreq == 0) {
: tfreq = raw_read_cntfrq_el0();
: assert(tfreq > 0)
: mult = 1000000;
: div = gcd(mult, tfreq);
: tfreq /= div;
: mult /= div;
: }
:
: long usecs = (tvalue * mult) / tfreq;
> Nice, but why not just cast `tvalue`, and let the compiler figure out the rest? Is that possible?
Not really sure what you want to cast it to? It's already 64-bit. The concern here is that even the 64-bit multiplication could overflow since the initialization value of CNTPCT is unknown.
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Change subject: lib: Add GCD function
......................................................................
Patch Set 1:
(2 comments)
File src/lib/gcd.c:
https://review.coreboot.org/c/coreboot/+/78798/comment/1b8583d5_6eb6b62e :
PS1, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */
Since we need to solve the same problem in libpayload, please put this in commonlib/bsd, and use a GCD implementation that is BSD-licensed. (In the majority of cases, at least for the timer problem, we'll just be trying to find the GCD between 1MHz and a multiple of 1MHz. So we probably don't need the most sophisticated GCD algorithm in the world, the simple modulus one should be good enough, it'll only take one iteration.)
https://review.coreboot.org/c/coreboot/+/78798/comment/8fb939cc_75e170da :
PS1, Line 20: *a ^= *b;
This hasn't been a good swap algorithm in 20+ years (see https://en.wikipedia.org/wiki/Register_renaming). Just use a temp variable, and I don't think this is worth factoring out into a separate function for a single use.
Oh, actually, looks like we already have a SWAP() in commonlib/helpers.h (part of <stdlib.h>) that you can use.
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Change subject: mb/google/guybrush: Set PS2K_IRQ to level/low
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
Matt DeVillier tested this and the EC change against Windows as well.
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Change subject: mb/google/guybrush: Set PS2K_IRQ to level/low
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/78137/comment/327dfaa9_ae990c85 :
PS3, Line 12: From https://review.coreboot.org/c/coreboot/+/54924:
> git operates with the hashes (74bce48f1d445053b217913df79a77dfe286e893), so I’d use that.
Done
https://review.coreboot.org/c/coreboot/+/78137/comment/90631dcc_bd8cb7f2 :
PS3, Line 13: > The default state for the IRQ lines when the eSPI controller comes
: > out of reset is high. This is because the IRQ lines are shared with
: > the other IRQ sources using AND gates. This means that in order to
: > not cause any spurious interrupts or miss any interrupts, the
: > IO-APIC must use a low polarity trigger.
> Remove the trailing two spaces?
Did you mean the leading spaces? I removed them.
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Change subject: mb/google/guybrush: Set PS2K_IRQ to level/low
......................................................................
mb/google/guybrush: Set PS2K_IRQ to level/low
On guybrush, keyboard presses are signaled by the EC via eSPI virtual
wire. The interrupt is shared with others and should be active low.
From 74bce48f1d4 ("mb/google/{zork,guybrush,skyrim},soc/amd/espi: Fix vw_irq_polarity"):
> The default state for the IRQ lines when the eSPI controller comes
> out of reset is high. This is because the IRQ lines are shared with
> the other IRQ sources using AND gates. This means that in order to
> not cause any spurious interrupts or miss any interrupts, the
> IO-APIC must use a low polarity trigger.
Setting `vw_irq_polarity` in the device tree provides an option to
invert interrupts from the eSPI controller, but the register is
initialized from verstage which is baked into RO.
As a workaround, the necessary interrupts on the EC have been
reconfigured to be active low, and we can modify the IO-APIC
accordingly.
EC related CL here: https://crrev.com/c/4891663
BUG=b:218874489
TEST=-`emerge-guybrush chromeos-ec coreboot chromeos-bootimage`
-Flash new RW fw and verify keyboard is functional
-`suspend_stress_test -c 1` and verify i8042 irq is removed as a
wake source
-`echo mem > /sys/power/state`. Press key and verify system wake
from i8042.
Cq-Depend: chromium:4891663
Change-Id: I7d093d94a666263684645ef724e945069c68c806
Signed-off-by: Mark Hasemeyer <markhas(a)google.com>
---
M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h
2 files changed, 5 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/78137/4
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Change subject: Documentation: add Nitrokey to distributions
......................................................................
Patch Set 5:
(1 comment)
File Documentation/distributions.md:
PS4:
> okok, will do
done -> restored original order
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Change subject: Documentation: add Nitrokey to distributions
......................................................................
Documentation: add Nitrokey to distributions
Nitrokey offers various products, which have coreboot pre-installed.
Change-Id: I3ef25e0e1cb97eda5fd457bdb650f3ee3f00210a
Signed-off-by: Markus Meissner <coder(a)safemailbox.de>
---
M Documentation/distributions.md
1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/78299/5
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