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Change subject: mb/google/guybrush: Set PS2K_IRQ to level/low
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
Matt DeVillier tested this and the EC change against Windows as well.
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Change subject: mb/google/guybrush: Set PS2K_IRQ to level/low
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/78137/comment/327dfaa9_ae990c85 :
PS3, Line 12: From https://review.coreboot.org/c/coreboot/+/54924:
> git operates with the hashes (74bce48f1d445053b217913df79a77dfe286e893), so I’d use that.
Done
https://review.coreboot.org/c/coreboot/+/78137/comment/90631dcc_bd8cb7f2 :
PS3, Line 13: > The default state for the IRQ lines when the eSPI controller comes
: > out of reset is high. This is because the IRQ lines are shared with
: > the other IRQ sources using AND gates. This means that in order to
: > not cause any spurious interrupts or miss any interrupts, the
: > IO-APIC must use a low polarity trigger.
> Remove the trailing two spaces?
Did you mean the leading spaces? I removed them.
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/guybrush: Set PS2K_IRQ to level/low
......................................................................
mb/google/guybrush: Set PS2K_IRQ to level/low
On guybrush, keyboard presses are signaled by the EC via eSPI virtual
wire. The interrupt is shared with others and should be active low.
From 74bce48f1d4 ("mb/google/{zork,guybrush,skyrim},soc/amd/espi: Fix vw_irq_polarity"):
> The default state for the IRQ lines when the eSPI controller comes
> out of reset is high. This is because the IRQ lines are shared with
> the other IRQ sources using AND gates. This means that in order to
> not cause any spurious interrupts or miss any interrupts, the
> IO-APIC must use a low polarity trigger.
Setting `vw_irq_polarity` in the device tree provides an option to
invert interrupts from the eSPI controller, but the register is
initialized from verstage which is baked into RO.
As a workaround, the necessary interrupts on the EC have been
reconfigured to be active low, and we can modify the IO-APIC
accordingly.
EC related CL here: https://crrev.com/c/4891663
BUG=b:218874489
TEST=-`emerge-guybrush chromeos-ec coreboot chromeos-bootimage`
-Flash new RW fw and verify keyboard is functional
-`suspend_stress_test -c 1` and verify i8042 irq is removed as a
wake source
-`echo mem > /sys/power/state`. Press key and verify system wake
from i8042.
Cq-Depend: chromium:4891663
Change-Id: I7d093d94a666263684645ef724e945069c68c806
Signed-off-by: Mark Hasemeyer <markhas(a)google.com>
---
M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h
2 files changed, 5 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/78137/4
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Change subject: Documentation: add Nitrokey to distributions
......................................................................
Patch Set 5:
(1 comment)
File Documentation/distributions.md:
PS4:
> okok, will do
done -> restored original order
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Change subject: Documentation: add Nitrokey to distributions
......................................................................
Documentation: add Nitrokey to distributions
Nitrokey offers various products, which have coreboot pre-installed.
Change-Id: I3ef25e0e1cb97eda5fd457bdb650f3ee3f00210a
Signed-off-by: Markus Meissner <coder(a)safemailbox.de>
---
M Documentation/distributions.md
1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/78299/5
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Change subject: Documentation: add Nitrokey to distributions
......................................................................
Patch Set 4:
(1 comment)
File Documentation/distributions.md:
PS4:
> Please restore the original order. […]
okok, will do
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Change subject: drivers/intel/gma/opregion: Use CBFS cache to load VBT
......................................................................
Patch Set 33: Code-Review+2
(1 comment)
File src/drivers/intel/gma/opregion.c:
https://review.coreboot.org/c/coreboot/+/77886/comment/3a6dffda_c5f8f029 :
PS4, Line 27: cbfs_map
> According to cscope, `local_vbt()` is called before but also after FSP-S (during GMA initialization) […]
Yes, it's pretty common practice to leak when necessary (e.g. if the file needs to stay around for later like in this case). It's just a memory allocator, and things like this are exactly what it was meant for (as opposed to needing to manually create scratch buffer arrays everywhere like this file did before).
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Change subject: drivers/intel/gma/opregion: Use CBFS cache to load VBT
......................................................................
Patch Set 33:
(1 comment)
File src/drivers/intel/gma/opregion.c:
https://review.coreboot.org/c/coreboot/+/77886/comment/e1976240_10d04f38 :
PS4, Line 27: cbfs_map
> IIRC, locate_vbt() is called rather early in ramstage. Doesn't this mean […]
According to cscope, `local_vbt()` is called before but also after FSP-S (during GMA initialization). IMO, considering that CBFS cache is just a scratchpad (not a cache) and that `vbt.bin` is relatively small the only thing that really matters is that we do not call cbfs_map() multiple times. Also to my understanding, `cbfs_unmap()` can only unmap the latest mapped CBFS file. Therefor, if I add code to unmap it and some other CBFS files got loaded in between then unmap will silently fail.
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Change subject: drivers/intel/gma/opregion: Use CBFS cache to load VBT
......................................................................
drivers/intel/gma/opregion: Use CBFS cache to load VBT
Thanks to x86 CBFS cache support, we can leverage cbfs_map() function
to load the VBT binary regardless of if it is compressed or not.
Change-Id: I1e37e718a71bd85b0d7dee1efc4c0391798f16f7
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/drivers/intel/gma/Kconfig
M src/drivers/intel/gma/opregion.c
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/jasperlake/Kconfig
M src/soc/intel/meteorlake/Kconfig
M src/soc/intel/tigerlake/Kconfig
6 files changed, 25 insertions(+), 46 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/77886/33
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Change subject: soc/intel/cse: Add API to check if CSE Firmware update is required
......................................................................
Patch Set 14:
(1 comment)
Patchset:
PS14:
> Subrata, we rechecked this on a non serial image with GBB flags = 0 […]
Done
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