coreboot-gerrit October 2023

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[XS] Change in coreboot[main]: soc/intel: separate slp-s0 residency counter frequency in LPIT table
by Subrata Banik (Code Review) 05 Oct '23

05 Oct '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78177?usp=email ) Change subject: soc/intel: separate slp-s0 residency counter frequency in LPIT table ...................................................................... soc/intel: separate slp-s0 residency counter frequency in LPIT table Intel platforms use Low Power Idle Table (LPIT) to enumerate platform Low Power Idle states. There are two types of low power residencies a) CPU PKG C10 - read via MSR (Function fixed hardware interface) b) Platform Controller Hub (PCH) SLP_S0 - read via memory mapped IO Ref. https://www.uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_…, section 2.2.1: value of 0 indicates that counter runs at TSC frequency. Ref. Intel 64 and IA-32 Architectures Software Developer’s Manual (Vol 4) MSR 0x632: PC10 residency counter is at same frequency as the TSC. Whereas slp_s0 residency counter running in different frequency. BUG=b:300440936 TEST=check kernel cpuidle sysfs are created after kernel boot cat /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us cat /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us Change-Id: Ibde764551a21b9aecb1c269948f4823548294711 Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78177 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/include/acpi/acpi.h M src/soc/intel/common/block/acpi/lpit.c 2 files changed, 4 insertions(+), 3 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 141e4d3..eae84a8 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -453,7 +453,8 @@ uint16_t reserved; } __packed acpi_lpi_desc_hdr_t; -#define ACPI_LPIT_CTR_FREQ_TSC 0 +#define ACPI_LPIT_CTR_FREQ_TSC 0 +#define ACPI_LPIT_SLP_S0_FREQ 0 /* LPIT: Native C-state instruction based LPI structure */ typedef struct acpi_lpi_desc_ncst { diff --git a/src/soc/intel/common/block/acpi/lpit.c b/src/soc/intel/common/block/acpi/lpit.c index 38a402f..de1e71d 100644 --- a/src/soc/intel/common/block/acpi/lpit.c +++ b/src/soc/intel/common/block/acpi/lpit.c @@ -50,13 +50,13 @@ sys_counter->entry_trigger.space_id = ACPI_ADDRESS_SPACE_FIXED; sys_counter->entry_trigger.access_size = ACPI_ACCESS_SIZE_UNDEFINED; - /* Slp_S0 residency counter */ + /* slp_s0 residency counter */ sys_counter->residency_counter.addrl = PCH_PWRM_BASE_ADDRESS + SLP_S0_RES; sys_counter->residency_counter.bit_offset = 0; sys_counter->residency_counter.bit_width = 32; sys_counter->residency_counter.space_id = ACPI_ADDRESS_SPACE_MEMORY; sys_counter->residency_counter.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - sys_counter->counter_frequency = ACPI_LPIT_CTR_FREQ_TSC; + sys_counter->counter_frequency = ACPI_LPIT_SLP_S0_FREQ; /* Min. residency and worst-case latency (from FSP and vendor dumps) */ sys_counter->min_residency = 30000; /* break-even: 30 ms */ -- To view, visit https://review.coreboot.org/c/coreboot/+/78177?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibde764551a21b9aecb1c269948f4823548294711 Gerrit-Change-Number: 78177 Gerrit-PatchSet: 10 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/intel: Fix slp-s0 residency counter frequency LPIT table
by Sukumar Ghorai (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Lance Zhao, Subrata Banik, Tarun, Tim Wawrzynczak. Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78164?usp=email ) Change subject: soc/intel: Fix slp-s0 residency counter frequency LPIT table ...................................................................... Patch Set 11: (1 comment) File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/78164/comment/6bd197c3_8bff4e4e : PS11, Line 457: #if CONFIG_ACPI_SOC_INTEL_SLP_S0_FREQ != 0 : #define ACPI_LPIT_SLP_S0_FREQ CONFIG_ACPI_SOC_INTEL_SLP_S0_FREQ : #else : #define ACPI_LPIT_SLP_S0_FREQ 0 : #endif > It will fail for other platform like ADL, when CONFIG_ACPI_SOC_INTEL_SLP_S0_FREQ is not defined. .. -- To view, visit https://review.coreboot.org/c/coreboot/+/78164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349 Gerrit-Change-Number: 78164 Gerrit-PatchSet: 11 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 05 Oct 2023 15:19:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel: Fix slp-s0 residency counter frequency LPIT table
by Sukumar Ghorai (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Lance Zhao, Subrata Banik, Tarun, Tim Wawrzynczak. Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78164?usp=email ) Change subject: soc/intel: Fix slp-s0 residency counter frequency LPIT table ...................................................................... Patch Set 11: (2 comments) File src/soc/intel/common/block/acpi/lpit.c: https://review.coreboot.org/c/coreboot/+/78164/comment/a567aa15_4c3bd882 : PS3, Line 34: MSR value return in usec > Ref. https://uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_Idle… Sec 2.2. […] Acknowledged https://review.coreboot.org/c/coreboot/+/78164/comment/f71e4352_5e285570 : PS3, Line 34: 0; > MSR 0x632 is for all Intel Core SoCs Package C-10 entry counter and give is mico-sec and hence we mu […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/78164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349 Gerrit-Change-Number: 78164 Gerrit-PatchSet: 11 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 05 Oct 2023 15:17:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jakub Czapiga <czapiga(a)google.com> Comment-In-Reply-To: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: Documentation: Drop mention of real time chats as "official"
by Martin L Roth (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Felix Singer, Patrick Georgi. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78022?usp=email ) Change subject: Documentation: Drop mention of real time chats as "official" ...................................................................... Patch Set 1: (1 comment) File Documentation/community/forums.md: https://review.coreboot.org/c/coreboot/+/78022/comment/c8cbefe3_5645d980 : PS1, Line 13: Maybe: ``` ## Real time chat There are a number of chat rooms, though none of these are "official" in terms of offering support from the coreboot project. All support in these chat rooms are done by strictly by individuals on their own time. * [IRC](ircs://irc.libera.chat/#coreboot) * [Discord](https://discord.gg/JqT8NM5Zbg) * [OSF Slack](https://osfw.slack.com/) - Slack requires that people come from specific domains or are explicitly invited. To work around that, there's an [invite bot](https://slack.osfw.dev/) to let people in. ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/78022?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If51ab9b9abc87772ce7584bb1976a1fbbc37854b Gerrit-Change-Number: 78022 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Oct 2023 15:16:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel: Fix slp-s0 residency counter frequency LPIT table
by Sukumar Ghorai (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Lance Zhao, Subrata Banik, Tarun, Tim Wawrzynczak. Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78164?usp=email ) Change subject: soc/intel: Fix slp-s0 residency counter frequency LPIT table ...................................................................... Patch Set 11: (1 comment) File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/78164/comment/69e483de_4312412e : PS11, Line 457: #if CONFIG_ACPI_SOC_INTEL_SLP_S0_FREQ != 0 : #define ACPI_LPIT_SLP_S0_FREQ CONFIG_ACPI_SOC_INTEL_SLP_S0_FREQ : #else : #define ACPI_LPIT_SLP_S0_FREQ 0 : #endif > can we just have […] It will fail for other platform like ADL, when CONFIG_ACPI_SOC_INTEL_SLP_S0_FREQ is not defined. -- To view, visit https://review.coreboot.org/c/coreboot/+/78164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349 Gerrit-Change-Number: 78164 Gerrit-PatchSet: 11 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 05 Oct 2023 15:15:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: sb/intel/bd82x6x: Warn about slow PCIe downstream devices
by Patrick Rudolph (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Kyösti Mälkki. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78229?usp=email ) Change subject: sb/intel/bd82x6x: Warn about slow PCIe downstream devices ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: TODO: Can this be moved into generic PCI enumeration code? -- To view, visit https://review.coreboot.org/c/coreboot/+/78229?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86b498b89d672b239d9951e116dc3680030666a6 Gerrit-Change-Number: 78229 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 05 Oct 2023 15:10:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/common/vboot: Fix the PSP verstage timestamps
by Felix Held (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Fred Reitberger, Jason Glenesk, Karthik Ramasubramanian, Martin Roth, Matt DeVillier, Tim Van Patten. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78231?usp=email ) Change subject: soc/amd/common/vboot: Fix the PSP verstage timestamps ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78231?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3e52bef22f65596152f29c511bed680427660ff5 Gerrit-Change-Number: 78231 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 05 Oct 2023 15:09:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/bd82x6x: Improve SLCAP
by Patrick Rudolph (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Kyösti Mälkki. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78228?usp=email ) Change subject: sb/intel/bd82x6x: Improve SLCAP ...................................................................... Patch Set 2: (1 comment) File src/southbridge/intel/bd82x6x/pcie.c: https://review.coreboot.org/c/coreboot/+/78228/comment/bed2ac1e_4a099e8c : PS2, Line 152: reg32 |= (slot_number++ << 19); > For now, maybe pre-increment, such that the first assignment is 1, to make a distinction from all th […] The SI Slot Implemented flag is now always set for enabled or hot pluggable ports, thus the check would always evaluate to true. The spec is the other way around: It says PCI_EXP_SLTCAP must be present when SI is set, but it doesn't cover the case where SI isn't set. -- To view, visit https://review.coreboot.org/c/coreboot/+/78228?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03aeb0a1ff0041901acc20fe700d3f7995d22366 Gerrit-Change-Number: 78228 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 05 Oct 2023 14:51:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: device/pci_def.h: Add more bits
by Patrick Rudolph (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Kyösti Mälkki. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78237?usp=email ) Change subject: device/pci_def.h: Add more bits ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I did not yet confirm these new bits are all defined in the PCIe specs, did you? Those bits are all defined PCIe spec, nothing vendor specific. -- To view, visit https://review.coreboot.org/c/coreboot/+/78237?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64e40ea6bd731cd52ce006224b7c3091d5ef3aac Gerrit-Change-Number: 78237 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 05 Oct 2023 14:25:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: MAINTAINERS: Add Brya maintainer
by Felix Held (Code Review) 05 Oct '23

05 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78219?usp=email ) Change subject: MAINTAINERS: Add Brya maintainer ...................................................................... MAINTAINERS: Add Brya maintainer Add myself :p Change-Id: Ib2bd5d9e9c93cf09ce4bca6a55cb5fab137f1bbc Signed-off-by: Eric Lai <ericllai(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78219 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M MAINTAINERS 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/MAINTAINERS b/MAINTAINERS index 9cf1ed4..904bfa5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -350,6 +350,7 @@ GOOGLE BRYA MAINBOARDS M: Subrata Banik <subratabanik(a)google.com> M: Nick Vaccaro <nvaccaro(a)chromium.org> +M: Eric Lai <ericllai(a)google.com> S: Maintained F: src/mainboard/google/brya/ -- To view, visit https://review.coreboot.org/c/coreboot/+/78219?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib2bd5d9e9c93cf09ce4bca6a55cb5fab137f1bbc Gerrit-Change-Number: 78219 Gerrit-PatchSet: 2 Gerrit-Owner: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: merged

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coreboot-gerrit October 2023