coreboot-gerrit October 2023

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[S] Change in coreboot[main]: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS
by Subrata Banik (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Cliff Huang, Eran Mitrani, Eric Lai, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Ravishankar Sarawadi, Tarun, Utkarsh H Patel. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78163?usp=email ) Change subject: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS ...................................................................... Patch Set 6: (2 comments) Patchset: PS6: > This change is not part of any doc, but I will let you if could get some reference. If there is any change in register definitions between ES and QS, that has to be documented somewhere. we can't/shouldn't program/change the offsets w/o any backing from Intel EDS at minimum. > Yes this is to do with new revisions coming in with Prod SOC. How should i review this code to know if those addresses are valid and purposeful as ES soc? also, what is the reason for changing those address space ? is there any TBT IP revision change between pre-prod and prod SoC ? File src/soc/intel/meteorlake/acpi/tcss_pcierp.asl: https://review.coreboot.org/c/coreboot/+/78163/comment/17e1bff6_8a4e27d9 : PS6, Line 3: 0xC00 > 0xC00 is size increase to access higher offsets so IMO no need to wrap under config. 0xc00 in bytes is the size of the opregion that you have created. hence, my question is if the size 0xc00 is even applicable for pre-prod soc? as you can see the opregion is system memory type and these IPs are using flat/consecutive/linear address space hence, i wish to make sure that you are not entering into the MMIO space of any other IP wrongly. If you can confirm the size of this IP address space is 0xc00 irrespective of pre-prod and prod, i believe we should be okay here. -- To view, visit https://review.coreboot.org/c/coreboot/+/78163?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0497f7108ef5046c2694aece232263582514a0c5 Gerrit-Change-Number: 78163 Gerrit-PatchSet: 6 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 05 Oct 2023 19:20:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: device/pci_def.h: Add more bits
by Kyösti Mälkki (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78237?usp=email ) Change subject: device/pci_def.h: Add more bits ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78237?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64e40ea6bd731cd52ce006224b7c3091d5ef3aac Gerrit-Change-Number: 78237 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 05 Oct 2023 19:05:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS
by Ravishankar Sarawadi (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Cliff Huang, Eran Mitrani, Eric Lai, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Subrata Banik, Tarun, Utkarsh H Patel. Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78163?usp=email ) Change subject: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS ...................................................................... Patch Set 6: (2 comments) Patchset: PS6: > which doc should follow to reflect this change ? […] This change is not part of any doc, but I will let you if could get some reference. Yes this is to do with new revisions coming in with Prod SOC. File src/soc/intel/meteorlake/acpi/tcss_pcierp.asl: https://review.coreboot.org/c/coreboot/+/78163/comment/92b8d4b8_20aced3c : PS6, Line 3: 0xC00 > shouldn't you make this value also configurable based on Config selection ? i.e. […] 0xC00 is size increase to access higher offsets so IMO no need to wrap under config. -- To view, visit https://review.coreboot.org/c/coreboot/+/78163?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0497f7108ef5046c2694aece232263582514a0c5 Gerrit-Change-Number: 78163 Gerrit-PatchSet: 6 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 05 Oct 2023 19:01:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/bd82x6x: Disable unused PCIe root ports
by Kyösti Mälkki (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78226?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: sb/intel/bd82x6x: Disable unused PCIe root ports ...................................................................... Patch Set 2: (1 comment) File src/southbridge/intel/bd82x6x/pch.c: https://review.coreboot.org/c/coreboot/+/78226/comment/04c2db34_48d482c6 : PS2, Line 309: pci_or_config16(dev, cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_SLOT); (I failed to copy-paste this correctly with previous review score) If the downstream PCIe device is an integrated device, Slot Implemented should stay cleared, but we may not have the necessary information in static devicetree to take this into account. I think it would be worth adding a comment on this and also mention this in the commit message. There should be no need to assign SLOTCAP fields like power limits or PSN for integrated devices, but appears we have done it like that all the time without noticeable issues. Setting FLAGS_SLOT=1, also integrated devices will use a "physical layer detection" mechanism to report the presence. I believe such mechanism is output from the PCIe PHY receiver sensing RX pair, so using this might be fine. If we get reports that integrated PCIe endpoints start to disappear, it's at least logged here already. With FLAGS_SLOT==0, these PCH roortports always return PCI_EXP_SLTSTA_PDS=1. -- To view, visit https://review.coreboot.org/c/coreboot/+/78226?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8ccfcab2e0e4faba8322755a4f8c2108d9b007ac Gerrit-Change-Number: 78226 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 05 Oct 2023 18:24:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS
by Subrata Banik (Code Review) 05 Oct '23

05 Oct '23

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[S] Change in coreboot[main]: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS
by Subrata Banik (Code Review) 05 Oct '23

05 Oct '23

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[S] Change in coreboot[main]: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS
by Bora Guvendik (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Cliff Huang, Eran Mitrani, Eric Lai, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Ravishankar Sarawadi, Subrata Banik, Tarun, Utkarsh H Patel. Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78163?usp=email ) Change subject: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78163?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0497f7108ef5046c2694aece232263582514a0c5 Gerrit-Change-Number: 78163 Gerrit-PatchSet: 6 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 05 Oct 2023 18:12:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS
by Ravishankar Sarawadi (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Bora Guvendik, Cliff Huang, Eran Mitrani, Eric Lai, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Ravishankar Sarawadi, Subrata Banik, Tarun, Utkarsh H Patel. Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78163?usp=email ) Change subject: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/78163/comment/868bd871_3e4c0e1a : PS4, Line 9: follwing > following Done File src/soc/intel/meteorlake/acpi/tcss_pcierp.asl: https://review.coreboot.org/c/coreboot/+/78163/comment/8dc519ec_1a5496c9 : PS4, Line 30: > can you use tabs to be consistent with the rest of the code please […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78163?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0497f7108ef5046c2694aece232263582514a0c5 Gerrit-Change-Number: 78163 Gerrit-PatchSet: 5 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 05 Oct 2023 18:11:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS
by Ravishankar Sarawadi (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Cliff Huang, Eran Mitrani, Eric Lai, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Ravishankar Sarawadi, Subrata Banik, Tarun, Utkarsh H Patel. Hello Cliff Huang, Eran Mitrani, Eric Lai, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Subrata Banik, Tarun, Utkarsh H Patel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78163?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Code-Review+1 by Cliff Huang, Code-Review+1 by Eric Lai, Code-Review+1 by Jamie Ryu, Verified+1 by build bot (Jenkins) Change subject: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS ...................................................................... soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS Within TBT PCIe, following register offsets have been updated for production silicon. Update ASL with new offsets. 1. MPC - Miscellaneous Port Configuration Register 2. RPPGEN - Root Port Power Gating Enable 3. SMSCS - SMI/SCI Status Register TEST= Check TBT PCIe Tunnel creation and device enumration. Change-Id: I0497f7108ef5046c2694aece232263582514a0c5 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- M src/soc/intel/meteorlake/acpi/tcss_pcierp.asl 1 file changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/78163/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/78163?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0497f7108ef5046c2694aece232263582514a0c5 Gerrit-Change-Number: 78163 Gerrit-PatchSet: 6 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS
by Ravishankar Sarawadi (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Kapil Porwal, Ravishankar Sarawadi, Subrata Banik, Tarun, Utkarsh H Patel. Ravishankar Sarawadi has uploaded a new patch set (#5) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/78163?usp=email ) Change subject: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS ...................................................................... soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS Within TBT PCIe, following register offsets have been updated for production silicon. Update ASL with new offsets. 1. MPC - Miscellaneous Port Configuration Register 2. RPPGEN - Root Port Power Gating Enable 3. SMSCS - SMI/SCI Status Register TEST= Check TBT PCIe Tunnel creation and device enumration. Change-Id: I0497f7108ef5046c2694aece232263582514a0c5 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- M src/soc/intel/meteorlake/acpi/tcss_pcierp.asl 1 file changed, 31 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/78163/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/78163?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0497f7108ef5046c2694aece232263582514a0c5 Gerrit-Change-Number: 78163 Gerrit-PatchSet: 5 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2023