coreboot-gerrit October 2023

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[L] Change in coreboot[main]: soc/intel/common: Refactor BERT generation flow for crashlog
by Pratikkumar V Prajapati (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Kane Chen, Kapil Porwal, Subrata Banik. Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78257?usp=email ) Change subject: soc/intel/common: Refactor BERT generation flow for crashlog ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Rex build will fail with this change. Is it OK to merge 78258 change with this patch? (That will lead to common code + soc code in a single patch) -- To view, visit https://review.coreboot.org/c/coreboot/+/78257?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I43bb61485b77d786647900ca284b7f492f412aee Gerrit-Change-Number: 78257 Gerrit-PatchSet: 2 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Thu, 05 Oct 2023 21:15:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS
by Ravishankar Sarawadi (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Bora Guvendik, Cliff Huang, Eran Mitrani, Eric Lai, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Paul Menzel, Subrata Banik, Tarun, Utkarsh H Patel. Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78163?usp=email ) Change subject: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS ...................................................................... Patch Set 6: (4 comments) File src/soc/intel/meteorlake/acpi/tcss_pcierp.asl: https://review.coreboot.org/c/coreboot/+/78163/comment/a0115179_7e24ba70 : PS6, Line 3: 0xC00 > > 0xC00 is size increase to access higher offsets so IMO no need to wrap under config. […] Added based on config. https://review.coreboot.org/c/coreboot/+/78163/comment/22da1f27_ed899ed1 : PS6, Line 54: Offset(0xBA8), /* 0xBA8, MPC - Miscellaneous Port Configuration Register */ : , 30, : HPEX, 1, /* 30, Hot Plug SCI Enable */ : PMEX, 1, /* 31, Power Management SCI Enable */ : Offset(0xBB2), /* 0xBB2, RPPGEN - Root Port Power Gating Enable */ : , 2, : L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */ : L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */ > In Gerrit, the `/*` are not correctly aligned with line 53. Done https://review.coreboot.org/c/coreboot/+/78163/comment/de118766_2803f934 : PS6, Line 70: Offset(0xBAC), /* 0xBAC, SMSCS - SMI/SCI Status Register */ > Please align `/*`. Done https://review.coreboot.org/c/coreboot/+/78163/comment/7e4c5aaa_c365bf25 : PS6, Line 67: #if CONFIG(SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON) : Offset(0xDC), /* 0xDC, SMSCS - SMI/SCI Status Register */ : #else : Offset(0xBAC), /* 0xBAC, SMSCS - SMI/SCI Status Register */ : #endif > Maybe define a macro for SMSCS? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78163?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0497f7108ef5046c2694aece232263582514a0c5 Gerrit-Change-Number: 78163 Gerrit-PatchSet: 6 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 05 Oct 2023 21:02:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS
by Ravishankar Sarawadi (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Bora Guvendik, Cliff Huang, Eran Mitrani, Eric Lai, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Ravishankar Sarawadi, Tarun, Utkarsh H Patel. Hello Bora Guvendik, Cliff Huang, Eran Mitrani, Eric Lai, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Subrata Banik, Tarun, Utkarsh H Patel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78163?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Code-Review+2 by Bora Guvendik, Verified+1 by build bot (Jenkins) Change subject: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS ...................................................................... soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS Within TBT PCIe, following register offsets have been updated for production silicon. Update ASL with new offsets. 1. MPC - Miscellaneous Port Configuration Register 2. RPPGEN - Root Port Power Gating Enable 3. SMSCS - SMI/SCI Status Register TEST= Check TBT PCIe Tunnel creation and device enumration. Change-Id: I0497f7108ef5046c2694aece232263582514a0c5 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- M src/soc/intel/meteorlake/acpi/tcss_pcierp.asl 1 file changed, 41 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/78163/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/78163?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0497f7108ef5046c2694aece232263582514a0c5 Gerrit-Change-Number: 78163 Gerrit-PatchSet: 7 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: commonlib/bsd: Get rid of CBMEM IDs for crashlog
by Pratikkumar V Prajapati (Code Review) 05 Oct '23

05 Oct '23

Hello Pratikkumar Prajapati, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78259?usp=email to look at the new patch set (#2). Change subject: commonlib/bsd: Get rid of CBMEM IDs for crashlog ...................................................................... commonlib/bsd: Get rid of CBMEM IDs for crashlog These IDs are not used as crashlog data is not stored in CBMEM now. BUG=b:298234592 TEST= TBD. Change-Id: Ie38571dece89a995d582099d34f0a1dd57cb936f Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/78259/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78259?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie38571dece89a995d582099d34f0a1dd57cb936f Gerrit-Change-Number: 78259 Gerrit-PatchSet: 2 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/intel/meteorlake: Refactor crashlog
by Pratikkumar V Prajapati (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Eran Mitrani, Kapil Porwal, Subrata Banik, Tarun. Hello Eran Mitrani, Kapil Porwal, Pratikkumar Prajapati, Subrata Banik, Tarun, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78258?usp=email to look at the new patch set (#2). Change subject: soc/intel/meteorlake: Refactor crashlog ...................................................................... soc/intel/meteorlake: Refactor crashlog Implement linked-list based method for collecting crashlog BUG=b:298234592 TEST= TBD. Change-Id: I89d36d137634d8f9b4401a17589fc318a2a29c3a Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/meteorlake/crashlog.c 1 file changed, 44 insertions(+), 116 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/78258/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78258?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I89d36d137634d8f9b4401a17589fc318a2a29c3a Gerrit-Change-Number: 78258 Gerrit-PatchSet: 2 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-CC: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: soc/intel/common: Refactor BERT generation flow for crashlog
by Pratikkumar V Prajapati (Code Review) 05 Oct '23

05 Oct '23

Hello Pratikkumar Prajapati, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78257?usp=email to look at the new patch set (#2). Change subject: soc/intel/common: Refactor BERT generation flow for crashlog ...................................................................... soc/intel/common: Refactor BERT generation flow for crashlog With earlier flow, a chunk of CBMEM region was allocated for each SRAM e.g., PUNIT SRAM, SOC PMC SRAM and IOE PMC SRAM. Then entire SRAM content was copied to dedicated CBMEM region. Later in acpi_bert.c, the BERT table was getting created for each chunk of CBMEM. This flow was not considering creating separate entries for each region of crashlog records. It resulted in only the first entry getting decoded from each SRAM. New flow aims to fix this issue. With new flow, a simple singly linked list is created to store each region of crashlog records from all SRAMs. The crashlog data is not copied to CBMEM. The nodes are allocated dynamically and then copied to ACPI BERT table and then freed. This flow also makes the overall crashlog code much simpler. BUG=b:298234592 TEST= TBD. Change-Id: I43bb61485b77d786647900ca284b7f492f412aee Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/common/block/acpi/acpi_bert.c M src/soc/intel/common/block/crashlog/crashlog.c M src/soc/intel/common/block/include/intelblocks/crashlog.h 3 files changed, 148 insertions(+), 190 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/78257/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78257?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I43bb61485b77d786647900ca284b7f492f412aee Gerrit-Change-Number: 78257 Gerrit-PatchSet: 2 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: commonlib/bsd: Get rid of CBMEM IDs for crashlog
by Pratikkumar V Prajapati (Code Review) 05 Oct '23

05 Oct '23

1 0

[M] Change in coreboot[main]: soc/intel/meteorlake: Refactor crashlog
by Pratikkumar V Prajapati (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Eran Mitrani, Kapil Porwal, Pratikkumar Prajapati, Subrata Banik, Tarun. Hello Pratikkumar Prajapati, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/78258?usp=email to review the following change. Change subject: soc/intel/meteorlake: Refactor crashlog ...................................................................... soc/intel/meteorlake: Refactor crashlog Implement linked-list based method for collecting crashlog BUG=b:298234592 TEST= TBD. Change-Id: I89d36d137634d8f9b4401a17589fc318a2a29c3a Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> --- M src/soc/intel/meteorlake/crashlog.c 1 file changed, 44 insertions(+), 116 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/78258/1 diff --git a/src/soc/intel/meteorlake/crashlog.c b/src/soc/intel/meteorlake/crashlog.c index 19a839a..97dfc00 100644 --- a/src/soc/intel/meteorlake/crashlog.c +++ b/src/soc/intel/meteorlake/crashlog.c @@ -23,10 +23,7 @@ static bool m_pmc_crashLog_present; static bool m_cpu_crashLog_support; static bool m_cpu_crashLog_present; -static bool m_ioe_crashLog_support; -static bool m_ioe_crashLog_present; static u32 m_pmc_crashLog_size; -static u32 m_ioe_crashLog_size; static u32 m_cpu_crashLog_size; static u32 cpu_crash_version; static pmc_ipc_discovery_buf_t discovery_buf; @@ -74,24 +71,23 @@ pci_or_config16(sram_dev, PCI_COMMAND, PCI_COMMAND_MEMORY); } -void cl_get_pmc_sram_data(void) +void cl_get_pmc_sram_data(cl_node_t *head) { - u32 *soc_pmc_dest = NULL, *ioe_pmc_dest = NULL; u32 pmc_sram_base = cl_get_cpu_tmp_bar(); u32 ioe_sram_base = get_sram_bar(PCI_DEVFN_IOE_SRAM); u32 pmc_crashLog_size = cl_get_pmc_record_size(); - u32 ioe_crashLog_size = 0; - - if (!pmc_sram_base) { - printk(BIOS_ERR, "PMC SRAM base not valid\n"); - return; - } + cl_node_t *cl_cur = head; if (!pmc_crashLog_size) { printk(BIOS_ERR, "No PMC crashlog records\n"); return; } + if (!pmc_sram_base) { + printk(BIOS_ERR, "PMC SRAM base not valid\n"); + return; + } + if (!ioe_sram_base) { printk(BIOS_ERR, "IOE SRAM base not valid\n"); return; @@ -107,23 +103,16 @@ printk(BIOS_DEBUG, "PMC crashLog size : 0x%x\n", pmc_crashLog_size); - /* allocate memory for the PMC crash records to be copied */ - unsigned long pmc_cl_cbmem_addr; + /* goto tail node */ + while (cl_cur && cl_cur->next) { + cl_cur = cl_cur->next; + } - pmc_cl_cbmem_addr = (unsigned long)cbmem_add(CBMEM_ID_PMC_CRASHLOG, - pmc_crashLog_size); - if (!pmc_cl_cbmem_addr) { - printk(BIOS_ERR, "Unable to allocate CBMEM PMC crashLog entry.\n"); - return; - } - - memset((void *)pmc_cl_cbmem_addr, 0, pmc_crashLog_size); - soc_pmc_dest = (u32 *)(uintptr_t)pmc_cl_cbmem_addr; - - bool pmc_sram = true; - - /* process crashlog records for SOC PMC SRAM */ + /* process crashlog records */ for (int i = 0; i < descriptor_table.numb_regions + 1; i++) { + + u32 sram_base = 0; + bool pmc_sram = true; printk(BIOS_DEBUG, "Region[0x%x].Tag=0x%x offset=0x%x, size=0x%x\n", i, descriptor_table.regions[i].bits.assign_tag, @@ -132,6 +121,7 @@ if (!descriptor_table.regions[i].bits.size) continue; + /* * Region with metadata TAG contains information about BDF entry for SOC PMC SRAM * and IOE SRAM. We don't need to parse this as we already define BDFs in @@ -144,91 +134,46 @@ sizeof(u32); printk(BIOS_DEBUG, "Found metadata tag. PMC crashlog size adjusted to: 0x%x\n", pmc_crashLog_size); - } else if (descriptor_table.regions[i].bits.assign_tag == - CRASHLOG_DESCRIPTOR_TABLE_TAG_SOC) { + continue; + } else { + if (descriptor_table.regions[i].bits.assign_tag == + CRASHLOG_DESCRIPTOR_TABLE_TAG_SOC) + sram_base = pmc_sram_base; + else if (descriptor_table.regions[i].bits.assign_tag == + CRASHLOG_DESCRIPTOR_TABLE_TAG_IOE) + sram_base = ioe_sram_base; + else + continue; - if (cl_copy_data_from_sram(pmc_sram_base, + cl_node_t *cl_node = malloc_cl_node(descriptor_table.regions[i].bits.size); + + if (!cl_node) { + printk(BIOS_DEBUG, "failed to allocate cl_node [region = %d]\n", i); + goto pmc_send_re_arm_after_reset; + } + + if (cl_copy_data_from_sram(sram_base, descriptor_table.regions[i].bits.offset, descriptor_table.regions[i].bits.size, - soc_pmc_dest, + cl_node->data, i, pmc_sram)) { - soc_pmc_dest = (u32 *)((u32)soc_pmc_dest + - (descriptor_table.regions[i].bits.size - * sizeof(u32))); + cl_cur->next = cl_node; + cl_cur = cl_cur->next; } else { + /* coping data from sram failed */ pmc_crashLog_size -= descriptor_table.regions[i].bits.size * - sizeof(u32); + sizeof(u32); printk(BIOS_DEBUG, "PMC crashlog size adjusted to: 0x%x\n", pmc_crashLog_size); + /* free cl_node */ + free_cl_node(cl_node); } - } else if (descriptor_table.regions[i].bits.assign_tag == - CRASHLOG_DESCRIPTOR_TABLE_TAG_IOE) { - /* - * SOC PMC crashlog records contains information about IOE SRAM - * records as well. Calculate IOE records size while parsing SOC - * PME SRAM. - */ - ioe_crashLog_size += descriptor_table.regions[i].bits.size * sizeof(u32); } } - pmc_crashLog_size -= ioe_crashLog_size; update_new_pmc_crashlog_size(&pmc_crashLog_size); - if (ioe_crashLog_size) - m_ioe_crashLog_present = true; - else - goto pmc_send_re_arm_after_reset; - - /* allocate memory for the IOE crashlog records to be copied */ - unsigned long ioe_cl_cbmem_addr; - - ioe_cl_cbmem_addr = (unsigned long)cbmem_add(CBMEM_ID_IOE_CRASHLOG, - ioe_crashLog_size); - if (!ioe_cl_cbmem_addr) { - printk(BIOS_ERR, "Unable to allocate CBMEM IOE crashLog entry.\n"); - return; - } - - memset((void *)ioe_cl_cbmem_addr, 0, ioe_crashLog_size); - ioe_pmc_dest = (u32 *)(uintptr_t)ioe_cl_cbmem_addr; - - /* process crashlog records for IOE SRAM */ - for (int i = 0; i < descriptor_table.numb_regions + 1; i++) { - printk(BIOS_DEBUG, "Region[0x%x].Tag=0x%x offset=0x%x, size=0x%x\n", - i, - descriptor_table.regions[i].bits.assign_tag, - descriptor_table.regions[i].bits.offset, - descriptor_table.regions[i].bits.size); - - if (!descriptor_table.regions[i].bits.size) - continue; - - if (descriptor_table.regions[i].bits.assign_tag == - CRASHLOG_DESCRIPTOR_TABLE_TAG_IOE) { - - if (cl_copy_data_from_sram(ioe_sram_base, - descriptor_table.regions[i].bits.offset, - descriptor_table.regions[i].bits.size, - ioe_pmc_dest, - i, - pmc_sram)) { - ioe_pmc_dest = (u32 *)((u32)ioe_pmc_dest + - (descriptor_table.regions[i].bits.size - * sizeof(u32))); - } else { - - ioe_crashLog_size -= descriptor_table.regions[i].bits.size * - sizeof(u32); - printk(BIOS_DEBUG, "IOE crashlog size adjusted to: 0x%x\n", - ioe_crashLog_size); - } - } - } - - update_new_ioe_crashlog_size(&ioe_crashLog_size); - pmc_send_re_arm_after_reset: /* when bit 7 of discov cmd resp is set -> bit 2 of size field */ cl_pmc_re_arm_after_reset(); @@ -264,9 +209,7 @@ (discovery_buf.conv_bits64.crash_dis_sts == 1)) { printk(BIOS_INFO, "PCH crashlog feature not supported.\n"); m_pmc_crashLog_support = false; - m_ioe_crashLog_support = false; m_pmc_crashLog_size = 0; - m_ioe_crashLog_size = 0; printk(BIOS_DEBUG, "discovery_buf supported: %d, mechanism: %d, CrashDisSts: %d\n", discovery_buf.conv_bits64.supported, discovery_buf.conv_bits64.discov_mechanism, @@ -464,9 +407,9 @@ int cl_get_total_data_size(void) { - printk(BIOS_DEBUG, "crashlog size:pmc-0x%x, ioe-pmc-0x%x cpu-0x%x\n", - m_pmc_crashLog_size, m_ioe_crashLog_size, m_cpu_crashLog_size); - return m_pmc_crashLog_size + m_cpu_crashLog_size + m_ioe_crashLog_size; + printk(BIOS_DEBUG, "crashlog size:pmc-0x%x, cpu-0x%x\n", + m_pmc_crashLog_size, m_cpu_crashLog_size); + return m_pmc_crashLog_size + m_cpu_crashLog_size; } static u32 get_control_status_interface(void) @@ -566,11 +509,6 @@ return m_cpu_crashLog_size; } -int cl_get_ioe_record_size(void) -{ - return m_ioe_crashLog_size; -} - bool cl_cpu_data_present(void) { return m_cpu_crashLog_present; @@ -581,11 +519,6 @@ return m_pmc_crashLog_present; } -bool cl_ioe_data_present(void) -{ - return m_ioe_crashLog_present; -} - bool cpu_crashlog_support(void) { return m_cpu_crashLog_support; @@ -601,11 +534,6 @@ m_pmc_crashLog_size = *pmc_crash_size; } -void update_new_ioe_crashlog_size(u32 *ioe_crash_size) -{ - m_ioe_crashLog_size = *ioe_crash_size; -} - cpu_crashlog_discovery_table_t cl_get_cpu_discovery_table(void) { return cpu_cl_disc_tab; -- To view, visit https://review.coreboot.org/c/coreboot/+/78258?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I89d36d137634d8f9b4401a17589fc318a2a29c3a Gerrit-Change-Number: 78258 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: soc/intel/common: Refactor BERT generation flow for crashlog
by Pratikkumar V Prajapati (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Pratikkumar Prajapati. Hello Pratikkumar Prajapati, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/78257?usp=email to review the following change. Change subject: soc/intel/common: Refactor BERT generation flow for crashlog ...................................................................... soc/intel/common: Refactor BERT generation flow for crashlog With earlier flow, a chunk of CBMEM region was allocated for each SRAM e.g., PUNIT SRAM, SOC PMC SRAM and IOE PMC SRAM. Then entire SRAM content was copied to dedicated CBMEM region. Later in acpi_bert.c, the BERT table was getting created for each chunk of CBMEM. This flow was not considering creating separate entries for each region of crashlog records. It resulted in only the first entry getting decoded from each SRAM. New flow aims to fix this issue. With new flow, a simple singly linked list is created to store each region of crashlog records from all SRAMs. The crashlog data is not copied to CBMEM. The nodes are allocated dynamically and then copied to ACPI BERT table and then freed. This flow also makes the overall crashlog code much simpler. BUG=b:298234592 TEST= TBD. Change-Id: I43bb61485b77d786647900ca284b7f492f412aee Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> --- M src/soc/intel/common/block/acpi/acpi_bert.c M src/soc/intel/common/block/crashlog/crashlog.c M src/soc/intel/common/block/include/intelblocks/crashlog.h 3 files changed, 148 insertions(+), 190 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/78257/1 diff --git a/src/soc/intel/common/block/acpi/acpi_bert.c b/src/soc/intel/common/block/acpi/acpi_bert.c index 350d5d3..310d4ef 100644 --- a/src/soc/intel/common/block/acpi/acpi_bert.c +++ b/src/soc/intel/common/block/acpi/acpi_bert.c @@ -7,14 +7,14 @@ #include <intelblocks/acpi.h> #include <intelblocks/crashlog.h> -static bool boot_error_src_present(void) +static bool boot_error_src_present(cl_node_t *head) { if (!discover_crashlog()) { printk(BIOS_SPEW, "Crashlog discovery result: crashlog not found\n"); return false; } - collect_pmc_and_cpu_crashlog_from_srams(); + collect_pmc_and_cpu_crashlog_from_srams(head); /* Discovery tables sizes can be larger than the actual valid collected data */ u32 crashlog_size = cl_get_total_data_size(); @@ -25,11 +25,11 @@ static enum cb_err record_crashlog_into_bert(void **region, size_t *length) { acpi_generic_error_status_t *status = NULL; - size_t cpu_record_size, pmc_record_size; size_t gesb_header_size; - void *cl_data = NULL; + void *cl_acpi_data = NULL; + cl_node_t cl_list_head = {.size = 0, .data = NULL, .next = NULL}; - if (!boot_error_src_present()) { + if (!boot_error_src_present(&cl_list_head)) { return CB_ERR; } @@ -47,67 +47,43 @@ } if (cl_get_total_data_size() > bert_storage_remaining()) { - printk(BIOS_ERR, "Crashlog entry would exceed " - "available region\n"); + printk(BIOS_ERR, "Crashlog entry would exceed available region\n"); return CB_ERR; } - cpu_record_size = cl_get_cpu_record_size(); - if (cpu_record_size) { - cl_data = new_cper_fw_error_crashlog(status, cpu_record_size); - if (!cl_data) { - printk(BIOS_ERR, "Crashlog CPU entry(size 0x%zx) " - "would exceed available region\n", - cpu_record_size); - return CB_ERR; - } - printk(BIOS_DEBUG, "cl_data %p, cpu_record_size 0x%zx\n", - cl_data, cpu_record_size); - cl_fill_cpu_records(cl_data); - } + bool multi_entry = false; + cl_node_t *cl_node = cl_list_head.next; + while (cl_node) { - pmc_record_size = cl_get_pmc_record_size(); - if (pmc_record_size) { - /* Allocate new FW ERR structure in case PMC crashlog is present */ - if (pmc_record_size && !bert_append_fw_err(status)) { - printk(BIOS_ERR, "Crashlog PMC entry would " - "exceed available region\n"); - return CB_ERR; + if (cl_node->size <= 0) { + cl_node = cl_node->next; + continue; } - cl_data = new_cper_fw_error_crashlog(status, pmc_record_size); - if (!cl_data) { - printk(BIOS_ERR, "Crashlog PMC entry(size 0x%zx) " - "would exceed available region\n", - pmc_record_size); - return CB_ERR; + if (!(cl_node->data)) { + cl_node = cl_node->next; + continue; } - printk(BIOS_DEBUG, "cl_data %p, pmc_record_size 0x%zx\n", - cl_data, pmc_record_size); - cl_fill_pmc_records(cl_data); - } - if (CONFIG(SOC_INTEL_IOE_DIE_SUPPORT)) { - size_t ioe_record_size = cl_get_ioe_record_size(); - if (ioe_record_size) { - /* Allocate new FW ERR structure in case IOE crashlog is present */ - if (ioe_record_size && !bert_append_fw_err(status)) { - printk(BIOS_ERR, "Crashlog IOE entry would " - "exceed available region\n"); + if (multi_entry) { + if (!bert_append_fw_err(status)) { + printk(BIOS_ERR, "Crashlog entry would exceed available region\n"); return CB_ERR; } - - cl_data = new_cper_fw_error_crashlog(status, ioe_record_size); - if (!cl_data) { - printk(BIOS_ERR, "Crashlog IOE entry(size 0x%zx) " - "would exceed available region\n", - ioe_record_size); - return CB_ERR; - } - printk(BIOS_DEBUG, "cl_data %p, ioe_record_size 0x%zx\n", - cl_data, ioe_record_size); - cl_fill_ioe_records(cl_data); } + + cl_acpi_data = new_cper_fw_error_crashlog(status, cl_node->size); + if (!cl_acpi_data) { + printk(BIOS_ERR, "Crashlog entry(size 0x%x) would exceed available region\n", + cl_node->size); + return CB_ERR; + } + memcpy(cl_acpi_data, (void *) cl_node->data, cl_node->size); + + cl_node_t *temp = cl_node; + cl_node = cl_node->next; + free_cl_node(temp); + multi_entry = true; } *length = status->data_length + gesb_header_size; diff --git a/src/soc/intel/common/block/crashlog/crashlog.c b/src/soc/intel/common/block/crashlog/crashlog.c index e3d85cd..6735d97 100644 --- a/src/soc/intel/common/block/crashlog/crashlog.c +++ b/src/soc/intel/common/block/crashlog/crashlog.c @@ -330,11 +330,36 @@ return true; } -void __weak cl_get_pmc_sram_data(void) +cl_node_t *malloc_cl_node(size_t len) { - u32 *dest = NULL; + cl_node_t *node = malloc(sizeof(cl_node_t)); + if (!node) + return NULL; + + node->data = malloc(len * sizeof(u32)); + if (!(node->data)) + return NULL; + + node->size = len * sizeof(u32); + node->next = NULL; + + return node; +} + +void free_cl_node(cl_node_t *node) +{ + if (!node) + return; + if (node->data) + free(node->data); + free(node); +} + +void __weak cl_get_pmc_sram_data(cl_node_t *head) +{ u32 tmp_bar_addr = cl_get_cpu_tmp_bar(); u32 pmc_crashLog_size = cl_get_pmc_record_size(); + cl_node_t *cl_cur = head; if (!cl_pmc_sram_has_mmio_access() || !tmp_bar_addr) return; @@ -353,7 +378,7 @@ goto pmc_send_re_arm_after_reset; } printk(BIOS_DEBUG, "PMC crashLog size in discovery mode : 0x%X\n", - pmc_crashLog_size); + pmc_crashLog_size); } else { if (discovery_buf.bits.dis) { printk(BIOS_DEBUG, "PCH crashlog is disabled in legacy mode.\n"); @@ -362,51 +387,65 @@ pmc_crashLog_size = (discovery_buf.bits.size != 0) ? discovery_buf.bits.size : 0xC00; printk(BIOS_DEBUG, "PMC crashLog size in legacy mode : 0x%X\n", - pmc_crashLog_size); + pmc_crashLog_size); } - /* allocate mem for the record to be copied */ - unsigned long pmc_cl_cbmem_addr; - - pmc_cl_cbmem_addr = (unsigned long)cbmem_add(CBMEM_ID_PMC_CRASHLOG, - pmc_crashLog_size); - if (!pmc_cl_cbmem_addr) { - printk(BIOS_ERR, "Unable to allocate CBMEM PMC crashLog entry.\n"); - return; - } - - memset((void *)pmc_cl_cbmem_addr, 0, pmc_crashLog_size); - dest = (u32 *)(uintptr_t)pmc_cl_cbmem_addr; bool pmc_sram = true; - pmc_crashlog_desc_table_t descriptor_table = cl_get_pmc_descriptor_table(); + pmc_crashlog_desc_table_t descriptor_table = cl_get_pmc_descriptor_table(); + + /* goto tail node */ + while (cl_cur && cl_cur->next) { + cl_cur = cl_cur->next; + } + if (discovery_buf.bits.discov_mechanism == 1) { for (int i = 0; i < descriptor_table.numb_regions; i++) { + + cl_node_t *cl_node = malloc_cl_node(descriptor_table.regions[i].bits.size); + if (!cl_node) { + printk(BIOS_DEBUG, "failed to allocate cl_node [region = %d]\n", i); + goto pmc_send_re_arm_after_reset; + } + if (cl_copy_data_from_sram(tmp_bar_addr, - descriptor_table.regions[i].bits.offset, - descriptor_table.regions[i].bits.size, - dest, - i, - pmc_sram)) { - dest = (u32 *)((u32)dest + - (descriptor_table.regions[i].bits.size - * sizeof(u32))); + descriptor_table.regions[i].bits.offset, + descriptor_table.regions[i].bits.size, + cl_node->data, + i, + pmc_sram)) { + cl_cur->next = cl_node; + cl_cur = cl_cur->next; } else { pmc_crashLog_size -= descriptor_table.regions[i].bits.size * sizeof(u32); printk(BIOS_DEBUG, "discover mode PMC crashlog size adjusted" - " to: 0x%x\n", pmc_crashLog_size); + " to: 0x%x\n", pmc_crashLog_size); + /* free cl_node */ + free_cl_node(cl_node); } } } else { - if (!cl_copy_data_from_sram(tmp_bar_addr, - discovery_buf.bits.base_offset, - discovery_buf.bits.size, - dest, - 0, - pmc_sram)) { + + cl_node_t *cl_node = malloc_cl_node(discovery_buf.bits.size); + if (!cl_node) { + printk(BIOS_DEBUG, "failed to allocate cl_node\n"); + goto pmc_send_re_arm_after_reset; + } + + if (cl_copy_data_from_sram(tmp_bar_addr, + discovery_buf.bits.base_offset, + discovery_buf.bits.size, + cl_node->data, + 0, + pmc_sram)) { + cl_cur->next = cl_node; + cl_cur = cl_cur->next; + } else { pmc_crashLog_size -= discovery_buf.bits.size * sizeof(u32); printk(BIOS_DEBUG, "legacy mode PMC crashlog size adjusted to: 0x%x\n", - pmc_crashLog_size); + pmc_crashLog_size); + /* free cl_node */ + free_cl_node(cl_node); } } @@ -422,10 +461,9 @@ } -void cl_get_cpu_sram_data(void) +void cl_get_cpu_sram_data(cl_node_t *head) { - u32 tmp_bar_addr = 0; - u32 *dest = NULL; + cl_node_t *cl_cur = head; u32 m_cpu_crashLog_size = cl_get_cpu_record_size(); cpu_crashlog_discovery_table_t cpu_cl_disc_tab = cl_get_cpu_discovery_table(); @@ -435,35 +473,41 @@ } printk(BIOS_DEBUG, "CPU crash data size: 0x%X bytes in 0x%X region(s).\n", - m_cpu_crashLog_size, cpu_cl_disc_tab.header.fields.count); + m_cpu_crashLog_size, cpu_cl_disc_tab.header.fields.count); - /* allocate memory buffers for CPU crashog data to be copied */ - unsigned long cpu_crashlog_cbmem_addr; - cpu_crashlog_cbmem_addr = (unsigned long)cbmem_add(CBMEM_ID_CPU_CRASHLOG, - m_cpu_crashLog_size); - if (!cpu_crashlog_cbmem_addr) { - printk(BIOS_ERR, "Failed to add CPU main crashLog entries to CBMEM.\n"); - return; + /* goto tail node */ + while (cl_cur && cl_cur->next) { + cl_cur = cl_cur->next; } - memset((void *)cpu_crashlog_cbmem_addr, 0, m_cpu_crashLog_size); - tmp_bar_addr = cl_get_cpu_bar_addr(); - dest = (u32 *)(uintptr_t)cpu_crashlog_cbmem_addr; - bool pmc_sram = false; - for (int i = 0 ; i < cpu_cl_disc_tab.header.fields.count ; i++) { - if (cl_copy_data_from_sram(tmp_bar_addr, - cpu_cl_disc_tab.buffers[i].fields.offset, - cpu_cl_disc_tab.buffers[i].fields.size, - dest, - i, - pmc_sram)) { - dest = (u32 *)((u32)dest + - (cpu_cl_disc_tab.buffers[i].fields.size * sizeof(u32))); + + u32 cpu_bar_addr = cl_get_cpu_bar_addr(); + bool pmc_sram = false; + + if (!cpu_cl_disc_tab.buffers[i].fields.size) { + continue; + } + + cl_node_t *cl_node = malloc_cl_node(cpu_cl_disc_tab.buffers[i].fields.size); + if (!cl_node) { + printk(BIOS_DEBUG, "failed to allocate cl_node [buffer = %d]\n", i); + return; + } + + if (cl_copy_data_from_sram(cpu_bar_addr, + cpu_cl_disc_tab.buffers[i].fields.offset, + cpu_cl_disc_tab.buffers[i].fields.size, + cl_node->data, + i, + pmc_sram)) { + cl_cur->next = cl_node; + cl_cur = cl_cur->next; + } else { m_cpu_crashLog_size -= cpu_cl_disc_tab.buffers[i].fields.size - * sizeof(u32); - + * sizeof(u32); + free_cl_node(cl_node); /* for CPU skip all buffers if the 1st one is not valid */ if (i == 0) { m_cpu_crashLog_size = 0; @@ -482,7 +526,7 @@ cpu_cl_rearm(); } -void collect_pmc_and_cpu_crashlog_from_srams(void) +void collect_pmc_and_cpu_crashlog_from_srams(cl_node_t *head) { if (pmc_crashlog_support() && cl_pmc_data_present() && (cl_get_pmc_record_size() > 0)) { @@ -490,7 +534,7 @@ cl_pmc_en_gen_on_all_reboot(); printk(BIOS_DEBUG, "Crashlog collection enabled on every reboot.\n"); } - cl_get_pmc_sram_data(); + cl_get_pmc_sram_data(head); } else { printk(BIOS_DEBUG, "Skipping PMC crashLog collection. Data not present.\n"); } @@ -500,74 +544,8 @@ if (cpu_crashlog_support() && cl_cpu_data_present() && (cl_get_cpu_record_size() > 0)) { printk(BIOS_DEBUG, "CPU crashLog present.\n"); - cl_get_cpu_sram_data(); + cl_get_cpu_sram_data(head); } else { printk(BIOS_DEBUG, "Skipping CPU crashLog collection. Data not present.\n"); } } - -bool cl_fill_cpu_records(void *cl_record) -{ - void *cl_src_addr = NULL; - - u32 m_cpu_crashLog_size = cl_get_cpu_record_size(); - - if (!cl_cpu_data_present() || m_cpu_crashLog_size == 0) { - printk(BIOS_DEBUG, "CPU crashLog not present, skipping.\n"); - return false; - } - - printk(BIOS_DEBUG, "CPU crash data collection.\n"); - cl_src_addr = cbmem_find(CBMEM_ID_CPU_CRASHLOG); - if (!cl_src_addr) { - printk(BIOS_DEBUG, "CPU crash data, CBMEM not found\n"); - return false; - } - memcpy(cl_record, cl_src_addr, m_cpu_crashLog_size); - - return true; -} - -bool cl_fill_pmc_records(void *cl_record) -{ - void *cl_src_addr = NULL; - - u32 m_pmc_crashLog_size = cl_get_pmc_record_size(); - - if (!cl_pmc_data_present() || m_pmc_crashLog_size == 0) { - printk(BIOS_DEBUG, "PMC crashLog not present, skipping.\n"); - return false; - } - - printk(BIOS_DEBUG, "PMC crash data collection.\n"); - cl_src_addr = cbmem_find(CBMEM_ID_PMC_CRASHLOG); - if (!cl_src_addr) { - printk(BIOS_DEBUG, "PMC crash data, CBMEM not found\n"); - return false; - } - memcpy(cl_record, cl_src_addr, m_pmc_crashLog_size); - - return true; -} - -bool cl_fill_ioe_records(void *cl_record) -{ - void *cl_src_addr = NULL; - - u32 m_ioe_crashLog_size = cl_get_ioe_record_size(); - - if (!cl_ioe_data_present() || m_ioe_crashLog_size == 0) { - printk(BIOS_DEBUG, "IOE crashLog not present, skipping.\n"); - return false; - } - - printk(BIOS_DEBUG, "IOE PMC crash data collection.\n"); - cl_src_addr = cbmem_find(CBMEM_ID_IOE_CRASHLOG); - if (!cl_src_addr) { - printk(BIOS_DEBUG, "IOE crash data, CBMEM not found\n"); - return false; - } - memcpy(cl_record, cl_src_addr, m_ioe_crashLog_size); - - return true; -} diff --git a/src/soc/intel/common/block/include/intelblocks/crashlog.h b/src/soc/intel/common/block/include/intelblocks/crashlog.h index 38d1a09..8948977 100644 --- a/src/soc/intel/common/block/include/intelblocks/crashlog.h +++ b/src/soc/intel/common/block/include/intelblocks/crashlog.h @@ -170,6 +170,14 @@ cpu_crashlog_buffer_info_t buffers[256]; } __packed cpu_crashlog_discovery_table_t; +typedef struct cl_node_t { + u32 size; + void *data; + struct cl_node_t* next; +} cl_node_t; + +cl_node_t *malloc_cl_node(size_t len); +void free_cl_node(cl_node_t *node); int cl_get_cpu_record_size(void); int cl_get_pmc_record_size(void); int cl_get_ioe_record_size(void); @@ -184,8 +192,8 @@ bool cl_cpu_data_present(void); bool cl_pmc_data_present(void); bool cl_ioe_data_present(void); -void cl_get_cpu_sram_data(void); -void cl_get_pmc_sram_data(void); +void cl_get_cpu_sram_data(cl_node_t *head); +void cl_get_pmc_sram_data(cl_node_t *head); void reset_discovery_buffers(void); void update_new_pmc_crashlog_size(u32 *pmc_crash_size); void update_new_cpu_crashlog_size(u32 *cpu_crash_size); @@ -213,11 +221,7 @@ u32 *dest_addr, u32 buffer_index, bool pmc_sram); -void collect_pmc_and_cpu_crashlog_from_srams(void); -bool cl_fill_cpu_records(void *cl_record); -bool cl_fill_pmc_records(void *cl_record); -bool cl_fill_ioe_records(void *cl_record); - +void collect_pmc_and_cpu_crashlog_from_srams(cl_node_t *head); static const EFI_GUID FW_ERR_SECTION_GUID = { 0x81212a96, 0x09ed, 0x4996, { 0x94, 0x71, 0x8d, 0x72, 0x9c, 0x8e, 0x69, 0xed } -- To view, visit https://review.coreboot.org/c/coreboot/+/78257?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I43bb61485b77d786647900ca284b7f492f412aee Gerrit-Change-Number: 78257 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Attention: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: MAINTAINERS: Add Brya maintainer
by Paul Menzel (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Eric Lai. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78219?usp=email ) Change subject: MAINTAINERS: Add Brya maintainer ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/78219/comment/ba9402b6_2af3a059 : PS2, Line 7: Add Brya maintainer Next time please use: Add Eric Lai as Brya maintainer Patchset: PS2: Congratulations on your new position! -- To view, visit https://review.coreboot.org/c/coreboot/+/78219?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib2bd5d9e9c93cf09ce4bca6a55cb5fab137f1bbc Gerrit-Change-Number: 78219 Gerrit-PatchSet: 2 Gerrit-Owner: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Comment-Date: Thu, 05 Oct 2023 19:49:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2023