coreboot-gerrit October 2023

coreboot-gerrit@coreboot.org

1 participants
3354 discussions

[XS] Change in coreboot[main]: sb/intel/bd82x6x/pcie: Drop register write
by Kyösti Mälkki (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78238?usp=email ) Change subject: sb/intel/bd82x6x/pcie: Drop register write ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78238?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7293e6eaa2d0bac5efe8316029bdecb04a5586e9 Gerrit-Change-Number: 78238 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 05 Oct 2023 12:54:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: spi: Add struct spi_flash_bpbits, a common rep. for block protection
by Daniel Gröber (dxld) (Code Review) 05 Oct '23

05 Oct '23

Hello Daniel Gröber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42112 to review the following change. Change subject: spi: Add struct spi_flash_bpbits, a common rep. for block protection ...................................................................... spi: Add struct spi_flash_bpbits, a common rep. for block protection Change-Id: I02828b1f764aea29374e794001e74cdc86a94c92 Signed-off-by: Daniel Gröber <dxld(a)darkboxed.org> --- M src/include/spi_flash.h 1 file changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/42112/1 diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 35b02db..7dce216 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -49,6 +49,39 @@ int (*status)(const struct spi_flash *flash, u8 *reg); }; +struct spi_flash_bpbits { + unsigned int bp; /*< block protection select bits */ + bool cmp; /*< complement protect */ + bool tb; /*< top=0 / bottom=1 select */ + union { + struct { + union { bool srp1, srl; }; + union { bool srp0, srp; }; + /* + * For W25Q*{,F}* parts: + * srp1 srp0 + * 0 0 | writable if WEL==1 + * 0 1 | writable if WEL==1 && #WP==Vcc + * 1 0 | not writable until next power-down + * 1 1 | not writable, permanently + * + * checked datasheets: W25Q128FV, (W25Q80, W25Q16, + * W25Q32) + * + * For W25Q*{J,D}* parts: + * + * srl srp + * 0 0 | writable if WEL==1 + * 0 1 | writable if WEL==1 && #WP==Vcc + * 1 x | not writable until next power-down + * + * checked datasheets: W25Q132JW, W25Q128JW, W25Q256JV. + * W25Q16DW + */ + } winbond; + }; +}; + /* Current code assumes all callbacks are supplied in this object. */ struct spi_flash_protection_ops { /* -- To view, visit https://review.coreboot.org/c/coreboot/+/42112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02828b1f764aea29374e794001e74cdc86a94c92 Gerrit-Change-Number: 42112 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Gröber (dxld) Gerrit-Reviewer: Daniel Gröber <dxld(a)darkboxed.org> Gerrit-MessageType: newchange

4 8

[XS] Change in coreboot[main]: cpu/intel/socket_BGA956: Double DCACHE_RAM_SIZE to 64 kB
by Felix Held (Code Review) 05 Oct '23

05 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71905?usp=email ) Change subject: cpu/intel/socket_BGA956: Double DCACHE_RAM_SIZE to 64 kB ...................................................................... cpu/intel/socket_BGA956: Double DCACHE_RAM_SIZE to 64 kB This fixes building lenovo/x200 with VBOOT. All supported CPUs have enough L2 cache to support this. Change-Id: Ifd6a16ce36c86349955cd7b7ddb3f74a19c17c4d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71905 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/socket_BGA956/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Kyösti Mälkki: Looks good to me, approved build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig index b56fb88..7c42722 100644 --- a/src/cpu/intel/socket_BGA956/Kconfig +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -10,7 +10,7 @@ config DCACHE_RAM_SIZE hex - default 0x8000 + default 0x10000 config DCACHE_BSP_STACK_SIZE hex -- To view, visit https://review.coreboot.org/c/coreboot/+/71905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifd6a16ce36c86349955cd7b7ddb3f74a19c17c4d Gerrit-Change-Number: 71905 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/quandiso: Change camera fw_config feild
by Felix Held (Code Review) 05 Oct '23

05 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78213?usp=email ) Change subject: mb/google/nissa/var/quandiso: Change camera fw_config feild ...................................................................... mb/google/nissa/var/quandiso: Change camera fw_config feild Quandiso reserve bit 11 for mipi camera usage. BUG=b:300574047 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Id4343083f0d69a49c642657d165ceac349cd7422 Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78213 Reviewed-by: Shawn Ku <shawnku(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/quandiso/overridetree.cb 1 file changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Shawn Ku: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/quandiso/overridetree.cb b/src/mainboard/google/brya/variants/quandiso/overridetree.cb index 63fb2f7..e94d3da 100644 --- a/src/mainboard/google/brya/variants/quandiso/overridetree.cb +++ b/src/mainboard/google/brya/variants/quandiso/overridetree.cb @@ -19,10 +19,6 @@ option SD_PRESENT 0 option SD_ABSENT 1 end - field WFC 11 - option WFC_ABSENT 0 - option WFC_PRESENT 1 - end field WIFI_SAR_ID2 16 19 option INTEL_QUANDISO_LTE 0 option INTEL_QUANDISO_WIFI 1 @@ -34,6 +30,10 @@ option MAX98360A 0 option ALC1019 1 end + field USB_WFC 22 23 + option USB_WFC_ABSENT 0 + option USB_WFC_PRESENT 1 + end end chip soc/intel/alderlake @@ -516,7 +516,7 @@ register "desc" = ""USB2 WF Camera"" register "type" = "UPC_TYPE_INTERNAL" device ref usb2_port7 on - probe WFC WFC_PRESENT + probe USB_WFC USB_WFC_PRESENT end end chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/78213?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id4343083f0d69a49c642657d165ceac349cd7422 Gerrit-Change-Number: 78213 Gerrit-PatchSet: 3 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/quandiso: Add ALC1019 amp support
by Felix Held (Code Review) 05 Oct '23

05 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77754?usp=email ) Change subject: mb/google/nissa/var/quandiso: Add ALC1019 amp support ...................................................................... mb/google/nissa/var/quandiso: Add ALC1019 amp support BUG=b:300573763 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Iff8167695c302f7b58976516d651a81f1a429bee Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77754 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shawn Ku <shawnku(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/quandiso/overridetree.cb 1 file changed, 14 insertions(+), 1 deletion(-) Approvals: Shawn Ku: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/quandiso/overridetree.cb b/src/mainboard/google/brya/variants/quandiso/overridetree.cb index 0b672ff..63fb2f7 100644 --- a/src/mainboard/google/brya/variants/quandiso/overridetree.cb +++ b/src/mainboard/google/brya/variants/quandiso/overridetree.cb @@ -30,6 +30,10 @@ option INTEL_QUANDISO360_WIFI 3 option UNUSED 15 end + field AUDIO_AMP 20 21 + option MAX98360A 0 + option ALC1019 1 + end end chip soc/intel/alderlake @@ -346,6 +350,13 @@ register "property_list[0].integer" = "1" device i2c 1a on end end + chip drivers/generic/alc1015 + register "hid" = ""RTL1019"" + register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + device generic 0 on + probe AUDIO_AMP ALC1019 + end + end end device ref i2c5 on chip drivers/i2c/generic @@ -372,7 +383,9 @@ register "hid" = ""MX98360A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" register "sdmode_delay" = "5" - device generic 0 on end + device generic 0 on + probe AUDIO_AMP MAX98360A + end end end device ref pcie_rp4 on -- To view, visit https://review.coreboot.org/c/coreboot/+/77754?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iff8167695c302f7b58976516d651a81f1a429bee Gerrit-Change-Number: 77754 Gerrit-PatchSet: 7 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/uldren: Remove fw_config probe for TS and TP
by Felix Held (Code Review) 05 Oct '23

05 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77538?usp=email ) Change subject: mb/google/nissa/var/uldren: Remove fw_config probe for TS and TP ...................................................................... mb/google/nissa/var/uldren: Remove fw_config probe for TS and TP When service center repair touchscreen or touchpad will change compatible device not specific one, the fw_config probe mechanism is not convenient for service center. Removing touchscreen and touchpad fw_config probe for the purpose. BUG=b:297840605 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I66f12ae478f74c019c53ee5e77f7e0f9c324e758 Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77538 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Derek Huang <derekhuang(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/uldren/overridetree.cb 1 file changed, 8 insertions(+), 32 deletions(-) Approvals: Derek Huang: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/uldren/overridetree.cb b/src/mainboard/google/brya/variants/uldren/overridetree.cb index 65c8151..829f877 100644 --- a/src/mainboard/google/brya/variants/uldren/overridetree.cb +++ b/src/mainboard/google/brya/variants/uldren/overridetree.cb @@ -222,10 +222,7 @@ register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x20" - device i2c 2c on - probe TOUCHSCREEN TOUCHSCREEN_UNKNOWN - probe TOUCHSCREEN TOUCHSCREEN_WDT8752A - end + device i2c 2c on end end chip drivers/i2c/generic register "hid" = ""ELAN0001"" @@ -241,10 +238,7 @@ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "enable_delay_ms" = "1" register "has_power_resource" = "1" - device i2c 10 on - probe TOUCHSCREEN TOUCHSCREEN_UNKNOWN - probe TOUCHSCREEN TOUCHSCREEN_EKTH5012 - end + device i2c 10 on end end chip drivers/i2c/hid register "generic.hid" = ""ELAN900C"" @@ -260,10 +254,7 @@ register "generic.enable_delay_ms" = "6" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" - device i2c 16 on - probe TOUCHSCREEN TOUCHSCREEN_UNKNOWN - probe TOUCHSCREEN TOUCHSCREEN_EKTH7D18 - end + device i2c 16 on end end chip drivers/i2c/hid register "generic.hid" = ""GXTP7996"" @@ -278,10 +269,7 @@ register "generic.enable_delay_ms" = "10" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" - device i2c 5d on - probe TOUCHSCREEN TOUCHSCREEN_UNKNOWN - probe TOUCHSCREEN TOUCHSCREEN_GT7996F - end + device i2c 5d on end end chip drivers/i2c/hid register "generic.hid" = ""GTCH7502"" @@ -296,10 +284,7 @@ register "generic.enable_delay_ms" = "30" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" - device i2c 40 on - probe TOUCHSCREEN TOUCHSCREEN_UNKNOWN - probe TOUCHSCREEN TOUCHSCREEN_GTCH7502 - end + device i2c 40 on end end chip drivers/i2c/hid register "generic.hid" = ""WDHT2601"" @@ -314,10 +299,7 @@ register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x20" - device i2c 3c on - probe TOUCHSCREEN TOUCHSCREEN_UNKNOWN - probe TOUCHSCREEN TOUCHSCREEN_WDT8790A - end + device i2c 3c on end end end device ref i2c3 on @@ -345,10 +327,7 @@ register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" register "wake" = "GPE0_DW2_14" register "detect" = "1" - device i2c 15 on - probe TOUCHPAD TOUCHPAD_UNKNOWN - probe TOUCHPAD TOUCHPAD_EKT3744 - end + device i2c 15 on end end chip drivers/i2c/hid register "generic.hid" = ""GXTP7863"" @@ -357,10 +336,7 @@ register "generic.wake" = "GPE0_DW2_14" register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" - device i2c 2c on - probe TOUCHPAD TOUCHPAD_UNKNOWN - probe TOUCHPAD TOUCHPAD_GT7863 - end + device i2c 2c on end end end device ref pcie_rp7 off end -- To view, visit https://review.coreboot.org/c/coreboot/+/77538?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I66f12ae478f74c019c53ee5e77f7e0f9c324e758 Gerrit-Change-Number: 77538 Gerrit-PatchSet: 7 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[main]: device/pci_def.h: Add more bits
by Kyösti Mälkki (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78237?usp=email ) Change subject: device/pci_def.h: Add more bits ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: I did not yet confirm these new bits are all defined in the PCIe specs, did you? -- To view, visit https://review.coreboot.org/c/coreboot/+/78237?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64e40ea6bd731cd52ce006224b7c3091d5ef3aac Gerrit-Change-Number: 78237 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 05 Oct 2023 12:48:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: configs: Clean up config.google.skyrim.with_binaries defconfig
by Felix Held (Code Review) 05 Oct '23

05 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78195?usp=email ) Change subject: configs: Clean up config.google.skyrim.with_binaries defconfig ...................................................................... configs: Clean up config.google.skyrim.with_binaries defconfig Drop the Cezanne FSP binaries (which were just placeholders), as well as all other defaults removed when running 'make savedefconfig' Change-Id: I6d355b838d30dca64a9e6206eb6000763cc105a1 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78195 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M configs/config.google_skyrim.with_binaries 1 file changed, 2 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/configs/config.google_skyrim.with_binaries b/configs/config.google_skyrim.with_binaries index 7c56ceb..c0aecd3 100644 --- a/configs/config.google_skyrim.with_binaries +++ b/configs/config.google_skyrim.with_binaries @@ -1,30 +1,18 @@ CONFIG_TIMESTAMPS_ON_CONSOLE=y CONFIG_USE_AMD_BLOBS=y CONFIG_VENDOR_GOOGLE=y -CONFIG_VGA_BIOS_ID="1002,1506" CONFIG_VGA_BIOS=y CONFIG_CONSOLE_POST=y CONFIG_BOARD_GOOGLE_SKYRIM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_SPL_TABLE_FILE="3rdparty/amd_blobs/mendocino/PSP/TypeId0x55_SplTableBl_MDN.sbin" -CONFIG_VGA_BIOS_FILE="3rdparty/amd_blobs/mendocino/MdnGenericVbios.bin" -CONFIG_FSP_M_FILE="3rdparty/amd_blobs/cezanne/CEZANNE_M.fd" -CONFIG_FSP_S_FILE="3rdparty/amd_blobs/cezanne/CEZANNE_S.fd" -CONFIG_ASYNC_FILE_LOADING=y CONFIG_PSP_SOFTFUSE_BITS="34 28" -CONFIG_UART_PCI_ADDR=0x0 +CONFIG_DEBUG_SMI=y +CONFIG_ASYNC_FILE_LOADING=y CONFIG_RUN_FSP_GOP=y -CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 -CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 -CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 CONFIG_DISPLAY_HOBS=y CONFIG_DISPLAY_UPD_DATA=y -CONFIG_ADD_FSP_BINARIES=y -CONFIG_POST_IO_PORT=0x80 CONFIG_PAYLOAD_NONE=y CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y CONFIG_DISPLAY_FSP_HEADER=y CONFIG_FATAL_ASSERTS=y -CONFIG_DEBUG_SMI=y -CONFIG_WRITE_STB_BUFFER_TO_CONSOLE=y -CONFIG_ADD_POSTCODES_TO_STB=y -- To view, visit https://review.coreboot.org/c/coreboot/+/78195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6d355b838d30dca64a9e6206eb6000763cc105a1 Gerrit-Change-Number: 78195 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[main]: sb/intel/bd82x6x: Disable unused PCIe root ports
by Kyösti Mälkki (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78226?usp=email ) Change subject: sb/intel/bd82x6x: Disable unused PCIe root ports ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: . -- To view, visit https://review.coreboot.org/c/coreboot/+/78226?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8ccfcab2e0e4faba8322755a4f8c2108d9b007ac Gerrit-Change-Number: 78226 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 05 Oct 2023 12:47:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: mb/google/rex/var/karis: Correct touchscreen GPIO settings
by Tyler Wang (Code Review) 05 Oct '23

05 Oct '23

Tyler Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78208?usp=email ) Change subject: mb/google/rex/var/karis: Correct touchscreen GPIO settings ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/78208?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1190016fbfb2aeb21bdbba334c8c25986435769f Gerrit-Change-Number: 78208 Gerrit-PatchSet: 2 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 05 Oct 2023 12:23:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2023