coreboot-gerrit October 2023

coreboot-gerrit@coreboot.org

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[XL] Change in coreboot[main]: mb/google/brox: Create new Brox baseboard
by Nick Vaccaro (Code Review) 10 Oct '23

10 Oct '23

Attention is currently required from: Shelley Chen. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78009?usp=email ) Change subject: mb/google/brox: Create new Brox baseboard ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/brox/Makefile.inc: https://review.coreboot.org/c/coreboot/+/78009/comment/fc2b7336_49d89349 : PS5, Line 18: subdirs-y += variants/$(VARIANT_DIR)/memory It looks like the memory directory was deleted from this CL as opposed to reduced to empty shell files. Will that cause issue with this if the memory folder does not exist? -- To view, visit https://review.coreboot.org/c/coreboot/+/78009?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I929b465646ac4c69d4bab33ce23848c7b1fa0f98 Gerrit-Change-Number: 78009 Gerrit-PatchSet: 5 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Comment-Date: Tue, 10 Oct 2023 16:01:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/amd/genoa: Enable eSPI early
by Felix Held (Code Review) 10 Oct '23

10 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76508?usp=email ) ( 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/genoa: Enable eSPI early ...................................................................... soc/amd/genoa: Enable eSPI early Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I4965eac4ec3d600b1e840affce4e5b4fa2ea4360 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76508 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/mainboard/amd/onyx/devicetree.cb M src/soc/amd/genoa/Kconfig M src/soc/amd/genoa/early_fch.c A src/soc/amd/genoa/include/soc/acpi.h A src/soc/amd/genoa/include/soc/lpc.h A src/soc/amd/genoa/include/soc/pci_devs.h 6 files changed, 90 insertions(+), 0 deletions(-) Approvals: Martin Roth: Looks good to me, approved Felix Held: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/amd/onyx/devicetree.cb b/src/mainboard/amd/onyx/devicetree.cb index 5f447b2..2b37b76 100644 --- a/src/mainboard/amd/onyx/devicetree.cb +++ b/src/mainboard/amd/onyx/devicetree.cb @@ -1,5 +1,18 @@ chip soc/amd/genoa + # eSPI configuration + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN, + .io_mode = ESPI_IO_MODE_SINGLE, + .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, + .crc_check_enable = 1, + .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, + .periph_ch_en = 0, + .vw_ch_en = 0, + .oob_ch_en = 0, + .flash_ch_en = 0, + }" + device domain 0 on end diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig index d380365..3044d71 100644 --- a/src/soc/amd/genoa/Kconfig +++ b/src/soc/amd/genoa/Kconfig @@ -12,9 +12,12 @@ select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H + select SOC_AMD_COMMON_BLOCK_HAS_ESPI + select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_TSC + select SOC_AMD_COMMON_BLOCK_USE_ESPI select X86_CUSTOM_BOOTMEDIA config USE_EXP_X86_64_SUPPORT diff --git a/src/soc/amd/genoa/early_fch.c b/src/soc/amd/genoa/early_fch.c index 21e988e..8de43e2 100644 --- a/src/soc/amd/genoa/early_fch.c +++ b/src/soc/amd/genoa/early_fch.c @@ -14,6 +14,8 @@ fch_enable_cf9_io(); enable_aoac_devices(); + + configure_espi_with_mb_hook(); } /* After console init */ diff --git a/src/soc/amd/genoa/include/soc/acpi.h b/src/soc/amd/genoa/include/soc/acpi.h new file mode 100644 index 0000000..51fa91e --- /dev/null +++ b/src/soc/amd/genoa/include/soc/acpi.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef AMD_GENOA_ACPI_H +#define AMD_GENOA_ACPI_H + +#define ACPI_SCI_IRQ 9 + +#endif /* AMD_GENOA_ACPI_H */ diff --git a/src/soc/amd/genoa/include/soc/lpc.h b/src/soc/amd/genoa/include/soc/lpc.h new file mode 100644 index 0000000..f98ffe8 --- /dev/null +++ b/src/soc/amd/genoa/include/soc/lpc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_GENOA_LPC_H +#define AMD_GENOA_LPC_H + +#define SPI_BASE_ADDRESS_REGISTER 0xa0 +#define SPI_BASE_ALIGNMENT BIT(8) +#define SPI_BASE_RESERVED (BIT(5) | BIT(6) | BIT(7)) +#define PSP_SPI_MMIO_SEL BIT(4) +#define ROUTE_TPM_2_SPI BIT(3) +#define SPI_ABORT_ENABLE BIT(2) +#define SPI_ROM_ENABLE BIT(1) +#define SPI_ROM_ALT_ENABLE BIT(0) +#define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4)) + +#endif /* AMD_GENOA_LPC_H */ diff --git a/src/soc/amd/genoa/include/soc/pci_devs.h b/src/soc/amd/genoa/include/soc/pci_devs.h new file mode 100644 index 0000000..d314deb --- /dev/null +++ b/src/soc/amd/genoa/include/soc/pci_devs.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_GENOA_PCI_DEVS_H +#define AMD_GENOA_PCI_DEVS_H + +#include <device/pci_def.h> +#include <amdblocks/pci_devs.h> + +/* GNB Root Complex */ +#define GNB_DEV 0x0 +#define GNB_FUNC 0 +#define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC) +#define SOC_GNB_DEV _SOC_DEV(GNB_DEV, GNB_FUNC) + +/* SMBUS */ +#define SMBUS_DEV 0x14 +#define SMBUS_FUNC 0 +#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) +#define SOC_SMBUS_DEV _SOC_DEV(SMBUS_DEV, SMBUS_FUNC) + +/* Data Fabric functions */ +#define DF_DEV 0x18 + +#define DF_F0_DEVFN PCI_DEVFN(DF_DEV, 0) +#define SOC_DF_F0_DEV _SOC_DEV(DF_DEV, 0) + +#define DF_F1_DEVFN PCI_DEVFN(DF_DEV, 1) +#define SOC_DF_F1_DEV _SOC_DEV(DF_DEV, 1) + +#define DF_F2_DEVFN PCI_DEVFN(DF_DEV, 2) +#define SOC_DF_F2_DEV _SOC_DEV(DF_DEV, 2) + +#define DF_F3_DEVFN PCI_DEVFN(DF_DEV, 3) +#define SOC_DF_F3_DEV _SOC_DEV(DF_DEV, 3) + +#define DF_F4_DEVFN PCI_DEVFN(DF_DEV, 4) +#define SOC_DF_F4_DEV _SOC_DEV(DF_DEV, 4) + +#define DF_F5_DEVFN PCI_DEVFN(DF_DEV, 5) +#define SOC_DF_F5_DEV _SOC_DEV(DF_DEV, 5) + +#define DF_F6_DEVFN PCI_DEVFN(DF_DEV, 6) +#define SOC_DF_F6_DEV _SOC_DEV(DF_DEV, 6) + +#define DF_F7_DEVFN PCI_DEVFN(DF_DEV, 7) +#define SOC_DF_F7_DEV _SOC_DEV(DF_DEV, 7) + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/76508?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4965eac4ec3d600b1e840affce4e5b4fa2ea4360 Gerrit-Change-Number: 76508 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: soc/amd/genoa: Add aoac.c & enable AOAC devices early
by Felix Held (Code Review) 10 Oct '23

10 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76506?usp=email ) ( 12 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/genoa: Add aoac.c & enable AOAC devices early ...................................................................... soc/amd/genoa: Add aoac.c & enable AOAC devices early Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ic9553e6016c92c9b1678c395cd6a9e6860bf8a76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76506 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/genoa/Kconfig M src/soc/amd/genoa/Makefile.inc A src/soc/amd/genoa/aoac.c M src/soc/amd/genoa/early_fch.c A src/soc/amd/genoa/include/soc/aoac_defs.h 5 files changed, 57 insertions(+), 0 deletions(-) Approvals: Felix Held: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig index 9863a59..d380365 100644 --- a/src/soc/amd/genoa/Kconfig +++ b/src/soc/amd/genoa/Kconfig @@ -10,6 +10,7 @@ select RESET_VECTOR_IN_RAM select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI_MMCONF diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc index 6b936b6..2f7241d 100644 --- a/src/soc/amd/genoa/Makefile.inc +++ b/src/soc/amd/genoa/Makefile.inc @@ -6,9 +6,11 @@ all-y += config.c bootblock-y += early_fch.c +bootblock-y += aoac.c romstage-y += romstage.c +ramstage-y += aoac.c ramstage-y += chip.c CPPFLAGS_common += -I$(src)/soc/amd/genoa/include diff --git a/src/soc/amd/genoa/aoac.c b/src/soc/amd/genoa/aoac.c new file mode 100644 index 0000000..53ba88f --- /dev/null +++ b/src/soc/amd/genoa/aoac.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <amdblocks/acpimmio.h> +#include <amdblocks/aoac.h> +#include <soc/aoac_defs.h> +#include <soc/southbridge.h> +#include <delay.h> + +#define FCH_AOAC_UART_FOR_CONSOLE \ + (CONFIG_UART_FOR_CONSOLE == 0 ? FCH_AOAC_DEV_UART0 \ + : CONFIG_UART_FOR_CONSOLE == 1 ? FCH_AOAC_DEV_UART1 \ + : CONFIG_UART_FOR_CONSOLE == 2 ? FCH_AOAC_DEV_UART2 \ + : -1) +#if CONFIG(AMD_SOC_CONSOLE_UART) && FCH_AOAC_UART_FOR_CONSOLE == -1 +# error Unsupported UART_FOR_CONSOLE chosen +#endif + +void wait_for_aoac_enabled(unsigned int dev) +{ + while (!is_aoac_device_enabled(dev)) + udelay(100); +} + +void enable_aoac_devices(void) +{ + if (CONFIG(AMD_SOC_CONSOLE_UART)) + power_on_aoac_device(FCH_AOAC_UART_FOR_CONSOLE); + + if (CONFIG(AMD_SOC_CONSOLE_UART)) + wait_for_aoac_enabled(FCH_AOAC_UART_FOR_CONSOLE); +} diff --git a/src/soc/amd/genoa/early_fch.c b/src/soc/amd/genoa/early_fch.c index d0b526c..21e988e 100644 --- a/src/soc/amd/genoa/early_fch.c +++ b/src/soc/amd/genoa/early_fch.c @@ -12,6 +12,8 @@ void fch_pre_init(void) { fch_enable_cf9_io(); + + enable_aoac_devices(); } /* After console init */ diff --git a/src/soc/amd/genoa/include/soc/aoac_defs.h b/src/soc/amd/genoa/include/soc/aoac_defs.h new file mode 100644 index 0000000..90f4de8 --- /dev/null +++ b/src/soc/amd/genoa/include/soc/aoac_defs.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_GENOA_AOAC_DEFS_H +#define AMD_GENOA_AOAC_DEFS_H + +/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */ +#define FCH_AOAC_DEV_CLK_GEN 0 +#define FCH_AOAC_DEV_I2C0 5 +#define FCH_AOAC_DEV_I2C1 6 +#define FCH_AOAC_DEV_I2C2 7 +#define FCH_AOAC_DEV_I2C3 8 +#define FCH_AOAC_DEV_I2C4 9 +#define FCH_AOAC_DEV_I2C5 10 +#define FCH_AOAC_DEV_UART0 11 +#define FCH_AOAC_DEV_UART1 12 +#define FCH_AOAC_DEV_UART2 16 +#define FCH_AOAC_DEV_AMBA 17 +#define FCH_AOAC_DEV_ESPI 27 + +#endif /* AMD_GENOA_AOAC_DEFS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/76506?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic9553e6016c92c9b1678c395cd6a9e6860bf8a76 Gerrit-Change-Number: 76506 Gerrit-PatchSet: 14 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/amd/genoa: Enable cf9 IO early
by Felix Held (Code Review) 10 Oct '23

10 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76505?usp=email ) ( 10 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/genoa: Enable cf9 IO early ...................................................................... soc/amd/genoa: Enable cf9 IO early Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I05990c2aca40d9cf47a9ebdfd269b80b8f60e300 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76505 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/genoa/early_fch.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/genoa/early_fch.c b/src/soc/amd/genoa/early_fch.c index dcb390b..d0b526c 100644 --- a/src/soc/amd/genoa/early_fch.c +++ b/src/soc/amd/genoa/early_fch.c @@ -11,7 +11,7 @@ /* Before console init */ void fch_pre_init(void) { - + fch_enable_cf9_io(); } /* After console init */ -- To view, visit https://review.coreboot.org/c/coreboot/+/76505?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I05990c2aca40d9cf47a9ebdfd269b80b8f60e300 Gerrit-Change-Number: 76505 Gerrit-PatchSet: 12 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/rex/var/karis: Set touchscreen power/reset GPIOs correctly
by Matt DeVillier (Code Review) 10 Oct '23

10 Oct '23

Attention is currently required from: David Wu, Eran Mitrani, Felix Held, Kapil Porwal, Lucas Chen, Ren Kuo, Tarun, Tyler Wang. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78254?usp=email ) Change subject: mb/google/rex/var/karis: Set touchscreen power/reset GPIOs correctly ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78254?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6c7815b81eb47fb41e58233fde512ac6b9c000a7 Gerrit-Change-Number: 78254 Gerrit-PatchSet: 6 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 10 Oct 2023 15:47:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/amd/genoa/include: add data_fabric.h
by Felix Held (Code Review) 10 Oct '23

10 Oct '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78306?usp=email ) Change subject: soc/amd/genoa/include: add data_fabric.h ...................................................................... soc/amd/genoa/include: add data_fabric.h Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I18871af0a8dbc1423524b681d516476e63b9596a --- A src/soc/amd/genoa/include/soc/data_fabric.h 1 file changed, 124 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/78306/1 diff --git a/src/soc/amd/genoa/include/soc/data_fabric.h b/src/soc/amd/genoa/include/soc/data_fabric.h new file mode 100644 index 0000000..6388926 --- /dev/null +++ b/src/soc/amd/genoa/include/soc/data_fabric.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_GENOA_DATA_FABRIC_H +#define AMD_GENOA_DATA_FABRIC_H + +#include <amdblocks/data_fabric_defs.h> +#include <types.h> + +#define DF_PCI_CFG_BASE0 DF_REG_ID(0, 0xc80) +#define DF_PCI_CFG_LIMIT0 DF_REG_ID(0, 0xc84) + +#define DF_PCI_CFG_MAP_COUNT 8 + +#define DF_PCI_CFG_REG_OFFSET(instance) ((instance) * 2 * sizeof(uint32_t)) +#define DF_PCI_CFG_BASE(reg) (DF_PCI_CFG_BASE0 + DF_PCI_CFG_REG_OFFSET(reg)) +#define DF_PCI_CFG_LIMIT(reg) (DF_PCI_CFG_LIMIT0 + DF_PCI_CFG_REG_OFFSET(reg)) + +union df_pci_cfg_base { + struct { + uint32_t re : 1; /* [ 0.. 0] */ + uint32_t we : 1; /* [ 1.. 1] */ + uint32_t : 6; /* [ 2.. 7] */ + uint32_t segment_num : 8; /* [ 8..15] */ + uint32_t bus_num_base : 8; /* [16..23] */ + uint32_t : 8; /* [24..31] */ + }; + uint32_t raw; +}; + +union df_pci_cfg_limit { + struct { + uint32_t dst_fabric_id : 12; /* [ 0..11] */ + uint32_t : 4; /* [12..15] */ + uint32_t bus_num_limit : 8; /* [16..23] */ + uint32_t : 8; /* [24..31] */ + }; + uint32_t raw; +}; + +#define DF_IO_BASE0 DF_REG_ID(0, 0xd00) +#define DF_IO_LIMIT0 DF_REG_ID(0, 0xd04) + +#define DF_IO_REG_COUNT 8 + +#define DF_IO_REG_OFFSET(instance) ((instance) * 2 * sizeof(uint32_t)) +#define DF_IO_BASE(reg) (DF_IO_BASE0 + DF_IO_REG_OFFSET(reg)) +#define DF_IO_LIMIT(reg) (DF_IO_LIMIT0 + DF_IO_REG_OFFSET(reg)) + +union df_io_base { + struct { + uint32_t re : 1; /* [ 0.. 0] */ + uint32_t we : 1; /* [ 1.. 1] */ + uint32_t : 3; /* [ 2.. 4] */ + uint32_t ie : 1; /* [ 5.. 5] */ + uint32_t : 10; /* [ 6..15] */ + uint32_t io_base : 13; /* [16..28] */ + uint32_t : 3; /* [29..31] */ + }; + uint32_t raw; +}; + +union df_io_limit { + struct { + uint32_t dst_fabric_id : 12; /* [ 0..11] */ + uint32_t : 4; /* [12..15] */ + uint32_t io_limit : 13; /* [16..28] */ + uint32_t : 3; /* [29..31] */ + }; + uint32_t raw; +}; + +#define DF_IO_ADDR_SHIFT 12 + +#define DF_MMIO_BASE0 DF_REG_ID(0, 0xd80) +#define DF_MMIO_LIMIT0 DF_REG_ID(0, 0xd84) +#define DF_MMIO_SHIFT 16 +#define DF_MMIO_CTRL0 DF_REG_ID(0, 0xd88) +#define DF_MMIO_ADDR_EXT0 DF_REG_ID(0, 0xd8c) +#define DF_MMIO_EXT_ADDR_SHIFT 48 + +#define DF_MMIO_REG_SET_SIZE 4 +#define DF_MMIO_REG_SET_COUNT 16 + +union df_mmio_control { + struct { + uint32_t re : 1; /* [ 0.. 0] */ + uint32_t we : 1; /* [ 1.. 1] */ + uint32_t : 1; /* [ 2.. 2] */ + uint32_t np : 1; /* [ 3.. 3] */ + uint32_t : 12; /* [ 4..15] */ + uint32_t dst_fabric_id : 12; /* [16..27] */ + uint32_t : 4; /* [28..31] */ + }; + uint32_t raw; +}; + +union df_mmio_addr_ext { + struct { + uint32_t base_ext : 8; /* [ 0.. 7] */ + uint32_t : 8; /* [ 8..15] */ + uint32_t limit_ext : 8; /* [16..23] */ + uint32_t : 8; /* [24..31] */ + }; + uint32_t raw; +}; + +#define DF_FICAA_BIOS DF_REG_ID(4, 0x8C) +#define DF_FICAD_LO DF_REG_ID(4, 0xB8) +#define DF_FICAD_HI DF_REG_ID(4, 0xBC) + +union df_ficaa { + struct { + uint32_t cfg_inst_acc_en : 1; /* [ 0.. 0] */ + uint32_t reg_num : 10; /* [10.. 1] */ + uint32_t func_num : 3; /* [13..11] */ + uint32_t b64_en : 1; /* [14..14] */ + uint32_t : 1; /* [15..15] */ + uint32_t inst_id : 8; /* [23..16] */ + uint32_t : 8; /* [31..24] */ + }; + uint32_t raw; +}; + +#endif /* AMD_GENOA_DATA_FABRIC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/78306?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I18871af0a8dbc1423524b681d516476e63b9596a Gerrit-Change-Number: 78306 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/rex/var/karis: Set touchscreen power/reset GPIOs correctly
by Subrata Banik (Code Review) 10 Oct '23

10 Oct '23

Attention is currently required from: David Wu, Eran Mitrani, Felix Held, Kapil Porwal, Lucas Chen, Matt DeVillier, Ren Kuo, Tarun, Tyler Wang. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78254?usp=email ) Change subject: mb/google/rex/var/karis: Set touchscreen power/reset GPIOs correctly ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78254?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6c7815b81eb47fb41e58233fde512ac6b9c000a7 Gerrit-Change-Number: 78254 Gerrit-PatchSet: 6 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 10 Oct 2023 14:26:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/rex/var/karis: Fix touchscreen HID to ELAN9004
by Subrata Banik (Code Review) 10 Oct '23

10 Oct '23

Attention is currently required from: David Wu, Eran Mitrani, Kapil Porwal, Paul Menzel, Tarun, Tyler Wang. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78266?usp=email ) Change subject: mb/google/rex/var/karis: Fix touchscreen HID to ELAN9004 ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78266?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ebb02540c894460388b9b9fe03f5c4031f8186d Gerrit-Change-Number: 78266 Gerrit-PatchSet: 7 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 10 Oct 2023 14:25:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: amdfwtool: Set the table size as the sum of entries and header
by Nikolai Vyssotski (Code Review) 10 Oct '23

10 Oct '23

Attention is currently required from: Bao Zheng, Martin Roth, Zheng Bao. Nikolai Vyssotski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78274?usp=email ) Change subject: amdfwtool: Set the table size as the sum of entries and header ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/78274?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id4fbc6d57d7ea070a9478649a96af92be9441289 Gerrit-Change-Number: 78274 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Tue, 10 Oct 2023 13:58:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/brya/var/dochi: update gpio settings
by Felix Held (Code Review) 10 Oct '23

10 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78112?usp=email ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/brya/var/dochi: update gpio settings ...................................................................... mb/google/brya/var/dochi: update gpio settings Configure GPIOs according to schematics revision 20230923. TEST=emerge-brya coreboot Change-Id: I10bd1b72c9b0299b8d29ab642fddb5f0c4727652 Signed-off-by: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78112 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/dochi/Makefile.inc A src/mainboard/google/brya/variants/dochi/gpio.c 2 files changed, 212 insertions(+), 0 deletions(-) Approvals: David Wu: Looks good to me, but someone else must approve build bot (Jenkins): Verified Ren Kuo: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/dochi/Makefile.inc b/src/mainboard/google/brya/variants/dochi/Makefile.inc index c44e4f0..defb592 100644 --- a/src/mainboard/google/brya/variants/dochi/Makefile.inc +++ b/src/mainboard/google/brya/variants/dochi/Makefile.inc @@ -1,2 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c romstage-y += memory.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/dochi/gpio.c b/src/mainboard/google/brya/variants/dochi/gpio.c new file mode 100644 index 0000000..8c6fb09 --- /dev/null +++ b/src/mainboard/google/brya/variants/dochi/gpio.c @@ -0,0 +1,207 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A6 : ESPI_ALERT1# ==> NC */ + PAD_NC(GPP_A6, NONE), + /* A7 : SRCCLK_OE7# ==> NC */ + PAD_NC(GPP_A7, NONE), + /* A8 : SRCCLKREQ7# ==> NC */ + PAD_NC(GPP_A8, NONE), + /* A12 : SATAXPCIE1 ==> NC */ + PAD_NC(GPP_A12, NONE), + /* A15 : USB_OC2# ==> NC */ + PAD_NC(GPP_A15, NONE), + /* A19 : DDSP_HPD1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC(GPP_A20, NONE), + + /* B3 : PROC_GP2 ==> NC */ + PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG), + + /* D3 : ISH_GP3 ==> NC */ + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* D6 : SRCCLKREQ1# ==> APU_PEN_DETECT_ODL */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_D6, NONE, PLTRST), + /* D7 : SRCCLKREQ2# ==> NC */ + PAD_NC(GPP_D7, NONE), + /* D8 : SRCCLKREQ3# ==> NC */ + PAD_NC(GPP_D8, NONE), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG), + /* D16 : ISH_UART0_CTS# ==> NC */ + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), + /* D17 : UART1_RXD ==> APU_PEN_DETECT_ODL */ + PAD_CFG_GPI_SCI_LOCK(GPP_D17, NONE, EDGE_SINGLE, NONE, LOCK_CONFIG), + /* D18 : UART1_TXD ==> NC */ + PAD_NC_LOCK(GPP_D18, NONE, LOCK_CONFIG), + + /* E0 : SATAXPCIE0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E3 : PROC_GP0 ==> NC */ + PAD_NC(GPP_E3, NONE), + /* E4 : SATA_DEVSLP0 ==> NC */ + PAD_NC(GPP_E4, NONE), + /* E7 : PROC_GP1 ==> NC */ + PAD_NC(GPP_E7, NONE), + /* E10 : THC0_SPI1_CS# ==> NC */ + PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG), + /* E17 : THC0_SPI1_INT# ==> NC */ + PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + + /* F6 : CNV_PA_BLANKING ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F20 : EXT_PWR_GATE# ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : EXT_PWR_GATE2# ==> NC */ + PAD_NC(GPP_F21, NONE), + + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), + /* H8 : I2C4_SDA ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : I2C4_SCL ==> NC */ + PAD_NC(GPP_H9, NONE), + /* H12 : I2C7_SDA ==> NC */ + PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), + /* H13 : I2C7_SCL ==> NC */ + PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG), + /* H19 : SRCCLKREQ4# ==> EMMC_CLKREQ_ODL */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + /* H20 : IMGCLKOUT1 ==> NC */ + PAD_NC(GPP_H20, NONE), + /* H21 : IMGCLKOUT2 ==> NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : SRCCLKREQ5# ==> NC */ + PAD_NC(GPP_H23, NONE), + + /* R4 : HDA_RST# ==> DMIC_CLK0_R */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), + /* R5 : HDA_SDI1 ==> DMIC_DATA0_R */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), + /* R6 : I2S2_TXD ==> DMIC_CLK1_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), + /* R7 : I2S2_RXD ==> DMIC_DATA1_R */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), + + /* S0 : SNDW0_CLK ==> I2S1_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), + /* S1 : SNDW0_DATA ==> I2S1_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), + /* S2 : SNDW1_CLK ==> I2S1_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), + /* S3 : SNDW1_DATA ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), + + /* GPD11: LANPHYC ==> NC */ + PAD_NC(GPD11, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* + * D1 : ISH_GP1 ==> FP_RST_ODL + * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. + * To ensure proper power sequencing for the FPMCU device, reset signal is driven low + * early on in bootblock, followed by enabling of power. Reset signal is deasserted + * later on in ramstage. Since reset signal is asserted in bootblock, it results in + * FPMCU not working after a S3 resume. This is a known issue. + */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* E0 : SATAXPCIE0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + + /* Enable touchscreen, hold in reset */ + /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C1, 0, DEEP), + + /* D1 : ISH_GP1 ==> FP_RST_ODL */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 0, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/78112?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10bd1b72c9b0299b8d29ab642fddb5f0c4727652 Gerrit-Change-Number: 78112 Gerrit-PatchSet: 7 Gerrit-Owner: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit October 2023