coreboot-gerrit October 2023

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: SNB+MRC boards: Do not redo PEI data struct in hook
by Patrick Rudolph (Code Review) 12 Oct '23

12 Oct '23

Attention is currently required from: Alexander Couzens, Angel Pons, Keith Hui, Martin L Roth, Nico Huber. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76962?usp=email ) Change subject: SNB+MRC boards: Do not redo PEI data struct in hook ...................................................................... Patch Set 5: (1 comment) File src/mainboard/roda/rv11/variants/rw11/early_init.c: https://review.coreboot.org/c/coreboot/+/76962/comment/2fe61d56_f70fbad1 : PS5, Line 65: usb3 > Fully migrate this and USB config to devicetree? (This also needs to be addressed but that setting c […] Yes, ideally everything, including USB config resides in devicetree. That would allow to select native init/MRC.bin for all boards as there would be no mainboard specific code and no duplicated code any more. -- To view, visit https://review.coreboot.org/c/coreboot/+/76962?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie349a8f400eecca3cdbc196ea0790aebe0549e39 Gerrit-Change-Number: 76962 Gerrit-PatchSet: 5 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Thu, 12 Oct 2023 14:44:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: Documentation: add Nitrokey to distributions
by Paul Menzel (Code Review) 12 Oct '23

12 Oct '23

Attention is currently required from: Markus Meissner, Patrick Georgi. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78299?usp=email ) Change subject: Documentation: add Nitrokey to distributions ...................................................................... Patch Set 1: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/78299/comment/693a06cb_a79af27f : PS1, Line 9: Coreboot Please spell it lowercase. Patchset: PS1: Thank you. It’d be great, if you could be so kind to send a follow-up patch to sort the list alphabetically. File Documentation/distributions.md: https://review.coreboot.org/c/coreboot/+/78299/comment/0e17e7b4_3f03a92d : PS1, Line 14: Coreboot Ditto. https://review.coreboot.org/c/coreboot/+/78299/comment/b567ffdc_74044192 : PS1, Line 19: e-mail email -- To view, visit https://review.coreboot.org/c/coreboot/+/78299?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ef25e0e1cb97eda5fd457bdb650f3ee3f00210a Gerrit-Change-Number: 78299 Gerrit-PatchSet: 1 Gerrit-Owner: Markus Meissner Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Markus Meissner Gerrit-Comment-Date: Thu, 12 Oct 2023 14:39:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/rex/var/karis: Fix touchscreen HID to ELAN9004
by Felix Held (Code Review) 12 Oct '23

12 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78266?usp=email ) Change subject: mb/google/rex/var/karis: Fix touchscreen HID to ELAN9004 ...................................................................... mb/google/rex/var/karis: Fix touchscreen HID to ELAN9004 Confirmed with vendor, Elan touchscreen HID should set to "ELAN9004". Correct Elan touchscreen HID to "ELAN9004" for karis. BUG=b:294155897 TEST=Dump the SSDT on karis and check the HID had been modified. Change-Id: I6ebb02540c894460388b9b9fe03f5c4031f8186d Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78266 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/variants/karis/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/karis/overridetree.cb b/src/mainboard/google/rex/variants/karis/overridetree.cb index 98769de..24dec6f 100644 --- a/src/mainboard/google/rex/variants/karis/overridetree.cb +++ b/src/mainboard/google/rex/variants/karis/overridetree.cb @@ -366,7 +366,7 @@ end #I2C0 device ref i2c1 on chip drivers/i2c/hid - register "generic.hid" = ""ELAN90FC"" + register "generic.hid" = ""ELAN9004"" register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C07_IRQ)" register "generic.detect" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/78266?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ebb02540c894460388b9b9fe03f5c4031f8186d Gerrit-Change-Number: 78266 Gerrit-PatchSet: 8 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: sb/intel/bd82x6x/pcie: Drop register write
by Felix Held (Code Review) 12 Oct '23

12 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78238?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: sb/intel/bd82x6x/pcie: Drop register write ...................................................................... sb/intel/bd82x6x/pcie: Drop register write The write to register 0x42 has no effect as at this point all of the bits are read-only. Drop the line. Change-Id: I7293e6eaa2d0bac5efe8316029bdecb04a5586e9 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78238 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/southbridge/intel/bd82x6x/pcie.c 1 file changed, 1 insertion(+), 3 deletions(-) Approvals: Kyösti Mälkki: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 45ce5aa..325bfd2 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -229,10 +229,8 @@ pci_write_config16(dev, 0x1e, reg16); /* Enable expresscard hotplug events. */ - if (pci_is_hotplugable(dev)) { + if (pci_is_hotplugable(dev)) pci_or_config32(dev, 0xd8, 1 << 30); - pci_write_config16(dev, 0x42, 0x142); - } } static void pch_pcie_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/78238?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7293e6eaa2d0bac5efe8316029bdecb04a5586e9 Gerrit-Change-Number: 78238 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: sb/intel/bd82x6x/pch: Mark static devices hidden
by Felix Held (Code Review) 12 Oct '23

12 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78230?usp=email ) Change subject: sb/intel/bd82x6x/pch: Mark static devices hidden ...................................................................... sb/intel/bd82x6x/pch: Mark static devices hidden Because integrated PCI devices are hidden in chip_ops the PCI enumeration code never sees them. When hiding static devices mark them as hidden so the PCI enumeration no longer complains about them being missing, even though they are present and were working just fine. Test: Disabled southbridge devices no longer appear in "Leftover static devices:" log. Change-Id: Iae70072a85b62a456102190a5f72f4d652ad6d5a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78230 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/bd82x6x/pch.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: Kyösti Mälkki: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index c668f9a6..a7ab83a 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -131,6 +131,10 @@ /* Set bit in function disable register to hide this device */ static void pch_hide_devfn(unsigned int devfn) { + struct device *dev = pcidev_path_on_root(devfn); + if (dev) + dev->hidden = true; + switch (devfn) { case PCI_DEVFN(20, 0): /* xHCI */ if (pch_silicon_type() == PCH_TYPE_PPT) { -- To view, visit https://review.coreboot.org/c/coreboot/+/78230?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae70072a85b62a456102190a5f72f4d652ad6d5a Gerrit-Change-Number: 78230 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: sb/intel/bd82x6x: Warn about slow PCIe downstream devices
by Felix Held (Code Review) 12 Oct '23

12 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78229?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: sb/intel/bd82x6x: Warn about slow PCIe downstream devices ...................................................................... sb/intel/bd82x6x: Warn about slow PCIe downstream devices Warn when a device took longer than usual to appear. Use the PDS bit to detect if a root port has a downstream device connected and warn if enumeration failed. Test: On Lenovo X220 all PCIe device are visible, thus the added code path is never taken. Change-Id: I86b498b89d672b239d9951e116dc3680030666a6 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78229 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/southbridge/intel/bd82x6x/pcie.c 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 2658fd3..45ce5aa 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -243,12 +243,18 @@ static void pch_pciexp_scan_bridge(struct device *dev) { + uint32_t cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); + if (CONFIG(PCIEXP_HOTPLUG) && pci_is_hotplugable(dev)) { pciexp_hotplug_scan_bridge(dev); } else { /* Normal PCIe Scan */ pciexp_scan_bridge(dev); } + if ((pci_read_config16(dev, cap + PCI_EXP_SLTSTA) & PCI_EXP_SLTSTA_PDS) && + !dev_is_active_bridge(dev)) + printk(BIOS_WARNING, "%s: Has a slow downstream device. Enumeration failed.\n", + dev_path(dev)); /* Late Power Management init after bridge device enumeration */ pch_pcie_pm_late(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/78229?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86b498b89d672b239d9951e116dc3680030666a6 Gerrit-Change-Number: 78229 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: sb/intel/bd82x6x/pcie: Use defines
by Felix Held (Code Review) 12 Oct '23

12 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78293?usp=email ) Change subject: sb/intel/bd82x6x/pcie: Use defines ...................................................................... sb/intel/bd82x6x/pcie: Use defines Use defines instead of magic values. Test: Lenovo X220 still boots and all PCIe devices are still working. Change-Id: Ie8fc7cc863017da07dd3ed37b487dae18de92b18 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78293 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/southbridge/intel/bd82x6x/pcie.c 1 file changed, 7 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index da6e007..2658fd3 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -126,17 +126,19 @@ reg32 &= ~(1 << 31); /* Disable PME# SCI for native PME handling */ pci_write_config32(dev, 0xd8, reg32); + cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); + /* Adjust ASPM L1 exit latency */ - reg32 = pci_read_config32(dev, 0x4c); - reg32 &= ~((1 << 17) | (1 << 16) | (1 << 15)); + reg32 = pci_read_config32(dev, cap + PCI_EXP_LNKCAP); + reg32 &= ~PCI_EXP_LNKCAP_L1EL; if (RCBA32(CIR9) & (1 << 16)) { /* If RCBA+2320[15]=1 set ASPM L1 to 8-16us */ - reg32 |= (1 << 17); + reg32 |= (4 << 15); } else { /* Else set ASPM L1 to 2-4us */ - reg32 |= (1 << 16); + reg32 |= (2 << 15); } - pci_write_config32(dev, 0x4c, reg32); + pci_write_config32(dev, cap + PCI_EXP_LNKCAP, reg32); /* * PCI device enumeration hasn't started yet, thus any downstream device here @@ -147,8 +149,6 @@ child = pcidev_path_behind(dev->link_list, PCI_DEVFN(0, 0)); /* Set slot power limit as configured above */ - cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); - reg32 = pci_read_config32(dev, cap + PCI_EXP_SLTCAP); if (pci_is_hotplugable(dev)) reg32 |= (PCI_EXP_SLTCAP_HPS | PCI_EXP_SLTCAP_HPC); -- To view, visit https://review.coreboot.org/c/coreboot/+/78293?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie8fc7cc863017da07dd3ed37b487dae18de92b18 Gerrit-Change-Number: 78293 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: sb/intel/bd82x6x: Improve SLCAP
by Felix Held (Code Review) 12 Oct '23

12 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78228?usp=email ) Change subject: sb/intel/bd82x6x: Improve SLCAP ...................................................................... sb/intel/bd82x6x: Improve SLCAP - Use pci_find_capability() and defines from pci_def.h - Set the 'Hotplug Capable' bit and 'Hot Plug Surprise' bit in SLCAP for hotplugable PCIe slots. - Assign unique slot number and set power limit for PCIe root ports that have a slot connected. For integrated devices clear slot number and power limit. Test: System still boots and all PCIe devices are working. Change-Id: I03aeb0a1ff0041901acc20fe700d3f7995d22366 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78228 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/bd82x6x/pcie.c 1 file changed, 27 insertions(+), 6 deletions(-) Approvals: Kyösti Mälkki: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 206894d..da6e007 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -42,8 +42,10 @@ static void pch_pcie_pm_early(struct device *dev) { u16 link_width_p0, link_width_p4; + struct device *child = NULL; u8 slot_power_limit = 10; /* 10W for x1 */ - u32 reg32; + static u8 slot_number = 1; + u32 reg32, cap; u8 reg8; reg32 = RCBA32(RPC); @@ -136,12 +138,31 @@ } pci_write_config32(dev, 0x4c, reg32); + /* + * PCI device enumeration hasn't started yet, thus any downstream device here + * must be a static device from devicetree.cb. + * If one is found assume it's an integrated device and not a PCIe slot. + */ + if (dev->link_list) + child = pcidev_path_behind(dev->link_list, PCI_DEVFN(0, 0)); + /* Set slot power limit as configured above */ - reg32 = pci_read_config32(dev, 0x54); - reg32 &= ~((1 << 15) | (1 << 16)); /* 16:15 = Slot power scale */ - reg32 &= ~(0xff << 7); /* 14:7 = Slot power limit */ - reg32 |= (slot_power_limit << 7); - pci_write_config32(dev, 0x54, reg32); + cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); + + reg32 = pci_read_config32(dev, cap + PCI_EXP_SLTCAP); + if (pci_is_hotplugable(dev)) + reg32 |= (PCI_EXP_SLTCAP_HPS | PCI_EXP_SLTCAP_HPC); + else + reg32 &= ~(PCI_EXP_SLTCAP_HPS | PCI_EXP_SLTCAP_HPC); + reg32 &= ~PCI_EXP_SLTCAP_SPLS; /* 16:15 = Slot power scale */ + reg32 &= ~PCI_EXP_SLTCAP_SPLV; /* 14:7 = Slot power limit */ + reg32 &= ~PCI_EXP_SLTCAP_PSN; + if (!child || !child->on_mainboard) { + /* Only PCIe slots have a power limit and slot number */ + reg32 |= (slot_power_limit << 7); + reg32 |= (slot_number++ << 19); + } + pci_write_config32(dev, cap + PCI_EXP_SLTCAP, reg32); } static void pch_pcie_pm_late(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/78228?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03aeb0a1ff0041901acc20fe700d3f7995d22366 Gerrit-Change-Number: 78228 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: Documentation: add Nitrokey to distributions
by Markus Meissner (Code Review) 12 Oct '23

12 Oct '23

Attention is currently required from: Markus Meissner, Patrick Georgi. Markus Meissner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78299?usp=email ) Change subject: Documentation: add Nitrokey to distributions ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Hey, we would be happy to have Nitrokey listed inside the documentation. Hope you are the correct reviewer to address here. thx -- To view, visit https://review.coreboot.org/c/coreboot/+/78299?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ef25e0e1cb97eda5fd457bdb650f3ee3f00210a Gerrit-Change-Number: 78299 Gerrit-PatchSet: 1 Gerrit-Owner: Markus Meissner Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Markus Meissner Gerrit-Comment-Date: Thu, 12 Oct 2023 12:23:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: Documentation: add Nitrokey to distributions
by Markus Meissner (Code Review) 12 Oct '23

12 Oct '23

Markus Meissner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78299?usp=email ) Change subject: Documentation: add Nitrokey to distributions ...................................................................... Documentation: add Nitrokey to distributions Nitrokey offers various products, which have Coreboot pre-installed. Change-Id: I3ef25e0e1cb97eda5fd457bdb650f3ee3f00210a Signed-off-by: Markus Meissner <coder(a)safemailbox.de> --- M Documentation/distributions.md 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/78299/1 diff --git a/Documentation/distributions.md b/Documentation/distributions.md index 139e5b6..b644c7a 100644 --- a/Documentation/distributions.md +++ b/Documentation/distributions.md @@ -8,6 +8,16 @@ ## Hardware shipping with coreboot +### Nitrokey + +[Nitrokey](https://nitrokey.com) is a German IT security hardware vendor which +offers a range of laptops, PCs, HSM, and networking devices with Coreboot and +[Dasharo](https://dasharo.com/). The devices come with neutralized Intel +Management Engine (ME) and with pre-installed [Heads](http://osresearch.net) or +edk2 payload providing measured boot and verified boot protection. For +additional security the systems can be physically sealed and pictures of those +sealings are send via encrypted e-mail. + ### NovaCustom laptops [NovaCustom](https://configurelaptop.eu/) sells configurable laptops with -- To view, visit https://review.coreboot.org/c/coreboot/+/78299?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ef25e0e1cb97eda5fd457bdb650f3ee3f00210a Gerrit-Change-Number: 78299 Gerrit-PatchSet: 1 Gerrit-Owner: Markus Meissner Gerrit-MessageType: newchange

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2016

2015

2014

2013

coreboot-gerrit October 2023