coreboot-gerrit October 2023

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: device/device.h: Rename busses for clarity
by Arthur Heymans (Code Review) 12 Oct '23

12 Oct '23

Attention is currently required from: Angel Pons, Boris Mittelberg, Caveh Jalali, Christian Walter, Eran Mitrani, Felix Held, Fred Reitberger, Jason Glenesk, Jason Nien, Jeff Daly, Johnny Lin, Kapil Porwal, Lance Zhao, Martin L Roth, Martin Roth, Matt DeVillier, Michał Żygowski, Nick Vaccaro, Piotr Król, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Tim Wawrzynczak, Vanessa Eusebio, Werner Zeh. Hello Angel Pons, Boris Mittelberg, Caveh Jalali, Christian Walter, Eran Mitrani, Felix Held, Fred Reitberger, Jason Glenesk, Jason Nien, Jeff Daly, Johnny Lin, Kapil Porwal, Lance Zhao, Martin L Roth, Martin Roth, Matt DeVillier, Michał Żygowski, Nick Vaccaro, Piotr Król, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Tim Wawrzynczak, Vanessa Eusebio, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78330?usp=email to look at the new patch set (#4). Change subject: device/device.h: Rename busses for clarity ...................................................................... device/device.h: Rename busses for clarity This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 --- M src/acpi/acpi.c M src/acpi/device.c M src/arch/x86/mpspec.c M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/device/cardbus_device.c M src/device/device.c M src/device/device_const.c M src/device/device_util.c M src/device/i2c_bus.c M src/device/mdio.c M src/device/oprom/realmode/x86.c M src/device/oprom/realmode/x86_interrupts.c M src/device/oprom/yabel/device.c M src/device/oprom/yabel/interrupt.c M src/device/pci_device.c M src/device/pci_rom.c M src/device/pciexp_device.c M src/device/pcix_device.c M src/device/pnp_device.c M src/device/resource_allocator_v4.c M src/device/root_device.c M src/drivers/i2c/ptn3460/ptn3460.c M src/drivers/intel/dptf/dptf.c M src/drivers/intel/ish/ish.c M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/soundwire/soundwire.c M src/drivers/net/phy/m88e1512/m88e1512.c M src/drivers/net/r8168.c M src/drivers/nxp/uwb/uwb.c M src/drivers/pcie/generic/generic.c M src/drivers/spi/acpi/acpi.c M src/drivers/usb/hub/acpi.c M src/drivers/usb/pci_xhci/pci_xhci.c M src/drivers/wifi/generic/acpi.c M src/drivers/wifi/generic/smbios.c M src/drivers/wwan/fm/acpi_fm350gl.c M src/ec/google/chromeec/ec_acpi.c M src/include/device/device.h M src/include/device/pci_ops.h M src/lib/smbios.c M src/mainboard/aopen/dxplplusu/acpi_tables.c M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/google/brya/mainboard.c M src/mainboard/google/kahlee/variants/careena/mainboard.c M src/mainboard/google/kahlee/variants/treeya/audio.c M src/mainboard/google/octopus/mainboard.c M src/mainboard/google/rex/mainboard.c M src/mainboard/google/zork/variants/baseboard/ramstage_common.c M src/mainboard/ibase/mb899/mptable.c M src/mainboard/kontron/986lcd-m/mptable.c M src/mainboard/pcengines/apu2/mainboard.c M src/mainboard/roda/rk9/ti_pci7xx1.c M src/mainboard/siemens/fa_ehl/mainboard.c M src/mainboard/siemens/mc_apl1/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c M src/mainboard/siemens/mc_ehl/mainboard.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/haswell/pcie.c M src/northbridge/intel/i440bx/northbridge.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/sandybridge/pcie.c M src/northbridge/intel/x4x/northbridge.c M src/soc/amd/cezanne/xhci.c M src/soc/amd/common/block/acpi/ivrs.c M src/soc/amd/common/block/data_fabric/domain.c M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/glinda/xhci.c M src/soc/amd/mendocino/xhci.c M src/soc/amd/phoenix/xhci.c M src/soc/amd/picasso/xhci.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/cavium/cn81xx/ecam0.c M src/soc/intel/apollolake/chip.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/common/block/acpi/pep.c M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/pcie/rtd3/rtd3.c M src/soc/intel/common/block/usb4/pcie.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/skylake/chip.c M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/soc_acpi.c M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/soc/intel/xeon_sp/spr/soc_acpi.c M src/soc/intel/xeon_sp/uncore.c M src/soc/intel/xeon_sp/uncore_acpi.c M src/southbridge/amd/pi/hudson/lpc.c M src/superio/common/generic.c M src/superio/common/ssdt.c M util/sconfig/main.c 99 files changed, 313 insertions(+), 319 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/78330/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/78330?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Gerrit-Change-Number: 78330 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/rex/var/rex: Configure PL4 to 64W if battery status is invalid
by Jamie Ryu (Code Review) 12 Oct '23

12 Oct '23

Attention is currently required from: Brandon Breitenstein, Caveh Jalali, Hannah Williams, Subrata Banik, Sukumar Ghorai. Jamie Ryu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78322?usp=email ) Change subject: mb/google/rex/var/rex: Configure PL4 to 64W if battery status is invalid ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/78322?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I12fd40abda76c8e7522b06a5aee72665f32ddec8 Gerrit-Change-Number: 78322 Gerrit-PatchSet: 5 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Comment-Date: Thu, 12 Oct 2023 17:55:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: ec/google/chromeec: Add read_battery_status to get dynamic battery flags
by Jamie Ryu (Code Review) 12 Oct '23

12 Oct '23

Attention is currently required from: Brandon Breitenstein, Caveh Jalali, Hannah Williams, Kapil Porwal, Subrata Banik, Sukumar Ghorai. Jamie Ryu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78321?usp=email ) Change subject: ec/google/chromeec: Add read_battery_status to get dynamic battery flags ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/78321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib38be55bc42559bab4f12d5e8580ddc3e1a6acc1 Gerrit-Change-Number: 78321 Gerrit-PatchSet: 4 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Comment-Date: Thu, 12 Oct 2023 17:55:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: mb/google/brox: Create new Brox baseboard
by Nick Vaccaro (Code Review) 12 Oct '23

12 Oct '23

Attention is currently required from: Paul Menzel, Shelley Chen. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78009?usp=email ) Change subject: mb/google/brox: Create new Brox baseboard ...................................................................... Patch Set 11: (19 comments) File src/mainboard/google/brox/Kconfig: https://review.coreboot.org/c/coreboot/+/78009/comment/ad19cb6a_40d7142f : PS11, Line 145: config INCLUDE_NVIDIA_GPU_ASL : def_bool n : help : Select this if the variant has an Nvidia GN20 GPU attached to PEG1 Is Nvidia GN20 GPU attached to PEG1 an option for Brox? File src/mainboard/google/brox/Kconfig.name: https://review.coreboot.org/c/coreboot/+/78009/comment/d0f1f10b_3d3548f1 : PS11, Line 5: select BOARD_GOOGLE_BASEBOARD_BROX selects now go in Kconfig File src/mainboard/google/brox/acpi/power.asl: https://review.coreboot.org/c/coreboot/+/78009/comment/2e347aae_af20954e : PS11, Line 9: if CONFIG(BOARD_GOOGLE_AGAH) : #define GPIO_1V8_PWR_EN GPP_F12 : : #define GPIO_NV33_PWR_EN GPP_A21 : #define GPIO_NV33_PG GPP_A22 : #else : remove https://review.coreboot.org/c/coreboot/+/78009/comment/780ae919_aaff6ca3 : PS11, Line 35: NIT - extra tab https://review.coreboot.org/c/coreboot/+/78009/comment/07ccb788_36f335db : PS11, Line 47: For board revs 3 and later, two pins moved: This comment is not really valid as written. https://review.coreboot.org/c/coreboot/+/78009/comment/8a4581f5_a2de742b : PS11, Line 132: #if CONFIG(BOARD_GOOGLE_AGAH) : STXS (GPIO_FBVDD_PWR_EN) : #else : remove https://review.coreboot.org/c/coreboot/+/78009/comment/c229189f_fff8fc97 : PS11, Line 140: #if CONFIG(BOARD_GOOGLE_AGAH) : Sleep (10) : #else : remove https://review.coreboot.org/c/coreboot/+/78009/comment/d611c45a_8f0077f8 : PS11, Line 182: #if CONFIG(BOARD_GOOGLE_AGAH) : CTXS (GPIO_FBVDD_PWR_EN) : #else : remove https://review.coreboot.org/c/coreboot/+/78009/comment/3c787e25_a5f818d9 : PS11, Line 251: #if CONFIG(BOARD_GOOGLE_AGAH) : CTXS (GPIO_FBVDD_PWR_EN) : #else : remove https://review.coreboot.org/c/coreboot/+/78009/comment/6740f678_7de68aca : PS11, Line 282: #if CONFIG(BOARD_GOOGLE_AGAH) : STXS (GPIO_FBVDD_PWR_EN) : #else : remove https://review.coreboot.org/c/coreboot/+/78009/comment/f2c86548_a6dd2e86 : PS11, Line 290: #if CONFIG(BOARD_GOOGLE_AGAH) : Sleep (10) : #else : remove File src/mainboard/google/brox/chromeos.fmd: https://review.coreboot.org/c/coreboot/+/78009/comment/efb3d522_3318c77a : PS11, Line 30: brya brox https://review.coreboot.org/c/coreboot/+/78009/comment/c9dd3726_33bdc2ec : PS11, Line 39: ADL Still relevant for RPL? File src/mainboard/google/brox/dsdt.asl: https://review.coreboot.org/c/coreboot/+/78009/comment/16ff4893_067aa2db : PS11, Line 18: #include <cpu/intel/common/acpi/cpu.asl> NIT - alphabetize File src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb: https://review.coreboot.org/c/coreboot/+/78009/comment/82fc5eaa_568ce027 : PS11, Line 76: disable_c1_state_auto_demotion Is this needed for RPL-UR? File src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/ec.h: https://review.coreboot.org/c/coreboot/+/78009/comment/dc866dac_af1601b1 : PS11, Line 8: #include <baseboard/gpio.h> NIT - alphabetize https://review.coreboot.org/c/coreboot/+/78009/comment/0dba67d9_53f0e937 : PS11, Line 10: INCLUDE_NVIDIA_GPU_ASL Will this be an option for Brox? File src/mainboard/google/brox/variants/baseboard/brox/ramstage.c: https://review.coreboot.org/c/coreboot/+/78009/comment/e11e0ddb_a1ffe11a : PS11, Line 8: : #include <drivers/intel/dptf/chip.h> : #include <intelblocks/power_limit.h> NIT - alphabetize into system includes block above File src/mainboard/google/brox/variants/brox/fw_config.c: https://review.coreboot.org/c/coreboot/+/78009/comment/26441dde_dd3c9392 : PS11, Line 4: #include <console/console.h> : #include <fw_config.h> : #include <gpio.h> These aren't needed, remove. -- To view, visit https://review.coreboot.org/c/coreboot/+/78009?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I929b465646ac4c69d4bab33ce23848c7b1fa0f98 Gerrit-Change-Number: 78009 Gerrit-PatchSet: 11 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 12 Oct 2023 17:43:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: x86: Add pre-memory stages CBFS cache support
by Jérémy Compostella (Code Review) 12 Oct '23

12 Oct '23

Attention is currently required from: Angel Pons, Felix Held, Matt DeVillier. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77290?usp=email ) Change subject: x86: Add pre-memory stages CBFS cache support ...................................................................... Patch Set 61: (1 comment) File src/arch/x86/car.ld: https://review.coreboot.org/c/coreboot/+/77290/comment/3d6405f3_d1a7d581 : PS36, Line 55: PRERAM_CBFS_CACHE(., CONFIG_PRERAM_CBFS_CACHE_SIZE) > I opted for the unified CBFS cache. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/77290?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iee493f9947fddcc57576f04c3d6a2d58c7368e09 Gerrit-Change-Number: 77290 Gerrit-PatchSet: 61 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 12 Oct 2023 17:33:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: device/device.h: Rename busses for clarity
by Arthur Heymans (Code Review) 12 Oct '23

12 Oct '23

Attention is currently required from: Angel Pons, Boris Mittelberg, Caveh Jalali, Christian Walter, Eran Mitrani, Felix Held, Fred Reitberger, Jason Glenesk, Jason Nien, Jeff Daly, Johnny Lin, Kapil Porwal, Lance Zhao, Martin L Roth, Martin Roth, Matt DeVillier, Michał Żygowski, Nick Vaccaro, Piotr Król, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Tim Wawrzynczak, Vanessa Eusebio, Werner Zeh. Hello Angel Pons, Boris Mittelberg, Caveh Jalali, Christian Walter, Eran Mitrani, Felix Held, Fred Reitberger, Jason Glenesk, Jason Nien, Jeff Daly, Johnny Lin, Kapil Porwal, Lance Zhao, Martin L Roth, Martin Roth, Matt DeVillier, Michał Żygowski, Nick Vaccaro, Piotr Król, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Tim Wawrzynczak, Vanessa Eusebio, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78330?usp=email to look at the new patch set (#3). Change subject: device/device.h: Rename busses for clarity ...................................................................... device/device.h: Rename busses for clarity This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 --- M src/acpi/acpi.c M src/acpi/device.c M src/arch/x86/mpspec.c M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/device/cardbus_device.c M src/device/device.c M src/device/device_const.c M src/device/device_util.c M src/device/i2c_bus.c M src/device/mdio.c M src/device/oprom/realmode/x86.c M src/device/oprom/realmode/x86_interrupts.c M src/device/oprom/yabel/device.c M src/device/oprom/yabel/interrupt.c M src/device/pci_device.c M src/device/pci_rom.c M src/device/pciexp_device.c M src/device/pcix_device.c M src/device/pnp_device.c M src/device/resource_allocator_v4.c M src/device/root_device.c M src/drivers/i2c/ptn3460/ptn3460.c M src/drivers/intel/dptf/dptf.c M src/drivers/intel/ish/ish.c M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/soundwire/soundwire.c M src/drivers/net/phy/m88e1512/m88e1512.c M src/drivers/net/r8168.c M src/drivers/nxp/uwb/uwb.c M src/drivers/pcie/generic/generic.c M src/drivers/spi/acpi/acpi.c M src/drivers/usb/hub/acpi.c M src/drivers/usb/pci_xhci/pci_xhci.c M src/drivers/wifi/generic/acpi.c M src/drivers/wifi/generic/smbios.c M src/drivers/wwan/fm/acpi_fm350gl.c M src/ec/google/chromeec/ec_acpi.c M src/include/device/device.h M src/include/device/pci_ops.h M src/lib/smbios.c M src/mainboard/aopen/dxplplusu/acpi_tables.c M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/google/brya/mainboard.c M src/mainboard/google/kahlee/variants/careena/mainboard.c M src/mainboard/google/kahlee/variants/treeya/audio.c M src/mainboard/google/octopus/mainboard.c M src/mainboard/google/rex/mainboard.c M src/mainboard/google/zork/variants/baseboard/ramstage_common.c M src/mainboard/ibase/mb899/mptable.c M src/mainboard/kontron/986lcd-m/mptable.c M src/mainboard/pcengines/apu2/mainboard.c M src/mainboard/roda/rk9/ti_pci7xx1.c M src/mainboard/siemens/mc_apl1/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c M src/mainboard/siemens/mc_ehl/mainboard.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/haswell/pcie.c M src/northbridge/intel/i440bx/northbridge.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/sandybridge/pcie.c M src/northbridge/intel/x4x/northbridge.c M src/soc/amd/cezanne/xhci.c M src/soc/amd/common/block/acpi/ivrs.c M src/soc/amd/common/block/data_fabric/domain.c M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/glinda/xhci.c M src/soc/amd/mendocino/xhci.c M src/soc/amd/phoenix/xhci.c M src/soc/amd/picasso/xhci.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/cavium/cn81xx/ecam0.c M src/soc/intel/apollolake/chip.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/common/block/acpi/pep.c M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/pcie/rtd3/rtd3.c M src/soc/intel/common/block/usb4/pcie.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/skylake/chip.c M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/soc_acpi.c M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/soc/intel/xeon_sp/spr/soc_acpi.c M src/soc/intel/xeon_sp/uncore.c M src/soc/intel/xeon_sp/uncore_acpi.c M src/southbridge/amd/pi/hudson/lpc.c M src/superio/common/generic.c M src/superio/common/ssdt.c M util/sconfig/main.c 98 files changed, 310 insertions(+), 316 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/78330/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/78330?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Gerrit-Change-Number: 78330 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> 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1 0

[XS] Change in coreboot[main]: device/device.h: Fix outdated comment
by Arthur Heymans (Code Review) 12 Oct '23

12 Oct '23

Arthur Heymans has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/78329?usp=email ) Change subject: device/device.h: Fix outdated comment ...................................................................... device/device.h: Fix outdated comment LAPIC devices in devicetree is not possible any longer since commit 3eba665 "util/sconfig: Remove lapic devices from devicetree parsers". Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I02192c9a11c35d9625837a8a9f3ba798ff0ae611 --- M src/include/device/device.h 1 file changed, 1 insertion(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/78329/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78329?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I02192c9a11c35d9625837a8a9f3ba798ff0ae611 Gerrit-Change-Number: 78329 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

1 0

[L] Change in coreboot[main]: device/device.h: Drop multiple links
by Arthur Heymans (Code Review) 12 Oct '23

12 Oct '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier. Hello Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78328?usp=email to look at the new patch set (#2). Change subject: device/device.h: Drop multiple links ...................................................................... device/device.h: Drop multiple links Multiple links are unused throughout the tree and make the code more confusing as an iteration over all busses is needed to get downstream devices. This also not done consistently e.g. the allocator does not care about multiple links on busses. A better way of dealing multiple links below a device is to feature dummy devices with each their respective bus. This drops the sconfig capability to declare the same device multiple times which was previously used to declare multiple links. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Iab6fe269faef46ae77ed1ea425440cf5c7dbd49b --- M src/arch/x86/mpspec.c M src/device/device.c M src/device/device_util.c M src/device/pci_device.c M src/device/root_device.c M src/include/device/device.h M src/northbridge/amd/pi/00730F01/northbridge.c M src/soc/amd/common/block/acpi/ivrs.c M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/intel/common/block/lpc/lpc.c M src/southbridge/amd/pi/hudson/lpc.c M util/sconfig/main.c M util/sconfig/sconfig.h M util/sconfig/sconfig.tab.c_shipped M util/sconfig/sconfig.y 16 files changed, 187 insertions(+), 388 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/78328/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78328?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab6fe269faef46ae77ed1ea425440cf5c7dbd49b Gerrit-Change-Number: 78328 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[main]: device/device.h: Drop acpi_inject_dsdt
by Arthur Heymans (Code Review) 12 Oct '23

12 Oct '23

Attention is currently required from: Lance Zhao, Tim Wawrzynczak. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78334?usp=email ) Change subject: device/device.h: Drop acpi_inject_dsdt ...................................................................... device/device.h: Drop acpi_inject_dsdt This is now unused in the tree and filling SSDT should always be used. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Iffefc865901b15fa299931b6ed4c27a9e3a1c330 --- M src/acpi/acpi.c M src/include/device/device.h 2 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/78334/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 82846fe..0df6c62 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1293,9 +1293,6 @@ if (CONFIG(CHROMEOS_NVS)) acpi_fill_cnvs(); - for (const struct device *dev = all_devices; dev; dev = dev->next) - if (dev->ops && dev->ops->acpi_inject_dsdt) - dev->ops->acpi_inject_dsdt(dev); current = (unsigned long)acpigen_get_current(); memcpy((char *)current, (char *)dsdt_file + sizeof(acpi_header_t), diff --git a/src/include/device/device.h b/src/include/device/device.h index 6f1d13e..665d420 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -59,7 +59,6 @@ unsigned long (*write_acpi_tables)(const struct device *dev, unsigned long start, struct acpi_rsdp *rsdp); void (*acpi_fill_ssdt)(const struct device *dev); - void (*acpi_inject_dsdt)(const struct device *dev); const char *(*acpi_name)(const struct device *dev); /* Returns the optional _HID (Hardware ID) */ const char *(*acpi_hid)(const struct device *dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/78334?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iffefc865901b15fa299931b6ed4c27a9e3a1c330 Gerrit-Change-Number: 78334 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp: Add IIO resources via SSDT
by Arthur Heymans (Code Review) 12 Oct '23

12 Oct '23

Attention is currently required from: Christian Walter, Johnny Lin, Tim Chu. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78333?usp=email ) Change subject: soc/intel/xeon_sp: Add IIO resources via SSDT ...................................................................... soc/intel/xeon_sp: Add IIO resources via SSDT There is no need to inject this code in DSDT. Just generating a _CRS Name in SSDT containing a resource template works well and reduces the need to sync up on names being used to return _CRS names in DSDT. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I691d7497dceb89619652e5523a29ea30a7b0fab8 --- M src/soc/intel/xeon_sp/acpi/iiostack.asl M src/soc/intel/xeon_sp/cpx/soc_acpi.c M src/soc/intel/xeon_sp/include/soc/acpi.h M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl M src/soc/intel/xeon_sp/spr/acpi/dino_resource.asl M src/soc/intel/xeon_sp/spr/acpi/iiostack.asl M src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl M src/soc/intel/xeon_sp/spr/acpi/ubox_resource.asl M src/soc/intel/xeon_sp/spr/soc_acpi.c M src/soc/intel/xeon_sp/uncore.c 11 files changed, 44 insertions(+), 71 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/78333/1 diff --git a/src/soc/intel/xeon_sp/acpi/iiostack.asl b/src/soc/intel/xeon_sp/acpi/iiostack.asl index e5e6bdc..d2b2296 100644 --- a/src/soc/intel/xeon_sp/acpi/iiostack.asl +++ b/src/soc/intel/xeon_sp/acpi/iiostack.asl @@ -14,11 +14,6 @@ } \ Return (\_SB_.PR##rt) \ } \ - External(\_SB.RT##id) \ - Method (_CRS, 0, NotSerialized) \ - { \ - Return (\_SB.RT##id) \ - } \ Name (SUPP, 0x00) \ Name (CTRL, 0x00) \ Name (_PXM, 0x00) /* _PXM: Device Proximity */ \ diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index b43ecb2..d887cac 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -41,7 +41,7 @@ fadt->flags &= ~(ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE); } -void uncore_inject_dsdt(const struct device *device) +void uncore_fill_ssdt(const struct device *device) { struct iiostack_resource stack_info = {0}; @@ -51,15 +51,14 @@ get_iiostack_info(&stack_info); - acpigen_write_scope("\\_SB"); - for (uint8_t stack = 0; stack < stack_info.no_of_stacks; ++stack) { const STACK_RES *ri = &stack_info.res[stack]; char rtname[16]; - snprintf(rtname, sizeof(rtname), "RT%02x", stack); + snprintf(rtname, sizeof(rtname), "\\_SB.PC%02x", stack); + acpigen_write_scope(rtname); - acpigen_write_name(rtname); + acpigen_write_name("_CRS"); printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for stack: %d\n", rtname, stack); @@ -106,8 +105,10 @@ (ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1)); acpigen_write_resourcetemplate_footer(); + + /* Scope */ + acpigen_pop_len(); } - acpigen_pop_len(); } /* TODO: See if we can use the common generate_p_state_entries */ diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h index 1c0afd3..f9c55ab 100644 --- a/src/soc/intel/xeon_sp/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -20,7 +20,7 @@ unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); -void uncore_inject_dsdt(const struct device *device); +void uncore_fill_ssdt(const struct device *device); unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current); unsigned long acpi_fill_cedt(unsigned long current); unsigned long acpi_fill_hmat(unsigned long current); diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 9c02161..2e2b14a 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -54,7 +54,7 @@ fill_fadt_extended_pm_io(fadt); } -void uncore_inject_dsdt(const struct device *device) +void uncore_fill_ssdt(const struct device *device) { const IIO_UDS *hob = get_iio_uds(); @@ -62,7 +62,6 @@ if (device->upstream->secondary != 0) return; - acpigen_write_scope("\\_SB"); for (int socket = 0, iio = 0; iio < hob->PlatformData.numofIIO; ++socket) { if (!soc_cpu_is_enabled(socket)) continue; @@ -72,10 +71,12 @@ for (int stack = 0; stack <= PSTACK2; ++stack) { const STACK_RES *ri = &iio_resource.StackRes[stack]; char rtname[16]; - snprintf(rtname, sizeof(rtname), "RT%02x", - (socket*MAX_IIO_STACK)+stack); - acpigen_write_name(rtname); + snprintf(rtname, sizeof(rtname), "\\_SB.PC%02x", socket * MAX_IIO_STACK + stack); + acpigen_write_scope(rtname); + + acpigen_write_name("_CRS"); + printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n", rtname, socket, stack); @@ -126,9 +127,11 @@ (ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1)); acpigen_write_resourcetemplate_footer(); + + /* Scope */ + acpigen_pop_len(); } } - acpigen_pop_len(); } void soc_power_states_generation(int core, int cores_per_package) diff --git a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl index 3644e87..80b3da2 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl @@ -26,11 +26,6 @@ { Return (\_SB.PRTID) } - External (\_SB.IIO_DEVICE_NAME(RESPREFIX, SOCKET, STACK)) - Method (_CRS, 0, NotSerialized) - { - Return (\_SB.IIO_DEVICE_NAME(RESPREFIX, SOCKET, STACK)) - } Name (SUPP, 0x00) // PCI _OSC Support Field Value Name (CTRL, 0x00) // PCI _OSC Control Field Value Name (SUPC, 0x00) // CXL _OSC Support Field Value diff --git a/src/soc/intel/xeon_sp/spr/acpi/dino_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/dino_resource.asl index 606c074..fb8f811 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/dino_resource.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/dino_resource.asl @@ -5,30 +5,20 @@ #undef DEVPREFIX #define DEVPREFIX DI -#undef RESPREFIX -#define RESPREFIX DT #include "pci_resource.asl" #undef DEVPREFIX #define DEVPREFIX PM -#undef RESPREFIX -#define RESPREFIX MT #include "pci_resource.asl" #undef DEVPREFIX #define DEVPREFIX HQ -#undef RESPREFIX -#define RESPREFIX HT #include "pci_resource.asl" #undef DEVPREFIX #define DEVPREFIX PN -#undef RESPREFIX -#define RESPREFIX MU #include "pci_resource.asl" #undef DEVPREFIX #define DEVPREFIX HR -#undef RESPREFIX -#define RESPREFIX HU #include "pci_resource.asl" diff --git a/src/soc/intel/xeon_sp/spr/acpi/iiostack.asl b/src/soc/intel/xeon_sp/spr/acpi/iiostack.asl index bf70bbc..552f4c0 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/iiostack.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/iiostack.asl @@ -3,8 +3,6 @@ /* ***** PCI Stacks **** */ #undef DEVPREFIX #define DEVPREFIX PC -#undef RESPREFIX -#define RESPREFIX PT #undef STPREFIX #define STPREFIX ST @@ -39,8 +37,6 @@ /* ***** CXL Stacks **** */ #undef DEVPREFIX #define DEVPREFIX CX -#undef RESPREFIX -#define RESPREFIX CT #undef STACK #define STACK 1 diff --git a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl index a369b11..c65b699 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl @@ -22,11 +22,6 @@ { Return (\_SB.PRTID) } - External (\_SB.IIO_DEVICE_NAME(RESPREFIX, SOCKET, STACK)) - Method (_CRS, 0, NotSerialized) - { - Return (\_SB.IIO_DEVICE_NAME(RESPREFIX, SOCKET, STACK)) - } Name (SUPP, 0x00) Name (CTRL, 0x00) Name (_PXM, SOCKET) /* _PXM: Device Proximity */ diff --git a/src/soc/intel/xeon_sp/spr/acpi/ubox_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/ubox_resource.asl index 416150f..b18fbe8 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/ubox_resource.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/ubox_resource.asl @@ -5,8 +5,6 @@ #undef DEVPREFIX #define DEVPREFIX UC -#undef RESPREFIX -#define RESPREFIX UT #include "pci_resource.asl" #undef PRTID @@ -14,6 +12,4 @@ #undef DEVPREFIX #define DEVPREFIX UD -#undef RESPREFIX -#define RESPREFIX UU #include "pci_resource.asl" diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c index 137bb19..643b0c8 100644 --- a/src/soc/intel/xeon_sp/spr/soc_acpi.c +++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c @@ -62,11 +62,11 @@ Stacks 1 .. 5 (TYPE_UBOX_IIO) Scope: PC<socket><stack>, ResourceTemplate: RBRS */ - - /* Write ResourceTemplate resource name */ + /* write _CRS scope */ char tres[16]; - snprintf(tres, sizeof(tres), "PT%d%X", socket, stack); - acpigen_write_name(tres); + snprintf(tres, sizeof(tres), "\\_SB.PC%d%X", socket, stack); + acpigen_write_scope(tres); + acpigen_write_name("_CRS"); printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n", tres, socket, stack); @@ -133,6 +133,7 @@ } acpigen_write_resourcetemplate_footer(); + acpigen_pop_len(); } static void create_dsdt_iou_cxl_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled) @@ -141,10 +142,11 @@ Stacks 1 .. 5 (TYPE_UBOX_IIO) Scope: CX<socket><stack>, ResourceTemplate: RBRS */ - /* write ResourceTemplate resource name */ + /* write _CRS scope */ char tres[16]; - snprintf(tres, sizeof(tres), "CT%d%X", socket, stack); - acpigen_write_name(tres); + snprintf(tres, sizeof(tres), "\\_SB.CX%d%X", socket, stack); + acpigen_write_scope(tres); + acpigen_write_name("_CRS"); printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n", tres, socket, stack); @@ -184,6 +186,7 @@ } acpigen_write_resourcetemplate_footer(); + acpigen_pop_len(); } static void create_dsdt_dino_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled) @@ -219,32 +222,32 @@ mem64_base = ri->PciResourceMem64Base + CPM_MMIO_SIZE + HQM_MMIO_SIZE + CPM_MMIO_SIZE + HQM_MMIO_SIZE; mem64_limit = ri->PciResourceMem64Limit; - snprintf(tres, sizeof(tres), "DT%d%X", socket, stack); + snprintf(tres, sizeof(tres), "\\_SB.DI%d%X", socket, stack); } else if (rlist[i] == DSDT_CPM) { bus_base = ri->BusBase + CPM_BUS_OFFSET; bus_limit = bus_base + CPM_RESERVED_BUS; mem64_base = ri->PciResourceMem64Base; mem64_limit = mem64_base + CPM_MMIO_SIZE - 1; - snprintf(tres, sizeof(tres), "MT%d%X", socket, stack); + snprintf(tres, sizeof(tres), "\\_SB.PM%d%X", socket, stack); } else if (rlist[i] == DSDT_HQM) { bus_base = ri->BusBase + HQM_BUS_OFFSET; bus_limit = bus_base + HQM_RESERVED_BUS; mem64_base = ri->PciResourceMem64Base + CPM_MMIO_SIZE; mem64_limit = mem64_base + HQM_MMIO_SIZE - 1; - snprintf(tres, sizeof(tres), "HT%d%X", socket, stack); + snprintf(tres, sizeof(tres), "\\_SB.HQ%d%X", socket, stack); } else if (rlist[i] == DSDT_CPM1) { bus_base = ri->BusBase + CPM1_BUS_OFFSET; bus_limit = bus_base + CPM_RESERVED_BUS; mem64_base = ri->PciResourceMem64Base + CPM_MMIO_SIZE + HQM_MMIO_SIZE; mem64_limit = mem64_base + CPM_MMIO_SIZE - 1; - snprintf(tres, sizeof(tres), "MU%d%X", socket, stack); - } else { // DSDT_HQM1 + snprintf(tres, sizeof(tres), "\\_SB.PN%d%X", socket, stack); + } else { bus_base = ri->BusBase + HQM1_BUS_OFFSET; bus_limit = bus_base + HQM_RESERVED_BUS; mem64_base = ri->PciResourceMem64Base + CPM_MMIO_SIZE + HQM_MMIO_SIZE + CPM_MMIO_SIZE; mem64_limit = mem64_base + HQM_MMIO_SIZE - 1; - snprintf(tres, sizeof(tres), "HU%d%X", socket, stack); + snprintf(tres, sizeof(tres), "\\_SB.HR%d%X", socket, stack); } printk(BIOS_DEBUG, @@ -252,7 +255,8 @@ "stack: %d\n bus_base:0x%x, bus_limit:0x%x\n", tres, socket, stack, bus_base, bus_limit); - acpigen_write_name(tres); + acpigen_write_scope(tres); + acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); if (stack_enabled) { @@ -281,6 +285,7 @@ } acpigen_write_resourcetemplate_footer(); + acpigen_pop_len(); } } @@ -290,19 +295,19 @@ Stacks D .. E (TYPE_UBOX) Scope: UC/UD<socket><0..1> for UBOX[1-2], ResourceTemplate: UT/UU */ - for (int i = 0; i < 2; ++i) { char tres[16]; - /* write ResourceTemplate resource name */ + /* write _CRS scope */ if (i == 0) - snprintf(tres, sizeof(tres), "UT%d%X", socket, stack); + snprintf(tres, sizeof(tres), "\\_SB.UC%d%X", socket, stack); else - snprintf(tres, sizeof(tres), "UU%d%X", socket, stack); + snprintf(tres, sizeof(tres), "\\_SB.UD%d%X", socket, stack); printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n", tres, socket, stack); - acpigen_write_name(tres); + acpigen_write_scope(tres); + acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); if (!stack_enabled) @@ -314,6 +319,7 @@ 0x0, 1); acpigen_write_resourcetemplate_footer(); + acpigen_pop_len(); } } @@ -333,7 +339,7 @@ acpigen_write_name_integer(stack_sta, ACPI_STATUS_DEVICE_ALL_ON); } -void uncore_inject_dsdt(const struct device *device) +void uncore_fill_ssdt(const struct device *device) { bool stack_enabled; @@ -357,8 +363,6 @@ printk(BIOS_DEBUG, "%s device: %s\n", __func__, dev_path(device)); - acpigen_write_scope("\\_SB"); - /* The _CSR generation must match SPR iiostack.asl. */ const IIO_UDS *hob = get_iio_uds(); /* Iterate over CONFIG_MAX_SOCKET to keep ASL templates and DSDT injection in sync */ @@ -386,8 +390,6 @@ } } } - - acpigen_pop_len(); } /* TODO: See if we can use the common generate_p_state_entries */ diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index a69cfb2..9c18393 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -349,7 +349,7 @@ .init = mmapvtd_init, .ops_pci = &soc_pci_ops, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_inject_dsdt = uncore_inject_dsdt, + .acpi_fill_ssdt = uncore_fill_ssdt, #endif }; -- To view, visit https://review.coreboot.org/c/coreboot/+/78333?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I691d7497dceb89619652e5523a29ea30a7b0fab8 Gerrit-Change-Number: 78333 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2023