coreboot-gerrit October 2023

coreboot-gerrit@coreboot.org

1 participants
3354 discussions

[S] Change in coreboot[main]: soc/intel/xeon_sp: Scan and allocate resources on all stacks
by Arthur Heymans (Code Review) 12 Oct '23

12 Oct '23

1 0

[S] Change in coreboot[main]: device/Kconfig: Add an option to allocate above 4G by default
by Arthur Heymans (Code Review) 12 Oct '23

12 Oct '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78331?usp=email ) Change subject: device/Kconfig: Add an option to allocate above 4G by default ...................................................................... device/Kconfig: Add an option to allocate above 4G by default Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I01218a8a3efc4a5f8ba344808949ca6b8898525f --- M src/device/Kconfig M src/device/resource_allocator_v4.c 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/78331/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index 8c6c734..29d7a17 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -1004,6 +1004,15 @@ undeclared resources. EDK2 is currently reported to also have problems on some platforms, at least with Intel's IGD. +config RESOURCE_IGNORE_FLAG_IORESOURCE_ABOVE_4G + bool + default n if ARCH_X86 + default y + help + Don't limit mem resources to 4G, but to their actual limit. + This can break both coreboot and the payload if they try to + access resources above 4G in 32bit mode. + config XHCI_UTILS def_bool n help diff --git a/src/device/resource_allocator_v4.c b/src/device/resource_allocator_v4.c index c3132f4..872e788 100644 --- a/src/device/resource_allocator_v4.c +++ b/src/device/resource_allocator_v4.c @@ -84,6 +84,9 @@ static resource_t effective_limit(const struct resource *const res) { + if (CONFIG(RESOURCE_IGNORE_FLAG_IORESOURCE_ABOVE_4G)) + return res->limit; + /* Always allow bridge resources above 4G. */ if (res->flags & IORESOURCE_BRIDGE) return res->limit; -- To view, visit https://review.coreboot.org/c/coreboot/+/78331?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I01218a8a3efc4a5f8ba344808949ca6b8898525f Gerrit-Change-Number: 78331 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[main]: device/device.h: Rename busses for clarity
by Arthur Heymans (Code Review) 12 Oct '23

12 Oct '23

Attention is currently required from: Angel Pons, Boris Mittelberg, Caveh Jalali, Christian Walter, Eran Mitrani, Felix Held, Fred Reitberger, Jason Glenesk, Jason Nien, Jeff Daly, Johnny Lin, Kapil Porwal, Lance Zhao, Martin L Roth, Martin Roth, Matt DeVillier, Michał Żygowski, Nick Vaccaro, Piotr Król, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Tim Wawrzynczak, Vanessa Eusebio, Werner Zeh. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78330?usp=email ) Change subject: device/device.h: Rename busses for clarity ...................................................................... device/device.h: Rename busses for clarity This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 --- M src/acpi/acpi.c M src/acpi/device.c M src/arch/x86/mpspec.c M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/device/cardbus_device.c M src/device/device.c M src/device/device_const.c M src/device/device_util.c M src/device/i2c_bus.c M src/device/mdio.c M src/device/oprom/realmode/x86.c M src/device/oprom/realmode/x86_interrupts.c M src/device/oprom/yabel/device.c M src/device/oprom/yabel/interrupt.c M src/device/pci_device.c M src/device/pci_rom.c M src/device/pciexp_device.c M src/device/pcix_device.c M src/device/pnp_device.c M src/device/resource_allocator_v4.c M src/device/root_device.c M src/drivers/i2c/ptn3460/ptn3460.c M src/drivers/intel/dptf/dptf.c M src/drivers/intel/ish/ish.c M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/soundwire/soundwire.c M src/drivers/net/phy/m88e1512/m88e1512.c M src/drivers/net/r8168.c M src/drivers/nxp/uwb/uwb.c M src/drivers/pcie/generic/generic.c M src/drivers/spi/acpi/acpi.c M src/drivers/usb/hub/acpi.c M src/drivers/usb/pci_xhci/pci_xhci.c M src/drivers/wifi/generic/acpi.c M src/drivers/wifi/generic/smbios.c M src/drivers/wwan/fm/acpi_fm350gl.c M src/ec/google/chromeec/ec_acpi.c M src/include/device/device.h M src/include/device/pci_ops.h M src/lib/smbios.c M src/mainboard/aopen/dxplplusu/acpi_tables.c M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/google/brya/mainboard.c M src/mainboard/google/kahlee/variants/careena/mainboard.c M src/mainboard/google/kahlee/variants/treeya/audio.c M src/mainboard/google/octopus/mainboard.c M src/mainboard/google/rex/mainboard.c M src/mainboard/google/zork/variants/baseboard/ramstage_common.c M src/mainboard/ibase/mb899/mptable.c M src/mainboard/kontron/986lcd-m/mptable.c M src/mainboard/pcengines/apu2/mainboard.c M src/mainboard/roda/rk9/ti_pci7xx1.c M src/mainboard/siemens/mc_apl1/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c M src/mainboard/siemens/mc_ehl/mainboard.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/haswell/pcie.c M src/northbridge/intel/i440bx/northbridge.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/sandybridge/pcie.c M src/northbridge/intel/x4x/northbridge.c M src/soc/amd/cezanne/xhci.c M src/soc/amd/common/block/acpi/ivrs.c M src/soc/amd/common/block/data_fabric/domain.c M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/glinda/xhci.c M src/soc/amd/mendocino/xhci.c M src/soc/amd/phoenix/xhci.c M src/soc/amd/picasso/xhci.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/cavium/cn81xx/ecam0.c M src/soc/intel/apollolake/chip.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/common/block/acpi/pep.c M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/pcie/rtd3/rtd3.c M src/soc/intel/common/block/usb4/pcie.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/skylake/chip.c M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/soc_acpi.c M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/soc/intel/xeon_sp/spr/soc_acpi.c M src/soc/intel/xeon_sp/uncore.c M src/soc/intel/xeon_sp/uncore_acpi.c M src/southbridge/amd/pi/hudson/lpc.c M src/superio/common/generic.c M src/superio/common/ssdt.c M util/sconfig/main.c 98 files changed, 310 insertions(+), 316 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/78330/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 17cd24c..82846fe 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -691,7 +691,7 @@ if (device->path.type == DEVICE_PATH_PCI) { spmi->pci_device_flag = ACPI_IPMI_PCI_DEVICE_FLAG; - spmi->pci_bus = device->bus->secondary; + spmi->pci_bus = device->upstream->secondary; spmi->pci_device = device->path.pci.devfn >> 3; spmi->pci_function = device->path.pci.devfn & 0x7; } else if (type != IPMI_INTERFACE_SSIF) { diff --git a/src/acpi/device.c b/src/acpi/device.c index b76357e..36f02d1 100644 --- a/src/acpi/device.c +++ b/src/acpi/device.c @@ -80,8 +80,8 @@ return dev->ops->acpi_name(dev); /* Walk up the tree to find if any parent can identify this device */ - while (pdev->bus) { - pdev = pdev->bus->dev; + while (pdev->upstream) { + pdev = pdev->upstream->dev; if (!pdev) break; if (pdev->path.type == DEVICE_PATH_ROOT) @@ -144,8 +144,8 @@ return cur; /* Walk up the tree to the root device */ - if (dev->path.type != DEVICE_PATH_ROOT && dev->bus && dev->bus->dev) - next = acpi_device_path_fill(dev->bus->dev, buf, buf_len, cur); + if (dev->path.type != DEVICE_PATH_ROOT && dev->upstream && dev->upstream->dev) + next = acpi_device_path_fill(dev->upstream->dev, buf, buf_len, cur); if (next < 0) return next; @@ -180,10 +180,10 @@ { static char buf[DEVICE_PATH_MAX] = {}; - if (!dev || !dev->bus || !dev->bus->dev) + if (!dev || !dev->upstream || !dev->upstream->dev) return NULL; - if (acpi_device_path_fill(dev->bus->dev, buf, sizeof(buf), 0) <= 0) + if (acpi_device_path_fill(dev->upstream->dev, buf, sizeof(buf), 0) <= 0) return NULL; return buf; diff --git a/src/arch/x86/mpspec.c b/src/arch/x86/mpspec.c index 3ecb42b..d18c478 100644 --- a/src/arch/x86/mpspec.c +++ b/src/arch/x86/mpspec.c @@ -283,11 +283,11 @@ unsigned char dstirq_x[4]; - if (!dev->link_list) + if (!dev->downstream) return; - child = dev->link_list->children; - srcbus = dev->link_list->secondary; + child = dev->downstream->children; + srcbus = dev->downstream->secondary; while (child) { if (child->path.type != DEVICE_PATH_PCI) @@ -475,7 +475,7 @@ memset(buses, 0, sizeof(buses)); for (dev = all_devices; dev; dev = dev->next) { - struct bus *bus = dev->link_list; + struct bus *bus = dev->downstream; if (!bus) continue; if (bus->secondary > 255) { diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 83d847cb..86dcbea 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -449,7 +449,7 @@ static void configure_thermal_target(struct device *dev) { /* Make sure your devicetree has the cpu_cluster below chip cpu/intel/haswell! */ - struct cpu_intel_haswell_config *conf = dev->bus->dev->chip_info; + struct cpu_intel_haswell_config *conf = dev->upstream->dev->chip_info; msr_t msr; /* Set TCC activation offset if supported */ diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 3497ae0..cb74854 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -22,7 +22,7 @@ static void configure_thermal_target(struct device *dev) { - struct cpu_intel_model_2065x_config *conf = dev->bus->dev->chip_info; + struct cpu_intel_model_2065x_config *conf = dev->upstream->dev->chip_info; msr_t msr; /* Set TCC activation offset if supported */ diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 242746e..d28bf8b 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -213,7 +213,7 @@ static void configure_thermal_target(struct device *dev) { - struct cpu_intel_model_206ax_config *conf = dev->bus->dev->chip_info; + struct cpu_intel_model_206ax_config *conf = dev->upstream->dev->chip_info; msr_t msr; /* Set TCC activation offset if supported */ diff --git a/src/device/cardbus_device.c b/src/device/cardbus_device.c index 23f24dd..2eb070e 100644 --- a/src/device/cardbus_device.c +++ b/src/device/cardbus_device.c @@ -119,7 +119,7 @@ u16 ctrl; ctrl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL); - ctrl |= (dev->link_list->bridge_ctrl & ( + ctrl |= (dev->downstream->bridge_ctrl & ( PCI_BRIDGE_CTL_VGA | PCI_BRIDGE_CTL_MASTER_ABORT | PCI_BRIDGE_CTL_BUS_RESET)); diff --git a/src/device/device.c b/src/device/device.c index 6bdbccf..5fc077c 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -101,7 +101,7 @@ dev->enabled = 1; /* Add the new device to the list of children of the bus. */ - dev->bus = parent; + dev->upstream = parent; if (child) child->sibling = dev; else @@ -169,8 +169,8 @@ curdev->ops->read_resources(curdev); /* Read in the resources behind the current device's links. */ - if (curdev->link_list) - read_resources(curdev->link_list); + if (curdev->downstream) + read_resources(curdev->downstream); } post_log_clear(); printk(BIOS_SPEW, "%s %s bus %d done\n", dev_path(bus->dev), __func__, bus->secondary); @@ -199,7 +199,7 @@ continue; printk(BIOS_DEBUG, "found VGA at %s\n", dev_path(dev)); - if (dev->bus->no_vga16) { + if (dev->upstream->no_vga16) { printk(BIOS_WARNING, "A bridge on the path doesn't support 16-bit VGA decoding!"); } @@ -233,7 +233,7 @@ /* All legacy VGA cards have MEM & I/O space registers. */ vga->command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_IO); vga_pri = vga; - bus = vga->bus; + bus = vga->upstream; } /* Now walk up the bridges setting the VGA enable. */ @@ -241,7 +241,7 @@ printk(BIOS_DEBUG, "Setting PCI_BRIDGE_CTL_VGA for bridge %s\n", dev_path(bus->dev)); bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA | PCI_BRIDGE_CTL_VGA16; - bus = (bus == bus->dev->bus) ? 0 : bus->dev->bus; + bus = (bus == bus->dev->upstream) ? 0 : bus->dev->upstream; } } @@ -304,8 +304,8 @@ } for (dev = link->children; dev; dev = dev->sibling) { - if (dev->link_list) - enable_resources(dev->link_list); + if (dev->downstream) + enable_resources(dev->downstream); } post_log_clear(); } @@ -352,14 +352,14 @@ do_scan_bus = 1; while (do_scan_bus) { - struct bus *link = busdev->link_list; + struct bus *link = busdev->downstream; busdev->ops->scan_bus(busdev); do_scan_bus = 0; if (link && link->reset_needed) { if (reset_bus(link)) do_scan_bus = 1; else - busdev->bus->reset_needed = 1; + busdev->upstream->reset_needed = 1; } } @@ -457,14 +457,14 @@ /* Read the resources for the entire tree. */ printk(BIOS_INFO, "Reading resources...\n"); - read_resources(root->link_list); + read_resources(root->downstream); printk(BIOS_INFO, "Done reading resources.\n"); print_resource_tree(root, BIOS_SPEW, "After reading."); allocate_resources(root); - assign_resources(root->link_list); + assign_resources(root->downstream); printk(BIOS_INFO, "Done setting resources.\n"); print_resource_tree(root, BIOS_SPEW, "After assigning values."); @@ -482,8 +482,8 @@ printk(BIOS_INFO, "Enabling resources...\n"); /* Now enable everything. */ - if (dev_root.link_list) - enable_resources(dev_root.link_list); + if (dev_root.downstream) + enable_resources(dev_root.downstream); printk(BIOS_INFO, "done.\n"); } @@ -507,7 +507,7 @@ long init_time; if (dev->path.type == DEVICE_PATH_I2C) { - printk(BIOS_DEBUG, "smbus: %s->", dev_path(dev->bus->dev)); + printk(BIOS_DEBUG, "smbus: %s->", dev_path(dev->upstream->dev)); } printk(BIOS_DEBUG, "%s init\n", dev_path(dev)); @@ -533,8 +533,8 @@ } for (dev = link->children; dev; dev = dev->sibling) - if (dev->link_list) - init_link(dev->link_list); + if (dev->downstream) + init_link(dev->downstream); } /** @@ -551,8 +551,8 @@ init_dev(&dev_root); /* Now initialize everything. */ - if (dev_root.link_list) - init_link(dev_root.link_list); + if (dev_root.downstream) + init_link(dev_root.downstream); post_log_clear(); printk(BIOS_INFO, "Devices initialized\n"); @@ -587,8 +587,8 @@ final_dev(dev); for (dev = link->children; dev; dev = dev->sibling) - if (dev->link_list) - final_link(dev->link_list); + if (dev->downstream) + final_link(dev->downstream); } /** * Finalize all devices in the global device tree. @@ -604,7 +604,7 @@ final_dev(&dev_root); /* Now finalize everything. */ - final_link(dev_root.link_list); + final_link(dev_root.downstream); printk(BIOS_INFO, "Devices finalized\n"); } diff --git a/src/device/device_const.c b/src/device/device_const.c index a63a629..588809d 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -34,7 +34,7 @@ result = 0; for (dev = all_devices; dev; dev = dev->next) { if ((dev->path.type == DEVICE_PATH_PCI) && - (dev->bus->secondary == bus) && + (dev->upstream->secondary == bus) && (dev->path.pci.devfn == devfn)) { result = dev; break; @@ -209,7 +209,7 @@ if (nested_path_length == 1 || !child) return child; - return find_dev_nested_path(child->link_list, nested_path + 1, nested_path_length - 1); + return find_dev_nested_path(child->downstream, nested_path + 1, nested_path_length - 1); } DEVTREE_CONST struct device *pcidev_path_behind( @@ -233,8 +233,8 @@ dev = dev->next; continue; } - if (dev->bus->secondary == bus) - return pcidev_path_behind(dev->bus, devfn); + if (dev->upstream->secondary == bus) + return pcidev_path_behind(dev->upstream, devfn); dev = dev->next; } return NULL; @@ -252,7 +252,7 @@ if (!pci_domain) return NULL; - pci_root = pci_domain->link_list; + pci_root = pci_domain->downstream; return pci_root; } @@ -276,7 +276,7 @@ return NULL; } - return pcidev_path_behind(bridge->link_list, devfn); + return pcidev_path_behind(bridge->downstream, devfn); } DEVTREE_CONST struct device *pcidev_path_on_root_debug(pci_devfn_t devfn, const char *func) @@ -316,7 +316,7 @@ result = 0; for (dev = all_devices; dev; dev = dev->next) { if ((dev->path.type == DEVICE_PATH_I2C) && - (dev->bus->secondary == bus) && + (dev->upstream->secondary == bus) && (dev->path.i2c.device == addr)) { result = dev; break; diff --git a/src/device/device_util.c b/src/device/device_util.c index a0824bd..9c80616 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -97,7 +97,7 @@ case DEVICE_PATH_ROOT: break; case DEVICE_PATH_PCI: - ret |= dev->bus->secondary << 8 | dev->path.pci.devfn; + ret |= dev->upstream->secondary << 8 | dev->path.pci.devfn; break; case DEVICE_PATH_PNP: ret |= dev->path.pnp.port << 8 | dev->path.pnp.device; @@ -169,7 +169,7 @@ case DEVICE_PATH_PCI: snprintf(buffer, sizeof(buffer), "PCI: %02x:%02x.%01x", - dev->bus->secondary, + dev->upstream->secondary, PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn)); break; @@ -179,7 +179,7 @@ break; case DEVICE_PATH_I2C: snprintf(buffer, sizeof(buffer), "I2C: %02x:%02x", - dev->bus->secondary, + dev->upstream->secondary, dev->path.i2c.device); break; case DEVICE_PATH_APIC: @@ -515,9 +515,9 @@ end = resource_end(resource); buf[0] = '\0'; - if (dev->link_list && (resource->flags & IORESOURCE_PCI_BRIDGE)) { + if (dev->downstream && (resource->flags & IORESOURCE_PCI_BRIDGE)) { snprintf(buf, sizeof(buf), - "bus %02x ", dev->link_list->secondary); + "bus %02x ", dev->downstream->secondary); } printk(BIOS_DEBUG, "%s %02lx <- [0x%016llx - 0x%016llx] size 0x%08llx " "gran 0x%02x %s%s%s\n", dev_path(dev), resource->index, @@ -545,7 +545,7 @@ /* If it is a subtractive resource recurse. */ if (res->flags & IORESOURCE_SUBTRACTIVE) { - search_bus_resources(curdev->link_list, type_mask, type, + search_bus_resources(curdev->downstream, type_mask, type, search, gp); continue; } @@ -601,8 +601,8 @@ struct device *child; for (child = bus->children; child; child = child->sibling) { - if (child->link_list) - disable_children(child->link_list); + if (child->downstream) + disable_children(child->downstream); dev_set_enabled(child, 0); } } @@ -618,10 +618,10 @@ if (!dev || !dev->enabled) return 0; - if (!dev->link_list || !dev->link_list->children) + if (!dev->downstream || !dev->downstream->children) return 0; - for (child = dev->link_list->children; child; child = child->sibling) { + for (child = dev->downstream->children; child; child = child->sibling) { if (child->path.type == DEVICE_PATH_NONE) continue; if (child->enabled) @@ -643,9 +643,9 @@ indent[i] = '\0'; printk(BIOS_DEBUG, "%s%s", indent, dev_path(root)); - if (root->link_list && root->link_list->children) + if (root->downstream && root->downstream->children) printk(BIOS_DEBUG, " child on link 0 %s", - dev_path(root->link_list->children)); + dev_path(root->downstream->children)); printk(BIOS_DEBUG, "\n"); for (res = root->resource_list; res; res = res->next) { @@ -656,10 +656,10 @@ res->index); } - if (!root->link_list) + if (!root->downstream) return; - for (child = root->link_list->children; child; child = child->sibling) + for (child = root->downstream->children; child; child = child->sibling) resource_tree(child, debug_level, depth + 1); } @@ -693,10 +693,10 @@ printk(debug_level, "%s%s: enabled %d\n", depth_str, dev_path(dev), dev->enabled); - if (!dev->link_list) + if (!dev->downstream) return; - for (sibling = dev->link_list->children; sibling; sibling = sibling->sibling) + for (sibling = dev->downstream->children; sibling; sibling = sibling->sibling) show_devs_tree(sibling, debug_level, depth + 1); } @@ -874,7 +874,7 @@ bool dev_path_hotplug(const struct device *dev) { - for (dev = dev->bus->dev; dev != dev->bus->dev; dev = dev->bus->dev) { + for (dev = dev->upstream->dev; dev != dev->upstream->dev; dev = dev->upstream->dev) { if (dev->hotplug_port) return true; } @@ -893,7 +893,7 @@ bool is_cpu(const struct device *cpu) { return cpu->path.type == DEVICE_PATH_APIC && - cpu->bus->dev->path.type == DEVICE_PATH_CPU_CLUSTER; + cpu->upstream->dev->path.type == DEVICE_PATH_CPU_CLUSTER; } bool is_enabled_cpu(const struct device *cpu) @@ -913,5 +913,5 @@ bool is_pci_dev_on_bus(const struct device *pci, unsigned int bus) { - return is_pci(pci) && pci->bus->secondary == bus; + return is_pci(pci) && pci->upstream->secondary == bus; } diff --git a/src/device/i2c_bus.c b/src/device/i2c_bus.c index 361bb67..a532e4c 100644 --- a/src/device/i2c_bus.c +++ b/src/device/i2c_bus.c @@ -16,10 +16,10 @@ struct bus *i2c_link(const struct device *const dev) { - if (!dev || !dev->bus) + if (!dev || !dev->upstream) return NULL; - struct bus *link = dev->bus; + struct bus *link = dev->upstream; while (link) { struct device *const parent = link->dev; @@ -27,8 +27,8 @@ (parent->ops->ops_i2c_bus || parent->ops->ops_smbus_bus)) break; - if (parent && parent->bus && link != parent->bus) - link = parent->bus; + if (parent && parent->upstream && link != parent->upstream) + link = parent->upstream; else link = NULL; } diff --git a/src/device/mdio.c b/src/device/mdio.c index 39ac40b..89da60b 100644 --- a/src/device/mdio.c +++ b/src/device/mdio.c @@ -19,7 +19,7 @@ uint16_t mdio_read(struct device *dev, uint8_t offset) { const struct mdio_bus_operations *mdio_ops; - struct device *parent = dev->bus->dev; + struct device *parent = dev->upstream->dev; assert(dev->path.type == DEVICE_PATH_MDIO); mdio_ops = dev_get_mdio_ops(parent); @@ -30,7 +30,7 @@ void mdio_write(struct device *dev, uint8_t offset, uint16_t val) { const struct mdio_bus_operations *mdio_ops; - struct device *parent = dev->bus->dev; + struct device *parent = dev->upstream->dev; assert(dev->path.type == DEVICE_PATH_MDIO); mdio_ops = dev_get_mdio_ops(parent); diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 367614d..c3adf40 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -415,7 +415,7 @@ void run_bios(struct device *dev, unsigned long addr) { - u32 num_dev = (dev->bus->secondary << 8) | dev->path.pci.devfn; + u32 num_dev = (dev->upstream->secondary << 8) | dev->path.pci.devfn; /* Setting up required hardware. * Removing this will cause random illegal instruction exceptions diff --git a/src/device/oprom/realmode/x86_interrupts.c b/src/device/oprom/realmode/x86_interrupts.c index 945052b..71fc1d5 100644 --- a/src/device/oprom/realmode/x86_interrupts.c +++ b/src/device/oprom/realmode/x86_interrupts.c @@ -138,7 +138,7 @@ X86_EAX |= PCIBIOS_SUCCESSFUL; // busnum is an unsigned char; // devfn is an int, so we mask it off. - busdevfn = (dev->bus->secondary << 8) + busdevfn = (dev->upstream->secondary << 8) | (dev->path.pci.devfn & 0xff); printk(BIOS_DEBUG, "0x%x: return 0x%x\n", func, busdevfn); X86_EBX = busdevfn; diff --git a/src/device/oprom/yabel/device.c b/src/device/oprom/yabel/device.c index 2c98578..d1dc801 100644 --- a/src/device/oprom/yabel/device.c +++ b/src/device/oprom/yabel/device.c @@ -65,7 +65,7 @@ { int taa_index = 0; struct resource *r; - u8 bus = bios_device.dev->bus->secondary; + u8 bus = bios_device.dev->upstream->secondary; u16 devfn = bios_device.dev->path.pci.devfn; bios_device.bus = bus; diff --git a/src/device/oprom/yabel/interrupt.c b/src/device/oprom/yabel/interrupt.c index 968e471..e78a3cb 100644 --- a/src/device/oprom/yabel/interrupt.c +++ b/src/device/oprom/yabel/interrupt.c @@ -375,7 +375,7 @@ } else if (CONFIG(YABEL_PCI_ACCESS_OTHER_DEVICES)) { dev = dev_find_device(M.x86.R_DX, M.x86.R_CX, 0); if (dev != NULL) { - M.x86.R_BH = dev->bus->secondary; + M.x86.R_BH = dev->upstream->secondary; M.x86.R_BL = dev->path.pci.devfn; DEBUG_PRINTF_INTR ("%s(): function %x: PCI Find Device --> 0x%04x\n", diff --git a/src/device/pci_device.c b/src/device/pci_device.c index dcf4ce3..0df09c7 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -585,7 +585,7 @@ void pci_domain_set_resources(struct device *dev) { - assign_resources(dev->link_list); + assign_resources(dev->downstream); } static void host_bridge_resources(struct device *dev) @@ -617,14 +617,14 @@ struct device *alloc_pci_host_bridge(struct device *parent_dev, uint16_t secondary_bus) { struct device_path path = { .type = DEVICE_PATH_GENERIC }; - struct device *pci_host_dev = alloc_dev(parent_dev->link_list, &path); + struct device *pci_host_dev = alloc_dev(parent_dev->downstream, &path); pci_host_dev->ops = &host_bridge_ops; struct bus *pci_bus = calloc(1, sizeof(struct bus)); if (pci_bus == NULL) die("%s: out of memory.\n", __func__); pci_bus->secondary = secondary_bus; pci_bus->subordinate = secondary_bus; - pci_host_dev->link_list = pci_bus; + pci_host_dev->downstream = pci_bus; return pci_host_dev; } @@ -759,8 +759,8 @@ for (res = dev->resource_list; res; res = res->next) pci_set_resource(dev, res); - if (dev->link_list && dev->link_list->children) - assign_resources(dev->link_list); + if (dev->downstream && dev->downstream->children) + assign_resources(dev->downstream); /* Set a default latency timer. */ pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40); @@ -823,10 +823,10 @@ * Enable I/O in command register if there is VGA card * connected with (even it does not claim I/O resource). */ - if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) + if (dev->downstream->bridge_ctrl & PCI_BRIDGE_CTL_VGA) dev->command |= PCI_COMMAND_IO; ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); - ctrl |= dev->link_list->bridge_ctrl; + ctrl |= dev->downstream->bridge_ctrl; ctrl |= (PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR); /* Error check. */ printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); @@ -1025,7 +1025,7 @@ pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, bridge_ctrl); /* If the upstream bridge doesn't support VGA16, we don't have to check */ - bus->no_vga16 |= bus->dev->bus->no_vga16; + bus->no_vga16 |= bus->dev->upstream->no_vga16; if (bus->no_vga16) return; @@ -1250,7 +1250,7 @@ if (!dev) { struct device dummy; - dummy.bus = bus; + dummy.upstream = bus; dummy.path.type = DEVICE_PATH_PCI; dummy.path.pci.devfn = devfn; @@ -1352,7 +1352,7 @@ */ unsigned int pci_match_simple_dev(struct device *dev, pci_devfn_t sdev) { - return dev->bus->secondary == PCI_DEV2SEGBUS(sdev) && + return dev->upstream->secondary == PCI_DEV2SEGBUS(sdev) && dev->path.pci.devfn == PCI_DEV2DEVFN(sdev); } @@ -1367,14 +1367,14 @@ */ uint16_t pci_find_cap_recursive(const struct device *dev, uint16_t cap) { - assert(dev->bus); + assert(dev->upstream); uint16_t pos = pci_find_capability(dev, cap); - const struct device *bridge = dev->bus->dev; + const struct device *bridge = dev->upstream->dev; while (bridge && (bridge->path.type == DEVICE_PATH_PCI)) { - assert(bridge->bus); + assert(bridge->upstream); if (!pci_find_capability(bridge, cap)) return 0; - bridge = bridge->bus->dev; + bridge = bridge->upstream->dev; } return pos; } @@ -1579,7 +1579,7 @@ static void pci_bridge_route(struct bus *link, scan_state state) { struct device *dev = link->dev; - struct bus *parent = dev->bus; + struct bus *parent = dev->upstream; uint8_t primary, secondary, subordinate; if (state == PCI_ROUTE_SCAN) { @@ -1657,17 +1657,17 @@ printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(dev)); - if (dev->link_list == NULL) { + if (dev->downstream == NULL) { struct bus *link; link = malloc(sizeof(*link)); if (link == NULL) die("Couldn't allocate a link!\n"); memset(link, 0, sizeof(*link)); link->dev = dev; - dev->link_list = link; + dev->downstream = link; } - bus = dev->link_list; + bus = dev->downstream; pci_bridge_vga_compat(bus); @@ -1702,7 +1702,7 @@ */ void pci_host_bridge_scan_bus(struct device *dev) { - struct bus *link = dev->link_list; + struct bus *link = dev->downstream; pci_scan_bus(link, PCI_DEVFN(0, 0), 0xff); } @@ -1765,8 +1765,8 @@ /* While our current device has parent devices */ child = dev; - for (parent = child->bus->dev; parent; parent = parent->bus->dev) { - parent_bus = parent->bus->secondary; + for (parent = child->upstream->dev; parent; parent = parent->upstream->dev) { + parent_bus = parent->upstream->secondary; parent_devfn = parent->path.pci.devfn; child_devfn = child->path.pci.devfn; @@ -1830,7 +1830,7 @@ if (!(dev->enabled && (dev->path.type == DEVICE_PATH_PCI))) return -1; - bus = dev->bus->secondary; + bus = dev->upstream->secondary; devfn = dev->path.pci.devfn; /* Get and validate the interrupt pin used. Only 1-4 are allowed */ diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 46bf114..c4c74c0 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -241,7 +241,7 @@ header->DeviceID = device->device; header->VendorID = device->vendor; - header->PCIBus = device->bus->secondary; + header->PCIBus = device->upstream->secondary; header->PCIFunction = PCI_FUNC(device->path.pci.devfn); header->PCIDevice = PCI_SLOT(device->path.pci.devfn); header->ImageLength = rom->size * 512; diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index ab8430f..969dbb00 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -302,7 +302,7 @@ struct device *parent = NULL; unsigned int parent_cap = 0; if (!dev->ops->ops_pci || !dev->ops->ops_pci->get_ltr_max_latencies) { - parent = dev->bus->dev; + parent = dev->upstream->dev; if (parent->path.type != DEVICE_PATH_PCI) return; parent_cap = pci_find_capability(parent, PCI_CAP_ID_PCIE); @@ -319,9 +319,9 @@ do { if (dev->ops->ops_pci && dev->ops->ops_pci->get_ltr_max_latencies) break; - if (dev->bus->dev == dev || dev->bus->dev->path.type != DEVICE_PATH_PCI) + if (dev->upstream->dev == dev || dev->upstream->dev->path.type != DEVICE_PATH_PCI) return false; - dev = dev->bus->dev; + dev = dev->upstream->dev; } while (true); dev->ops->ops_pci->get_ltr_max_latencies(max_snoop, max_nosnoop); @@ -627,7 +627,7 @@ static void pciexp_tune_dev(struct device *dev) { - struct device *root = dev->bus->dev; + struct device *root = dev->upstream->dev; unsigned int root_cap, cap; cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); @@ -752,7 +752,7 @@ /* Add dummy slot to preserve resources, must happen after bus scan */ struct device *dummy; struct device_path dummy_path = { .type = DEVICE_PATH_NONE }; - dummy = alloc_dev(dev->link_list, &dummy_path); + dummy = alloc_dev(dev->downstream, &dummy_path); dummy->ops = &pciexp_hotplug_dummy_ops; } diff --git a/src/device/pcix_device.c b/src/device/pcix_device.c index 5593357f..1b00aa9 100644 --- a/src/device/pcix_device.c +++ b/src/device/pcix_device.c @@ -107,10 +107,10 @@ sstatus = pci_read_config16(dev, pos + PCI_X_SEC_STATUS); if (PCI_X_SSTATUS_MFREQ(sstatus) != PCI_X_SSTATUS_CONVENTIONAL_PCI) - pcix_tune_bus(dev->link_list); + pcix_tune_bus(dev->downstream); /* Print the PCI-X bus speed. */ - printk(BIOS_DEBUG, "PCI: %02x: %s\n", dev->link_list->secondary, + printk(BIOS_DEBUG, "PCI: %02x: %s\n", dev->downstream->secondary, pcix_speed(sstatus)); } diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index dad791c..f799530 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -384,7 +384,7 @@ continue; path.pnp.device = info[i].function; - dev = alloc_find_dev(base_dev->bus, &path); + dev = alloc_find_dev(base_dev->upstream, &path); /* Don't initialize a device multiple times. */ if (dev->ops) diff --git a/src/device/resource_allocator_v4.c b/src/device/resource_allocator_v4.c index 96d4488..c3132f4 100644 --- a/src/device/resource_allocator_v4.c +++ b/src/device/resource_allocator_v4.c @@ -78,7 +78,7 @@ static bool dev_has_children(const struct device *dev) { - const struct bus *bus = dev->link_list; + const struct bus *bus = dev->downstream; return bus && bus->children; } @@ -119,7 +119,7 @@ resource_t base; const unsigned long type_mask = IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH; const unsigned long type_match = bridge_res->flags & type_mask; - struct bus *bus = bridge->link_list; + struct bus *bus = bridge->downstream; child_res = NULL; @@ -205,7 +205,7 @@ { const struct device *child; struct resource *res; - struct bus *bus = bridge->link_list; + struct bus *bus = bridge->downstream; const unsigned long type_mask = IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH; for (res = bridge->resource_list; res; res = res->next) { @@ -253,10 +253,10 @@ const struct device *child; const int print_depth = 1; - if (domain->link_list == NULL) + if (domain->downstream == NULL) return; - for (child = domain->link_list->children; child; child = child->sibling) { + for (child = domain->downstream->children; child; child = child->sibling) { /* Skip if this is not a bridge or has no children under it. */ if (!dev_has_children(child)) @@ -296,7 +296,7 @@ memranges_create_hole(ranges, res->base, res->size); } - bus = dev->link_list; + bus = dev->downstream; if (bus == NULL) return; @@ -396,7 +396,7 @@ setup_resource_ranges(domain, type, &ranges); - while ((dev = largest_resource(domain->link_list, &res, type_mask, type))) { + while ((dev = largest_resource(domain->downstream, &res, type_mask, type))) { if (!res->size) continue; @@ -438,7 +438,7 @@ { const unsigned long type_mask = IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH | IORESOURCE_FIXED; - struct bus *const bus = bridge->link_list; + struct bus *const bus = bridge->downstream; struct resource *res; struct device *child; @@ -493,7 +493,7 @@ allocate_toplevel_resources(domain, IORESOURCE_MEM); struct device *child; - for (child = domain->link_list->children; child; child = child->sibling) { + for (child = domain->downstream->children; child; child = child->sibling) { if (!dev_has_children(child)) continue; @@ -550,10 +550,10 @@ { const struct device *child; - if ((root == NULL) || (root->link_list == NULL)) + if ((root == NULL) || (root->downstream == NULL)) return; - for (child = root->link_list->children; child; child = child->sibling) { + for (child = root->downstream->children; child; child = child->sibling) { if (child->path.type != DEVICE_PATH_DOMAIN) continue; diff --git a/src/device/root_device.c b/src/device/root_device.c index cf5ffb7..d2f7e62 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -39,7 +39,7 @@ { struct device *child; - for (child = bus->link_list->children; child; child = child->sibling) + for (child = bus->downstream->children; child; child = child->sibling) enable_static_device(child); } @@ -50,12 +50,12 @@ printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); - if (bus->link_list) { - bus->link_list->secondary = ++bus_max; + if (bus->downstream) { + bus->downstream->secondary = ++bus_max; - for (child = bus->link_list->children; child; child = child->sibling) { + for (child = bus->downstream->children; child; child = child->sibling) { enable_static_device(child); - printk(BIOS_DEBUG, "bus: %s->", dev_path(child->bus->dev)); + printk(BIOS_DEBUG, "bus: %s->", dev_path(child->upstream->dev)); } } @@ -75,7 +75,7 @@ * given by the mainboard's `devicetree.cb`. * * First, all direct descendants of the given device are - * enabled. Then, link_list buses are scanned. + * enabled. Then, downstream buses are scanned. */ void scan_static_bus(struct device *bus) { @@ -83,8 +83,8 @@ enable_static_devices(bus); - if (bus->link_list) - scan_bridges(bus->link_list); + if (dev_root.downstream) + scan_bridges(bus->downstream); printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); } diff --git a/src/drivers/i2c/ptn3460/ptn3460.c b/src/drivers/i2c/ptn3460/ptn3460.c index 7dee222..086be9a 100644 --- a/src/drivers/i2c/ptn3460/ptn3460.c +++ b/src/drivers/i2c/ptn3460/ptn3460.c @@ -172,8 +172,8 @@ return; } /* Initialize the I2C controller before it is used. */ - if (ptn_dev->bus && ptn_dev->bus->dev->ops && ptn_dev->bus->dev->ops->init) - ptn_dev->bus->dev->ops->init(ptn_dev->bus->dev); + if (ptn_dev->upstream && ptn_dev->upstream->dev->ops && ptn_dev->upstream->dev->ops->init) + ptn_dev->upstream->dev->ops->init(ptn_dev->upstream->dev); ptn3460_init(ptn_dev); } diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index 71a4ec3..9228584 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -503,7 +503,7 @@ enum dptf_participant p; /* The CPU device gets an _ADR that matches the ACPI PCI address for 00:04.00 */ - parent = dev && dev->bus ? dev->bus->dev : NULL; + parent = dev && dev->upstream ? dev->upstream->dev : NULL; if (!parent || parent->path.type != DEVICE_PATH_PCI) { printk(BIOS_ERR, "%s: DPTF objects must live under 00:04.0 PCI device\n", __func__); diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c index d1b85f5..5f73c35 100644 --- a/src/drivers/intel/ish/ish.c +++ b/src/drivers/intel/ish/ish.c @@ -12,7 +12,7 @@ static void ish_fill_ssdt_generator(const struct device *dev) { struct drivers_intel_ish_config *config = dev->chip_info; - struct device *root = dev->bus->dev; + struct device *root = dev->upstream->dev; struct acpi_dp *dsd; if (!config) diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index 00c85a7..2da98fc 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -199,7 +199,7 @@ static uint32_t address_for_dev_type(const struct device *dev, uint8_t dev_type) { struct drivers_intel_mipi_camera_config *config = dev->chip_info; - uint16_t i2c_bus = dev->bus ? dev->bus->secondary : 0xFFFF; + uint16_t i2c_bus = dev->upstream ? dev->upstream->secondary : 0xFFFF; uint16_t i2c_addr; switch (dev_type) { @@ -416,7 +416,7 @@ .type = DEVICE_PATH_I2C, .i2c.device = config->vcm_address, }; - struct device *vcm_dev = find_dev_path(dev->bus, &path); + struct device *vcm_dev = find_dev_path(dev->upstream, &path); struct drivers_intel_mipi_camera_config *vcm_config; vcm_config = vcm_dev ? vcm_dev->chip_info : NULL; @@ -927,7 +927,7 @@ const struct device *pdev; if (config->has_power_resource) { - pdev = dev->bus->dev; + pdev = dev->upstream->dev; if (!pdev || !pdev->enabled) return; @@ -951,7 +951,7 @@ write_i2c_camera_device(dev, scope); break; case DEVICE_PATH_GENERIC: - pdev = dev->bus->dev; + pdev = dev->upstream->dev; scope = acpi_device_scope(pdev); if (!scope) return; diff --git a/src/drivers/intel/soundwire/soundwire.c b/src/drivers/intel/soundwire/soundwire.c index c7e84a5..1028176 100644 --- a/src/drivers/intel/soundwire/soundwire.c +++ b/src/drivers/intel/soundwire/soundwire.c @@ -21,7 +21,7 @@ { struct device *child; - for (child = dev->link_list->children; child; child = child->sibling) { + for (child = dev->downstream->children; child; child = child->sibling) { if (child->enabled && child->path.type == DEVICE_PATH_GENERIC && child->path.generic.id == link) return true; diff --git a/src/drivers/net/phy/m88e1512/m88e1512.c b/src/drivers/net/phy/m88e1512/m88e1512.c index 2e8994c..5c6ed9a 100644 --- a/src/drivers/net/phy/m88e1512/m88e1512.c +++ b/src/drivers/net/phy/m88e1512/m88e1512.c @@ -21,10 +21,10 @@ if (config->downshift_cnt) { if (config->downshift_cnt > DOWNSHIFT_CNT_MAX) { printk(BIOS_INFO, "%s: Downshift counter for %s is too large.\n", - dev_path(dev->bus->dev), dev->chip_ops->name); + dev_path(dev->upstream->dev), dev->chip_ops->name); } else { printk(BIOS_DEBUG, "%s: Enable downshift after %d attempts for %s.\n", - dev_path(dev->bus->dev), config->downshift_cnt, + dev_path(dev->upstream->dev), config->downshift_cnt, dev->chip_ops->name); reg = mdio_read(dev, COPPER_SPEC_CTRL_REG_1); @@ -42,7 +42,7 @@ /* Configure LEDs if requested. */ if (config->configure_leds) { printk(BIOS_DEBUG, "%s: Set a customized LED mode for %s.\n", - dev_path(dev->bus->dev), dev->chip_ops->name); + dev_path(dev->upstream->dev), dev->chip_ops->name); /* Select page 3 to access LED function control register. */ switch_page(dev, 3); @@ -57,7 +57,7 @@ /* INTn can be routed to LED[2] pin. */ if (config->enable_int) { printk(BIOS_DEBUG, "%s: INTn is routed to LED[2] pin %s.\n", - dev_path(dev->bus->dev), dev->chip_ops->name); + dev_path(dev->upstream->dev), dev->chip_ops->name); /* Select page 3 to access LED function control register. */ switch_page(dev, 3); @@ -70,7 +70,7 @@ /* Set RGMII output impedance manually. */ if (config->force_mos) { printk(BIOS_DEBUG, "%s: Set RGMII driver strength manually for %s.\n", - dev_path(dev->bus->dev), dev->chip_ops->name); + dev_path(dev->upstream->dev), dev->chip_ops->name); /* Select page 2 to access RGMII output impedance calibration override register. */ diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index f21edd0..27296a7 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -364,7 +364,7 @@ static void r8168_net_fill_ssdt(const struct device *dev) { struct drivers_net_config *config = dev->chip_info; - const char *path = acpi_device_path(dev->bus->dev); + const char *path = acpi_device_path(dev->upstream->dev); u32 address; if (!path || !config) diff --git a/src/drivers/nxp/uwb/uwb.c b/src/drivers/nxp/uwb/uwb.c index 978edeb..dc9da5b 100644 --- a/src/drivers/nxp/uwb/uwb.c +++ b/src/drivers/nxp/uwb/uwb.c @@ -15,10 +15,10 @@ struct device *spi_dev; struct device_operations *ops; - if (!dev->bus || !dev->bus->dev) + if (!dev->upstream || !dev->bus->dev) return -1; - spi_dev = dev->bus->dev; + spi_dev = dev->upstream->dev; ops = spi_dev->ops; if (ops && ops->ops_spi_bus && ops->ops_spi_bus->dev_to_bus) diff --git a/src/drivers/pcie/generic/generic.c b/src/drivers/pcie/generic/generic.c index 1873e65..daa2959 100644 --- a/src/drivers/pcie/generic/generic.c +++ b/src/drivers/pcie/generic/generic.c @@ -27,13 +27,13 @@ pci_rom_ssdt(dev); config = dev->chip_info; - if (!config || !dev->bus || !dev->bus->dev) + if (!config || !dev->upstream || !dev->upstream->dev) return; const char *scope; const char *name; - scope = acpi_device_path(dev->bus->dev); + scope = acpi_device_path(dev->upstream->dev); name = acpi_device_name(dev); acpigen_write_scope(scope); diff --git a/src/drivers/spi/acpi/acpi.c b/src/drivers/spi/acpi/acpi.c index 9b6fd80..f39893b 100644 --- a/src/drivers/spi/acpi/acpi.c +++ b/src/drivers/spi/acpi/acpi.c @@ -15,10 +15,10 @@ struct device *spi_dev; struct device_operations *ops; - if (!dev->bus || !dev->bus->dev) + if (!dev->upstream || !dev->upstream->dev) return -1; - spi_dev = dev->bus->dev; + spi_dev = dev->upstream->dev; ops = spi_dev->ops; if (ops && ops->ops_spi_bus && diff --git a/src/drivers/usb/hub/acpi.c b/src/drivers/usb/hub/acpi.c index 10e38fb6..2f3e249 100644 --- a/src/drivers/usb/hub/acpi.c +++ b/src/drivers/usb/hub/acpi.c @@ -41,7 +41,7 @@ struct device *port = NULL; unsigned int child_count = 0; - while ((port = dev_bus_each_child(dev->link_list, port)) != NULL) { + while ((port = dev_bus_each_child(dev->downstream, port)) != NULL) { if (child_count++ >= config->port_count) { printk(BIOS_WARNING, "%s cannot be added. Port Count limit reached.\n", dev_name(port)); diff --git a/src/drivers/usb/pci_xhci/pci_xhci.c b/src/drivers/usb/pci_xhci/pci_xhci.c index 6d022d1..8e9d566 100644 --- a/src/drivers/usb/pci_xhci/pci_xhci.c +++ b/src/drivers/usb/pci_xhci/pci_xhci.c @@ -76,7 +76,7 @@ if (dev->path.type == DEVICE_PATH_ROOT) return NULL; - dev = dev->bus->dev; + dev = dev->upstream->dev; } return dev; diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index 3996739..6bd53d6 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -610,7 +610,7 @@ if (!dev) return; - path = acpi_device_path(dev->bus->dev); + path = acpi_device_path(dev->upstream->dev); if (!path) return; diff --git a/src/drivers/wifi/generic/smbios.c b/src/drivers/wifi/generic/smbios.c index 82c96a5..e6ccd5d 100644 --- a/src/drivers/wifi/generic/smbios.c +++ b/src/drivers/wifi/generic/smbios.c @@ -38,5 +38,5 @@ int smbios_write_wifi_cnvi(struct device *dev, int *handle, unsigned long *current) { - return smbios_write_wifi_pcie(dev->bus->dev, handle, current); + return smbios_write_wifi_pcie(dev->upstream->dev, handle, current); } diff --git a/src/drivers/wwan/fm/acpi_fm350gl.c b/src/drivers/wwan/fm/acpi_fm350gl.c index 139fd15..8d79517 100644 --- a/src/drivers/wwan/fm/acpi_fm350gl.c +++ b/src/drivers/wwan/fm/acpi_fm350gl.c @@ -266,7 +266,7 @@ static void wwan_fm350gl_acpi_fill_ssdt(const struct device *dev) { const struct drivers_wwan_fm_config *config = config_of(dev); - const struct device *parent = dev->bus->dev; + const struct device *parent = dev->upstream->dev; const char *scope = acpi_device_path(parent); const struct soc_intel_common_block_pcie_rtd3_config *rtd3_config; diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 3367cfa..cf29636 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -273,7 +273,7 @@ path.type = DEVICE_PATH_GENERIC; path.generic.id = 0; path.generic.subid = 0; - ec = alloc_find_dev(dev->bus, &path); + ec = alloc_find_dev(dev->upstream, &path); ec->ops = &ec_ops; if (CONFIG(DRIVERS_INTEL_DPTF)) diff --git a/src/include/device/device.h b/src/include/device/device.h index a55ca82..6f1d13e 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -98,8 +98,8 @@ */ struct device { - DEVTREE_CONST struct bus *bus; /* bus this device is on, for bridge - * devices, it is the up stream bus */ + DEVTREE_CONST struct bus *upstream; + DEVTREE_CONST struct bus *downstream; DEVTREE_CONST struct device *sibling; /* next device on this bus */ @@ -127,11 +127,6 @@ /* Base registers for this device. I/O, MEM and Expansion ROM */ DEVTREE_CONST struct resource *resource_list; - /* links are (downstream) buses attached to the device, usually a leaf - * device with no children has 0 buses attached and a bridge has 1 bus - */ - DEVTREE_CONST struct bus *link_list; - #if !DEVTREE_EARLY struct device_operations *ops; struct chip_operations *chip_ops; @@ -228,14 +223,14 @@ static inline void mp_cpu_bus_init(struct device *dev) { /* Make sure the cpu cluster has a downstream bus for LAPICs to be allocated. */ - if (!dev->link_list) { + if (!dev->downstream) { struct bus *bus = calloc(1, sizeof(struct bus)); if (!bus) die("Couldn't allocate downstream bus!\n"); - dev->link_list = bus; + dev->downstream = bus; } - mp_init_cpus(dev->link_list); + mp_init_cpus(dev->downstream); } /* Debug functions */ diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index b5d4e23..a70b3af 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -12,7 +12,7 @@ static __always_inline pci_devfn_t pcidev_bdf(const struct device *dev) { - return (dev->path.pci.devfn << 12) | (dev->bus->secondary << 20); + return (dev->path.pci.devfn << 12) | (dev->upstream->secondary << 20); } static __always_inline pci_devfn_t pcidev_assert(const struct device *dev) diff --git a/src/lib/smbios.c b/src/lib/smbios.c index deee193b..6121679 100644 --- a/src/lib/smbios.c +++ b/src/lib/smbios.c @@ -1114,7 +1114,7 @@ name, // name instance_id, // inst 0, // segment - dev->bus->secondary, //bus + dev->upstream->secondary, //bus PCI_SLOT(dev->path.pci.devfn), // device PCI_FUNC(dev->path.pci.devfn), // func device_type); @@ -1166,7 +1166,7 @@ 0, 1, 0, - dev->bus->secondary, + dev->upstream->secondary, dev->path.pci.devfn); } diff --git a/src/mainboard/aopen/dxplplusu/acpi_tables.c b/src/mainboard/aopen/dxplplusu/acpi_tables.c index e22b454..114068f 100644 --- a/src/mainboard/aopen/dxplplusu/acpi_tables.c +++ b/src/mainboard/aopen/dxplplusu/acpi_tables.c @@ -11,7 +11,7 @@ bdev = pcidev_on_root(2, 0); /* P64H2 Bus B IOAPIC */ if (bdev) - dev = pcidev_path_behind(bdev->link_list, PCI_DEVFN(28, 0)); + dev = pcidev_path_behind(bdev->downstream, PCI_DEVFN(28, 0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, res->base); @@ -19,7 +19,7 @@ /* P64H2 Bus A IOAPIC */ if (bdev) - dev = pcidev_path_behind(bdev->link_list, PCI_DEVFN(30, 0)); + dev = pcidev_path_behind(bdev->downstream, PCI_DEVFN(30, 0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, res->base); diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 5fe12e7..75268bd 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -39,7 +39,7 @@ static void cpu_pci_domain_set_resources(struct device *dev) { - assign_resources(dev->link_list); + assign_resources(dev->downstream); } static void cpu_pci_domain_read_resources(struct device *dev) diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c index aa332cd..9cf56b2 100644 --- a/src/mainboard/google/brya/mainboard.c +++ b/src/mainboard/google/brya/mainboard.c @@ -106,7 +106,7 @@ static void mainboard_generate_wwan_shutdown(const struct device *dev) { const struct drivers_wwan_fm_config *config = config_of(dev); - const struct device *parent = dev->bus->dev; + const struct device *parent = dev->upstream->dev; if (!config) return; @@ -126,7 +126,7 @@ static void mainboard_generate_dgpu_shutdown(const struct device *dev) { /* Call `_OFF` from the Power Resource associated with the dGPU's PEG port. */ - const struct device *parent = dev->bus->dev; + const struct device *parent = dev->upstream->dev; if (parent) acpigen_emit_namestring(acpi_device_path_join(parent, "PGPR._OFF")); diff --git a/src/mainboard/google/kahlee/variants/careena/mainboard.c b/src/mainboard/google/kahlee/variants/careena/mainboard.c index 937a411..c54b530 100644 --- a/src/mainboard/google/kahlee/variants/careena/mainboard.c +++ b/src/mainboard/google/kahlee/variants/careena/mainboard.c @@ -26,7 +26,7 @@ if (mmio_dev == NULL) return; - while ((child = dev_bus_each_child(mmio_dev->link_list, child)) != NULL) { + while ((child = dev_bus_each_child(mmio_dev->downstream, child)) != NULL) { if (child->path.type != DEVICE_PATH_I2C) continue; if (child->path.i2c.device != 0x1a) diff --git a/src/mainboard/google/kahlee/variants/treeya/audio.c b/src/mainboard/google/kahlee/variants/treeya/audio.c index ac7f7a2..e7a20ea 100644 --- a/src/mainboard/google/kahlee/variants/treeya/audio.c +++ b/src/mainboard/google/kahlee/variants/treeya/audio.c @@ -25,7 +25,7 @@ } } while (mmio_dev->path.mmio.addr != APU_I2C0_BASE); - while ((child = dev_bus_each_child(mmio_dev->link_list, child)) != NULL) { + while ((child = dev_bus_each_child(mmio_dev->downstream, child)) != NULL) { if (child->path.type != DEVICE_PATH_I2C) continue; if (child->path.i2c.device != RT58_I2C_ADDRESS) diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index 92b1074..3392a3c 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -179,7 +179,7 @@ { struct device *audio_dev = NULL; struct bus *audio_i2c_bus = - pcidev_path_on_root(PCH_DEVFN_I2C5)->link_list; + pcidev_path_on_root(PCH_DEVFN_I2C5)->downstream; enum ssfc_audio_codec codec = ssfc_get_audio_codec(); while ((audio_dev = dev_bus_each_child(audio_i2c_bus, audio_dev))) { diff --git a/src/mainboard/google/rex/mainboard.c b/src/mainboard/google/rex/mainboard.c index 619ca71..24356f3 100644 --- a/src/mainboard/google/rex/mainboard.c +++ b/src/mainboard/google/rex/mainboard.c @@ -82,7 +82,7 @@ static void mainboard_generate_wwan_shutdown(const struct device *dev) { const struct drivers_wwan_fm_config *config = config_of(dev); - const struct device *parent = dev->bus->dev; + const struct device *parent = dev->upstream->dev; if (!config) return; diff --git a/src/mainboard/google/zork/variants/baseboard/ramstage_common.c b/src/mainboard/google/zork/variants/baseboard/ramstage_common.c index 3c203f5..a544548 100644 --- a/src/mainboard/google/zork/variants/baseboard/ramstage_common.c +++ b/src/mainboard/google/zork/variants/baseboard/ramstage_common.c @@ -115,7 +115,7 @@ if (variant_uses_v3_6_schematics()) return; - while ((child = dev_bus_each_child(mmio_dev->link_list, child)) != NULL) { + while ((child = dev_bus_each_child(mmio_dev->downstream, child)) != NULL) { struct drivers_i2c_generic_config *cfg; if (child->chip_ops == &drivers_i2c_generic_ops) { diff --git a/src/mainboard/ibase/mb899/mptable.c b/src/mainboard/ibase/mb899/mptable.c index 4ec578a..a9ad7c7 100644 --- a/src/mainboard/ibase/mb899/mptable.c +++ b/src/mainboard/ibase/mb899/mptable.c @@ -19,7 +19,7 @@ firewire = dev_find_device(0x104c, 0x8023, 0); if (firewire) { - firewire_bus = firewire->bus->secondary; + firewire_bus = firewire->upstream->secondary; printk(BIOS_SPEW, "Firewire device is on bus %x\n", firewire_bus); } @@ -30,7 +30,7 @@ if (!riser) riser = dev_find_device(0x3388, 0x0022, 0); if (riser) { - riser_bus = riser->link_list->secondary; + riser_bus = riser->downstream->secondary; printk(BIOS_SPEW, "Riser bus is %x\n", riser_bus); } diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c index 605b8d7..b0bfbe7 100644 --- a/src/mainboard/kontron/986lcd-m/mptable.c +++ b/src/mainboard/kontron/986lcd-m/mptable.c @@ -18,7 +18,7 @@ firewire = dev_find_device(0x104c, 0x8023, 0); if (firewire) { - firewire_bus = firewire->bus->secondary; + firewire_bus = firewire->upstream->secondary; } /* If a riser card is used, this riser is detected on bus 4, so its secondary bus is the */ @@ -27,7 +27,7 @@ if (!riser) riser = dev_find_device(0x3388, 0x0022, 0); if (riser) { - riser_bus = riser->link_list->secondary; + riser_bus = riser->downstream->secondary; } mptable_write_buses(mc, NULL, &isa_bus); diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index ab9156f..38e052c 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -275,7 +275,7 @@ dev = pcidev_on_root(2, 2); if (dev) - dev = pcidev_path_behind(dev->link_list, PCI_DEVFN(0, 0)); + dev = pcidev_path_behind(dev->downstream, PCI_DEVFN(0, 0)); if (!dev) return serial; diff --git a/src/mainboard/roda/rk9/ti_pci7xx1.c b/src/mainboard/roda/rk9/ti_pci7xx1.c index a980f5c..7c5a808 100644 --- a/src/mainboard/roda/rk9/ti_pci7xx1.c +++ b/src/mainboard/roda/rk9/ti_pci7xx1.c @@ -19,7 +19,7 @@ u16 gcr = pci_read_config16(dev, 0x86); for (fn = 5; fn > 0; --fn) { const struct device *const d = - pcidev_path_behind(dev->bus, PCI_DEVFN(slot, fn)); + pcidev_path_behind(dev->upstream, PCI_DEVFN(slot, fn)); if (!d || d->enabled) continue; printk(BIOS_DEBUG, "%s: Hiding function #%d.\n", __func__, fn); diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index 0593797..51427be 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -55,7 +55,7 @@ */ enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[MAC_ADDR_LEN]) { - struct bus *parent = dev->bus; + struct bus *parent = dev->upstream; uint8_t buf[16], mapping[16], i = 0, chain_len = 0; memset(buf, 0, sizeof(buf)); @@ -64,10 +64,10 @@ /* The first entry in the tree is the device itself. */ buf[0] = dev->path.pci.devfn; chain_len = 1; - for (i = 1; i < MAX_PATH_DEPTH && parent->dev->bus->subordinate; i++) { + for (i = 1; i < MAX_PATH_DEPTH && parent->dev->upstream->subordinate; i++) { buf[i] = parent->dev->path.pci.devfn; chain_len++; - parent = parent->dev->bus; + parent = parent->dev->upstream; } if (i == MAX_PATH_DEPTH) { /* The path is deeper than MAX_PATH_DEPTH devices, error. */ diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c index b61f32d..c6beff6 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c @@ -41,7 +41,7 @@ /* Disable clock outputs 0 and 2-4 (CLKOUT) for upstream XIO2001 PCIe to PCI Bridge. */ - struct device *parent = dev->bus->dev; + struct device *parent = dev->upstream->dev; if (parent && parent->device == PCI_DID_TI_XIO2001) pci_write_config8(parent, 0xd8, 0x1d); } @@ -50,7 +50,7 @@ mainboard. */ dev = dev_find_device(PCI_VID_SIEMENS, 0x403f, 0); if (dev) { - struct device *parent = dev->bus->dev; + struct device *parent = dev->upstream->dev; if (parent && parent->device == PCI_DID_TI_XIO2001) pci_write_config8(parent, 0xd8, 0x3c); } diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c index 8eedce6..eda4b1b 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c @@ -51,7 +51,7 @@ /* Disable clock outputs 0-3 (CLKOUT) for upstream XIO2001 PCIe to PCI Bridge. */ - struct device *parent = dev->bus->dev; + struct device *parent = dev->upstream->dev; if (parent && parent->device == PCI_DID_TI_XIO2001) pci_write_config8(parent, 0xd8, 0x0f); } @@ -60,7 +60,7 @@ mainboard. */ dev = dev_find_device(PCI_VID_SIEMENS, 0x403f, 0); if (dev) { - struct device *parent = dev->bus->dev; + struct device *parent = dev->upstream->dev; if (parent && parent->device == PCI_DID_TI_XIO2001) pci_write_config8(parent, 0xd8, 0x3e); } diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c index 1856a35..a5fe3d7 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c @@ -41,7 +41,7 @@ /* Disable clock outputs 0-3 (CLKOUT) for upstream XIO2001 PCIe to PCI Bridge. */ - struct device *parent = dev->bus->dev; + struct device *parent = dev->upstream->dev; if (parent && parent->device == PCI_DID_TI_XIO2001) pci_write_config8(parent, 0xd8, 0x0F); } @@ -50,7 +50,7 @@ mainboard. */ dev = dev_find_device(PCI_VID_SIEMENS, 0x403f, 0); if (dev) { - struct device *parent = dev->bus->dev; + struct device *parent = dev->upstream->dev; if (parent && parent->device == PCI_DID_TI_XIO2001) pci_write_config8(parent, 0xd8, 0x3c); } diff --git a/src/mainboard/siemens/mc_ehl/mainboard.c b/src/mainboard/siemens/mc_ehl/mainboard.c index 7aa0d86..ac16346 100644 --- a/src/mainboard/siemens/mc_ehl/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/mainboard.c @@ -42,7 +42,7 @@ */ enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[MAC_ADDR_LEN]) { - struct bus *parent = dev->bus; + struct bus *parent = dev->upstream; uint8_t buf[16], mapping[16], i = 0, chain_len = 0; memset(buf, 0, sizeof(buf)); @@ -51,10 +51,10 @@ /* The first entry in the tree is the device itself. */ buf[0] = dev->path.pci.devfn; chain_len = 1; - for (i = 1; i < MAX_PATH_DEPTH && parent->dev->bus->subordinate; i++) { + for (i = 1; i < MAX_PATH_DEPTH && parent->dev->upstream->subordinate; i++) { buf[i] = parent->dev->path.pci.devfn; chain_len++; - parent = parent->dev->bus; + parent = parent->dev->upstream; } if (i == MAX_PATH_DEPTH) { /* The path is deeper than MAX_PATH_DEPTH devices, error. */ diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index f471a00..b35fca9 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -177,10 +177,9 @@ sblink = (pci_read_config32(get_mc_dev(), 0x64) >> 8) & 7; // don't forget sublink1 - if (!dev->link_list) + if (!dev->downstream) return; - - if (!(dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA)) + if (!(dev->downstream->bridge_ctrl & PCI_BRIDGE_CTL_VGA)) return; printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink); @@ -299,7 +298,7 @@ ivrs_ivhd_generic_t *ivhd_entry = (ivrs_ivhd_generic_t *)*current; ivhd_entry->type = type; - ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); + ivhd_entry->dev_id = dev->path.pci.devfn | (dev->upstream->secondary << 8); ivhd_entry->dte_setting = data; *current += sizeof(ivrs_ivhd_generic_t); } else if (type == IVHD_DEV_8_BYTE_ALIAS_SELECT) { @@ -308,12 +307,12 @@ ivrs_ivhd_alias_t *ivhd_entry = (ivrs_ivhd_alias_t *)*current; ivhd_entry->type = type; - ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); + ivhd_entry->dev_id = dev->path.pci.devfn | (dev->upstream->secondary << 8); ivhd_entry->dte_setting = data; ivhd_entry->reserved1 = 0; ivhd_entry->reserved2 = 0; ivhd_entry->source_dev_id = parent->path.pci.devfn | - (parent->bus->secondary << 8); + (parent->upstream->secondary << 8); *current += sizeof(ivrs_ivhd_alias_t); } @@ -356,7 +355,7 @@ if (dev->path.type == DEVICE_PATH_PCI) { - if ((dev->bus->secondary == 0x0) && + if ((dev->upstream->secondary == 0x0) && (dev->path.pci.devfn == 0x0)) *root_level = depth; @@ -366,8 +365,8 @@ } } - if (dev->link_list) { - for (sibling = dev->link_list->children; sibling; sibling = sibling->sibling) + if (dev->downstream) { + for (sibling = dev->downstream->children; sibling; sibling = sibling->sibling) add_ivhd_device_entries(dev, sibling, depth + 1, depth, root_level, current, ivhd_length); } @@ -403,7 +402,7 @@ ivhd_11->flags = ivrs_agesa->ivhd.flags & 0x3f; ivhd_11->length = sizeof(struct acpi_ivrs_ivhd_11); /* BDF <bus>:00.2 */ - ivhd_11->device_id = 0x02 | (nb_dev->bus->secondary << 8); + ivhd_11->device_id = 0x02 | (nb_dev->upstream->secondary << 8); /* PCI Capability block 0x40 (type 0xf, "Secure device") */ ivhd_11->capability_offset = 0x40; ivhd_11->iommu_base_low = ivrs_agesa->ivhd.iommu_base_low; @@ -471,7 +470,7 @@ ivrs->ivhd.flags = ivrs_agesa->ivhd.flags; ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd); /* BDF <bus>:00.2 */ - ivrs->ivhd.device_id = 0x02 | (nb_dev->bus->secondary << 8); + ivrs->ivhd.device_id = 0x02 | (nb_dev->upstream->secondary << 8); /* PCI Capability block 0x40 (type 0xf, "Secure device") */ ivrs->ivhd.capability_offset = 0x40; ivrs->ivhd.iommu_base_low = ivrs_agesa->ivhd.iommu_base_low; diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 65a0212..e2bb24c 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -52,7 +52,7 @@ static void mch_domain_set_resources(struct device *dev) { - assign_resources(dev->link_list); + assign_resources(dev->downstream); } struct device_operations e7505_pci_domain_ops = { diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 4bddf20..c888546 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -122,7 +122,7 @@ report_resource_stored(dev, resource, ""); } - assign_resources(dev->link_list); + assign_resources(dev->downstream); } static void mch_domain_init(struct device *dev) diff --git a/src/northbridge/intel/haswell/pcie.c b/src/northbridge/intel/haswell/pcie.c index 7fe57e9..4eeaa3f 100644 --- a/src/northbridge/intel/haswell/pcie.c +++ b/src/northbridge/intel/haswell/pcie.c @@ -20,8 +20,8 @@ if (dev->path.type != DEVICE_PATH_PCI) return NULL; - assert(dev->bus); - if (dev->bus->secondary == 0) + assert(dev->upstream); + if (dev->upstream->secondary == 0) switch (dev->path.pci.devfn) { case PCI_DEVFN(1, 0): return "PEGP"; @@ -31,12 +31,12 @@ return "PEG2"; }; - struct device *const port = dev->bus->dev; + struct device *const port = dev->upstream->dev; assert(port); - assert(port->bus); + assert(port->upstream); if (dev->path.pci.devfn == PCI_DEVFN(0, 0) && - port->bus->secondary == 0 && + port->upstream->secondary == 0 && (port->path.pci.devfn == PCI_DEVFN(1, 0) || port->path.pci.devfn == PCI_DEVFN(1, 1) || port->path.pci.devfn == PCI_DEVFN(1, 2))) diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index 0670f72..cd0a570 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -34,8 +34,8 @@ pci_domain_read_resources(dev); - pci_tolm = find_pci_tolm(dev->link_list); - mc_dev = dev->link_list->children; + pci_tolm = find_pci_tolm(dev->downstream); + mc_dev = dev->downstream->children; if (mc_dev) { unsigned long tomk, tolmk; int idx; diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 1dfcc40..da0e4dd 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -26,7 +26,7 @@ /* Can we find out how much memory we can use at most * this way? */ - pci_tolm = find_pci_tolm(dev->link_list); + pci_tolm = find_pci_tolm(dev->downstream); printk(BIOS_DEBUG, "pci_tolm: 0x%x\n", pci_tolm); tolud = pci_read_config8(d0f0, TOLUD) << 24; @@ -65,7 +65,7 @@ for (res = dev->resource_list; res; res = res->next) report_resource_stored(dev, res, ""); - assign_resources(dev->link_list); + assign_resources(dev->downstream); } static const char *northbridge_acpi_name(const struct device *dev) diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index a23a0d5..dc7dd3d 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -108,7 +108,7 @@ for (res = dev->resource_list; res; res = res->next) report_resource_stored(dev, res, ""); - assign_resources(dev->link_list); + assign_resources(dev->downstream); } static void mch_domain_init(struct device *dev) diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c index ec737a2..94c3717 100644 --- a/src/northbridge/intel/sandybridge/pcie.c +++ b/src/northbridge/intel/sandybridge/pcie.c @@ -14,8 +14,8 @@ if (dev->path.type != DEVICE_PATH_PCI) return NULL; - assert(dev->bus); - if (dev->bus->secondary == 0) + assert(dev->upstream); + if (dev->upstream->secondary == 0) switch (dev->path.pci.devfn) { case PCI_DEVFN(1, 0): return "PEGP"; @@ -27,12 +27,12 @@ return "PEG6"; }; - struct device *const port = dev->bus->dev; + struct device *const port = dev->upstream->dev; assert(port); - assert(port->bus); + assert(port->upstream); if (dev->path.pci.devfn == PCI_DEVFN(0, 0) && - port->bus->secondary == 0 && + port->upstream->secondary == 0 && (port->path.pci.devfn == PCI_DEVFN(1, 0) || port->path.pci.devfn == PCI_DEVFN(1, 1) || port->path.pci.devfn == PCI_DEVFN(1, 2) || diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 12a7a40..1f8b6c0 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -72,7 +72,7 @@ for (res = dev->resource_list; res; res = res->next) report_resource_stored(dev, res, ""); - assign_resources(dev->link_list); + assign_resources(dev->downstream); } static void mch_domain_init(struct device *dev) diff --git a/src/soc/amd/cezanne/xhci.c b/src/soc/amd/cezanne/xhci.c index b0205c6..fc1c119 100644 --- a/src/soc/amd/cezanne/xhci.c +++ b/src/soc/amd/cezanne/xhci.c @@ -26,10 +26,10 @@ enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe) { - if (dev->bus->dev->path.type != DEVICE_PATH_PCI) + if (dev->upstream->dev->path.type != DEVICE_PATH_PCI) return CB_ERR_ARG; - if (dev->bus->dev->path.pci.devfn != PCIE_ABC_A_DEVFN) + if (dev->upstream->dev->path.pci.devfn != PCIE_ABC_A_DEVFN) return CB_ERR_ARG; if (dev->path.type != DEVICE_PATH_PCI) diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index 03e1fae..aaebedc 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -98,7 +98,7 @@ memset(ivhd_entry, 0, sizeof(*ivhd_entry)); ivhd_entry->type = type; - ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); + ivhd_entry->dev_id = dev->path.pci.devfn | (dev->upstream->secondary << 8); ivhd_entry->dte_setting = data; *current += sizeof(ivrs_ivhd_generic_t); } else if (type == IVHD_DEV_8_BYTE_ALIAS_SELECT) { @@ -106,12 +106,12 @@ memset(ivhd_entry, 0, sizeof(*ivhd_entry)); ivhd_entry->type = type; - ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); + ivhd_entry->dev_id = dev->path.pci.devfn | (dev->upstream->secondary << 8); ivhd_entry->dte_setting = data; ivhd_entry->reserved1 = 0; ivhd_entry->reserved2 = 0; ivhd_entry->source_dev_id = parent->path.pci.devfn | - (parent->bus->secondary << 8); + (parent->upstream->secondary << 8); *current += sizeof(ivrs_ivhd_alias_t); } @@ -147,7 +147,7 @@ return; if (dev->path.type == DEVICE_PATH_PCI) { - if ((dev->bus->secondary == nb_bus) && + if ((dev->upstream->secondary == nb_bus) && (dev->path.pci.devfn == 0x0)) *root_level = depth; @@ -156,9 +156,9 @@ ivrs_add_device_or_bridge(parent, dev, current); } - if (!dev->link_list) + if (!dev->downstream) return; - for (sibling = dev->link_list->children; sibling; sibling = sibling->sibling) + for (sibling = dev->downstream->children; sibling; sibling = sibling->sibling) add_ivhd_device_entries(dev, sibling, depth + 1, depth, root_level, current, nb_bus); } @@ -175,21 +175,21 @@ * Add all possible PCI devices in the domain that can generate transactions * processed by IOMMU. Start with device <bus>:01.0 */ - current = ivhd_dev_range(current, PCI_DEVFN(0, 3) | (dev->link_list->secondary << 8), - 0xff | (dev->link_list->subordinate << 8), 0); + current = ivhd_dev_range(current, PCI_DEVFN(0, 3) | (dev->downstream->secondary << 8), + 0xff | (dev->downstream->subordinate << 8), 0); add_ivhd_device_entries(NULL, dev, 0, -1, &root_level, - &current, dev->link_list->secondary); + &current, dev->downstream->secondary); res = probe_resource(dev, IOMMU_IOAPIC_IDX); if (res) { /* Describe IOAPIC associated with the IOMMU */ current = acpi_fill_ivrs_ioapic(current, (u8 *)(uintptr_t)res->base, - PCI_DEVFN(0, 1) | (dev->link_list->secondary << 8), 0); + PCI_DEVFN(0, 1) | (dev->downstream->secondary << 8), 0); } /* If the domain has secondary bus as zero then associate HPET & FCH IOAPIC */ - if (dev->link_list->secondary == 0) { + if (dev->downstream->secondary == 0) { /* Describe HPET */ current = ivhd_describe_hpet(current, 0x00, SMBUS_DEVFN); /* Describe FCH IOAPICs */ @@ -214,7 +214,7 @@ ivhd_40->flags = ivhd->flags & 0x3f; ivhd_40->length = sizeof(struct acpi_ivrs_ivhd_40); /* BDF <bus>:00.2 */ - ivhd_40->device_id = 0x02 | (nb_dev->bus->secondary << 8); + ivhd_40->device_id = 0x02 | (nb_dev->upstream->secondary << 8); ivhd_40->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID); ivhd_40->iommu_base_low = ivhd->iommu_base_low; ivhd_40->iommu_base_high = ivhd->iommu_base_high; @@ -232,9 +232,9 @@ /* Now repeat all the device entries from type 10h */ current_backup = current; - current = acpi_ivhd_misc(current, nb_dev->bus->dev); + current = acpi_ivhd_misc(current, nb_dev->upstream->dev); - if (nb_dev->bus->secondary == 0) { + if (nb_dev->upstream->secondary == 0) { /* Describe EMMC */ if (CONFIG(SOC_AMD_COMMON_BLOCK_EMMC)) { /* PCI_DEVFN(0x13, 1) doesn't exist in the hardware, but it's what the @@ -271,7 +271,7 @@ ivhd_11->flags = ivhd->flags & 0x3f; ivhd_11->length = sizeof(struct acpi_ivrs_ivhd_11); /* BDF <bus>:00.2 */ - ivhd_11->device_id = 0x02 | (nb_dev->bus->secondary << 8); + ivhd_11->device_id = 0x02 | (nb_dev->upstream->secondary << 8); ivhd_11->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID); ivhd_11->iommu_base_low = ivhd->iommu_base_low; ivhd_11->iommu_base_high = ivhd->iommu_base_high; @@ -291,7 +291,7 @@ /* Now repeat all the device entries from type 10h */ current_backup = current; - current = acpi_ivhd_misc(current, nb_dev->bus->dev); + current = acpi_ivhd_misc(current, nb_dev->upstream->dev); ivhd_11->length += (current - current_backup); return acpi_fill_ivrs40(current, ivhd, nb_dev, iommu_dev); @@ -319,8 +319,8 @@ while ((dev = dev_find_path(dev, DEVICE_PATH_DOMAIN)) != NULL) { - nb_dev = pcidev_path_behind(dev->link_list, PCI_DEVFN(0, 0)); - iommu_dev = pcidev_path_behind(dev->link_list, PCI_DEVFN(0, 2)); + nb_dev = pcidev_path_behind(dev->downstream, PCI_DEVFN(0, 0)); + iommu_dev = pcidev_path_behind(dev->downstream, PCI_DEVFN(0, 2)); if (!nb_dev) { printk(BIOS_WARNING, "%s: Northbridge device not present!\n", __func__); printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__); @@ -336,7 +336,7 @@ ivhd->length = sizeof(struct acpi_ivrs_ivhd); /* BDF <bus>:00.2 */ - ivhd->device_id = 0x02 | (nb_dev->bus->secondary << 8); + ivhd->device_id = 0x02 | (nb_dev->upstream->secondary << 8); ivhd->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID); ivhd->iommu_base_low = pci_read_config32(iommu_dev, IOMMU_CAP_BASE_LO) & 0xffffc000; ivhd->iommu_base_high = pci_read_config32(iommu_dev, IOMMU_CAP_BASE_HI); diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c index 4ec52fc..e8c93bb 100644 --- a/src/soc/amd/common/block/data_fabric/domain.c +++ b/src/soc/amd/common/block/data_fabric/domain.c @@ -27,11 +27,11 @@ limit = MIN(limit, CONFIG_ECAM_MMCONF_BUS_NUMBER - 1); /* Set bus first number of PCI root */ - domain->link_list->secondary = bus; + domain->downstream->secondary = bus; /* subordinate needs to be the same as secondary before pci_host_bridge_scan_bus call. */ - domain->link_list->subordinate = bus; + domain->downstream->subordinate = bus; /* Tell allocator about maximum PCI bus number in domain */ - domain->link_list->max_subordinate = limit; + domain->downstream->max_subordinate = limit; pci_host_bridge_scan_bus(domain); } @@ -241,11 +241,11 @@ /* PCI bus number range in domain */ printk(BIOS_DEBUG, "%s _CRS: adding busses [%x-%x]\n", acpi_device_name(domain), - domain->link_list->secondary, domain->link_list->max_subordinate); - acpigen_resource_producer_bus_number(domain->link_list->secondary, - domain->link_list->max_subordinate); + domain->downstream->secondary, domain->downstream->max_subordinate); + acpigen_resource_producer_bus_number(domain->downstream->secondary, + domain->downstream->max_subordinate); - if (domain->link_list->secondary == 0) { + if (domain->downstream->secondary == 0) { /* ACPI 6.4.2.5 I/O Port Descriptor */ acpigen_write_io16(PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_LAST_PORT, 1, PCI_IO_CONFIG_PORT_COUNT, 1); @@ -273,7 +273,7 @@ } } - if (domain->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + if (domain->downstream->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { printk(BIOS_DEBUG, "%s _CRS: adding VGA resource\n", acpi_device_name(domain)); acpigen_resource_producer_mmio(VGA_MMIO_BASE, VGA_MMIO_LIMIT, MEM_RSRC_FLAG_MEM_READ_WRITE | MEM_RSRC_FLAG_MEM_ATTR_CACHE); @@ -281,7 +281,7 @@ acpigen_write_resourcetemplate_footer(); - acpigen_write_BBN(domain->link_list->secondary); + acpigen_write_BBN(domain->downstream->secondary); /* Scope */ acpigen_pop_len(); diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index ca881a2..5c9addf 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -281,10 +281,10 @@ { struct device *child; - if (!dev->link_list) + if (!dev->downstream) return; - for (child = dev->link_list->children; child; child = child->sibling) { + for (child = dev->downstream->children; child; child = child->sibling) { if (!child->enabled) continue; if (child->path.type != DEVICE_PATH_PNP) diff --git a/src/soc/amd/glinda/xhci.c b/src/soc/amd/glinda/xhci.c index dad5593..74e8816 100644 --- a/src/soc/amd/glinda/xhci.c +++ b/src/soc/amd/glinda/xhci.c @@ -34,13 +34,13 @@ enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe) { - if (dev->bus->dev->path.type != DEVICE_PATH_PCI) + if (dev->upstream->dev->path.type != DEVICE_PATH_PCI) return CB_ERR_ARG; if (dev->path.type != DEVICE_PATH_PCI) return CB_ERR_ARG; - if (dev->bus->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) { + if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) { if (dev->path.pci.devfn == XHCI0_DEVFN) { *gpe = xhci_sci_sources[0].gpe; return CB_SUCCESS; @@ -48,7 +48,7 @@ *gpe = xhci_sci_sources[1].gpe; return CB_SUCCESS; } - } else if (dev->bus->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) { + } else if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) { if (dev->path.pci.devfn == XHCI2_DEVFN && dev->device == PCI_DID_AMD_FAM17H_MODELA0H_XHCI2) { *gpe = xhci_sci_sources[2].gpe; diff --git a/src/soc/amd/mendocino/xhci.c b/src/soc/amd/mendocino/xhci.c index e564991..8f46374 100644 --- a/src/soc/amd/mendocino/xhci.c +++ b/src/soc/amd/mendocino/xhci.c @@ -35,13 +35,13 @@ enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe) { - if (dev->bus->dev->path.type != DEVICE_PATH_PCI) + if (dev->upstream->dev->path.type != DEVICE_PATH_PCI) return CB_ERR_ARG; if (dev->path.type != DEVICE_PATH_PCI) return CB_ERR_ARG; - if (dev->bus->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) { + if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) { if (dev->path.pci.devfn == XHCI0_DEVFN) { *gpe = xhci_sci_sources[0].gpe; return CB_SUCCESS; @@ -49,7 +49,7 @@ *gpe = xhci_sci_sources[1].gpe; return CB_SUCCESS; } - } else if (dev->bus->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) { + } else if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) { if (dev->path.pci.devfn == XHCI2_DEVFN && dev->device == PCI_DID_AMD_FAM17H_MODELA0H_XHCI2) { *gpe = xhci_sci_sources[2].gpe; diff --git a/src/soc/amd/phoenix/xhci.c b/src/soc/amd/phoenix/xhci.c index 99033f9..79d4d07 100644 --- a/src/soc/amd/phoenix/xhci.c +++ b/src/soc/amd/phoenix/xhci.c @@ -39,13 +39,13 @@ enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe) { - if (dev->bus->dev->path.type != DEVICE_PATH_PCI) + if (dev->upstream->dev->path.type != DEVICE_PATH_PCI) return CB_ERR_ARG; if (dev->path.type != DEVICE_PATH_PCI) return CB_ERR_ARG; - if (dev->bus->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) { + if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) { if (dev->path.pci.devfn == XHCI0_DEVFN) { *gpe = xhci_sci_sources[0].gpe; return CB_SUCCESS; @@ -55,7 +55,7 @@ } } - if (dev->bus->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) { + if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) { if (dev->path.pci.devfn == USB4_XHCI0_DEVFN) { *gpe = xhci_sci_sources[2].gpe; return CB_SUCCESS; diff --git a/src/soc/amd/picasso/xhci.c b/src/soc/amd/picasso/xhci.c index 84b3a2b..a238916 100644 --- a/src/soc/amd/picasso/xhci.c +++ b/src/soc/amd/picasso/xhci.c @@ -26,10 +26,10 @@ enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe) { - if (dev->bus->dev->path.type != DEVICE_PATH_PCI) + if (dev->upstream->dev->path.type != DEVICE_PATH_PCI) return CB_ERR_ARG; - if (dev->bus->dev->path.pci.devfn != PCIE_GPP_A_DEVFN) + if (dev->upstream->dev->path.pci.devfn != PCIE_GPP_A_DEVFN) return CB_ERR_ARG; if (dev->path.type != DEVICE_PATH_PCI) diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 66ebd2a..43b5501 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -127,9 +127,9 @@ { /* find out which link the VGA card is connected, * we only deal with the 'first' vga card */ - if (!dev->link_list) + if (!dev->downstream) return; - if (!(dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA)) + if (!(dev->downstream->bridge_ctrl & PCI_BRIDGE_CTL_VGA)) return; printk(BIOS_DEBUG, "VGA: %s has VGA device\n", dev_path(dev)); @@ -148,8 +148,8 @@ for (res = dev->resource_list ; res ; res = res->next) set_resource(dev, res, 0); - if (dev->link_list && dev->link_list->children) - assign_resources(dev->link_list); + if (dev->downstream && dev->downstream->children) + assign_resources(dev->downstream); } static void northbridge_init(struct device *dev) diff --git a/src/soc/cavium/cn81xx/ecam0.c b/src/soc/cavium/cn81xx/ecam0.c index d02e884..ff3e709 100644 --- a/src/soc/cavium/cn81xx/ecam0.c +++ b/src/soc/cavium/cn81xx/ecam0.c @@ -226,12 +226,12 @@ * Search for missing devices on BUS 1. * Only required for ARI capability programming. */ - ecam0_fix_missing_devices(bridge->link_list); + ecam0_fix_missing_devices(bridge->downstream); /* Program secure ARI capability on bus 1 */ child_last = NULL; for (i = 0; i <= PCI_DEVFN(0x1f, 7); i++) { - child = pcidev_path_behind(bridge->link_list, i); + child = pcidev_path_behind(bridge->downstream, i); if (!child || !child->enabled) continue; @@ -250,7 +250,7 @@ /* Program insecure ARI capability on bus 1 */ child_last = NULL; for (i = 0; i <= PCI_DEVFN(0x1f, 7); i++) { - child = pcidev_path_behind(bridge->link_list, i); + child = pcidev_path_behind(bridge->downstream, i); if (!child) continue; config = child->chip_info; @@ -281,7 +281,7 @@ /* Enable / disable devices and functions on bus 1 */ for (i = 0; i <= PCI_DEVFN(0x1f, 7); i++) { - child = pcidev_path_behind(bridge->link_list, i); + child = pcidev_path_behind(bridge->downstream, i); config = child ? child->chip_info : NULL; if (child && child->enabled && ((config && !config->secure) || !config)) @@ -293,7 +293,7 @@ /* Apply IRQ on PCI devices */ /* UUA */ for (i = 0; i < 4; i++) { - child = pcidev_path_behind(bridge->link_list, + child = pcidev_path_behind(bridge->downstream, PCI_DEVFN(8, i)); if (!child) continue; diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 07c2637..61052dd 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -478,7 +478,7 @@ return; } /* Only disable bus 0 devices. */ - for (dev = dev->bus->children; dev; dev = dev->sibling) { + for (dev = dev->upstream->children; dev; dev = dev->sibling) { if (!dev->enabled) disable_dev(dev, silconfig); } diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index a0df97c..2e37280 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -117,7 +117,7 @@ continue; current_bdf = irq_dev->path.pci.devfn | - irq_dev->bus->secondary << 8; + irq_dev->upstream->secondary << 8; /* * Step 1: Get the INT_PIN and device structure to look for @@ -132,7 +132,7 @@ original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); parent_bdf = targ_dev->path.pci.devfn - | targ_dev->bus->secondary << 8; + | targ_dev->upstream->secondary << 8; device_num = PCI_SLOT(parent_bdf); if (ir->pcidev[device_num] == 0) { diff --git a/src/soc/intel/common/block/acpi/pep.c b/src/soc/intel/common/block/acpi/pep.c index 5e03345..c024b42 100644 --- a/src/soc/intel/common/block/acpi/pep.c +++ b/src/soc/intel/common/block/acpi/pep.c @@ -144,7 +144,7 @@ case DEVICE_PATH_PCI: /* skip external buses*/ - if ((dev->bus->secondary != 0) || (!states_arr)) + if ((dev->upstream->secondary != 0) || (!states_arr)) return ACPI_DEVICE_SLEEP_NONE; for (size_t i = 0; i < size; i++) if (states_arr[i].pci_dev == dev->path.pci.devfn) diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 283a07e..326727f 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -102,10 +102,10 @@ { struct device *child; - if (!dev->link_list) + if (!dev->downstream) return; - for (child = dev->link_list->children; child; child = child->sibling) + for (child = dev->downstream->children; child; child = child->sibling) pch_lpc_loop_resources(child); } diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c index abd7e466..76d9718 100644 --- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -140,7 +140,7 @@ enum pcie_rp_type rp_type, const struct device *dev) { - const struct device *parent = dev->bus->dev; + const struct device *parent = dev->upstream->dev; acpigen_write_method_serialized("_ON", 0); @@ -224,7 +224,7 @@ const struct device *dev) { - const struct device *parent = dev->bus->dev; + const struct device *parent = dev->upstream->dev; acpigen_write_method_serialized("_OFF", 0); @@ -385,7 +385,7 @@ const struct soc_intel_common_block_pcie_rtd3_config *config = config_of(dev); static const char *const power_res_states[] = {"_PR0"}; - const struct device *parent = dev->bus->dev; + const struct device *parent = dev->upstream->dev; const char *scope = acpi_device_path(parent); const struct opregion opregion = OPREGION("PXCS", PCI_CONFIG, 0, 0xff); const struct fieldlist fieldlist[] = { diff --git a/src/soc/intel/common/block/usb4/pcie.c b/src/soc/intel/common/block/usb4/pcie.c index 0139647..5afe9af 100644 --- a/src/soc/intel/common/block/usb4/pcie.c +++ b/src/soc/intel/common/block/usb4/pcie.c @@ -19,7 +19,7 @@ int port_id; /* Get parent PCI device */ - parent = dev->bus->dev; + parent = dev->upstream->dev; if (!parent) { printk(BIOS_ERR, "%s: Unable to find parent device\n", __func__); return; diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 9cc4211..5c0df54 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -92,8 +92,8 @@ return; } - while ((hub = dev_bus_each_child(xhci->link_list, hub)) != NULL) { - while ((port = dev_bus_each_child(hub->link_list, port)) != NULL) { + while ((hub = dev_bus_each_child(xhci->downstream, hub)) != NULL) { + while ((port = dev_bus_each_child(hub->downstream, port)) != NULL) { enable = true; config = config_of(port); if (config->type == UPC_TYPE_INTERNAL) { diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 7ebca1e..ae923d7 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -275,7 +275,7 @@ /* Swizzle this device if needed */ config = targ_dev->chip_info; - parent_bdf = targ_dev->path.pci.devfn | targ_dev->bus->secondary << 8; + parent_bdf = targ_dev->path.pci.devfn | targ_dev->upstream->secondary << 8; if (is_dnv_swizzled_rp(parent_bdf) && irq_dev != targ_dev) { swiz_int_pin = dnv_get_swizzled_pin(config, parent_bdf, new_int_pin); printk(BIOS_DEBUG, "%s: dnv swizzle %s from %c to %c\n", __func__, @@ -387,7 +387,7 @@ int_line = dnv_get_int_line(irq_dev); printk(BIOS_DEBUG, "%s: %02x:%02x.%d pin %d int line %d\n", __func__, - irq_dev->bus->secondary, devfn >> 3, devfn & 0x7, int_pin, int_line); + irq_dev->upstream->secondary, devfn >> 3, devfn & 0x7, int_pin, int_line); pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); } diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 5ec9cf4..cdc8acf 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -758,7 +758,7 @@ for (dev = all_devices; dev; dev = dev->next) { if (!(is_dev_enabled(dev) && dev->path.type == DEVICE_PATH_PCI && - dev->bus->secondary == 0)) + dev->upstream->secondary == 0)) continue; if (dev->path.pci.devfn == PCI_DEVFN_ROOT) { diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 8df1ad3..93a85da 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -94,7 +94,7 @@ return NULL; /* Match functions 0 and 1 for possible GPUs on a secondary bus */ - if (dev->bus && dev->bus->secondary > 0) { + if (dev->upstream && dev->upstream->secondary > 0) { switch (PCI_FUNC(dev->path.pci.devfn)) { case 0: return "DEV0"; case 1: return "DEV1"; diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index 12add8e..8e4533e 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -61,19 +61,19 @@ void iio_pci_domain_scan_bus(struct device *dev) { const STACK_RES *sr = domain_to_stack_res(dev); - if (!dev->link_list) { - dev->link_list = calloc(1, sizeof(struct bus)); - if (!dev->link_list) + if (!dev->downstream) { + dev->downstream = calloc(1, sizeof(struct bus)); + if (!dev->downstream) die("%s: out of memory.\n", __func__); } - struct bus *bus = dev->link_list; + struct bus *bus = dev->downstream; bus->secondary = sr->BusBase; bus->subordinate = sr->BusBase; bus->max_subordinate = sr->BusLimit; printk(BIOS_SPEW, "Scanning IIO stack %d: busses %x-%x\n", dev->path.domain.domain, - dev->link_list->secondary, dev->link_list->max_subordinate); + dev->downstream->secondary, dev->downstream->max_subordinate); pci_host_bridge_scan_bus(dev); } @@ -86,7 +86,7 @@ bus->secondary = sr->BusBase; bus->subordinate = sr->BusBase; bus->max_subordinate = sr->BusLimit; - dev->link_list = bus; + dev->downstream = bus; /* Add host_bridge devices for each PCI BUS */ for (int i = sr->BusBase; i <= sr->BusLimit; i++) { @@ -96,7 +96,7 @@ dev->path.domain.domain, i); struct device *host_bridge = alloc_pci_host_bridge(dev, i); /* We only expect bridges on IIO stacks so set this to secondary */ - host_bridge->link_list->max_subordinate = i; + host_bridge->downstream->max_subordinate = i; } } @@ -127,7 +127,7 @@ struct device_path path; path.type = DEVICE_PATH_DOMAIN; path.domain.domain = s * MAX_IIO_STACK + x; - struct device *iio_domain = alloc_dev(dev->bus, &path); + struct device *iio_domain = alloc_dev(dev->upstream, &path); if (iio_domain == NULL) die("%s: out of memory.\n", __func__); iio_domain->ops = is_iio_stack_res(ri) ? &iiostack_pci_domain_ops : &non_iiostack_pci_domain_ops; diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index 52afe45..b43ecb2 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -46,7 +46,7 @@ struct iiostack_resource stack_info = {0}; /* Only add RTxx entries once. */ - if (device->bus->secondary != 0) + if (device->upstream->secondary != 0) return; get_iiostack_info(&stack_info); diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 35e3ea1..9c02161 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -59,7 +59,7 @@ const IIO_UDS *hob = get_iio_uds(); /* Only add RTxx entries once. */ - if (device->bus->secondary != 0) + if (device->upstream->secondary != 0) return; acpigen_write_scope("\\_SB"); diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c index 193b859..137bb19 100644 --- a/src/soc/intel/xeon_sp/spr/soc_acpi.c +++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c @@ -338,7 +338,7 @@ bool stack_enabled; /* Only add RTxx entries once. */ - if (device->bus->secondary != 0) + if (device->upstream->secondary != 0) return; /* @@ -501,7 +501,7 @@ for (cpu = all_devices; cpu; cpu = cpu->next) { if ((cpu->path.type != DEVICE_PATH_APIC) - || (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { + || (cpu->upstream->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { continue; } if (!cpu->enabled) diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 66f63d5..a69cfb2 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -192,7 +192,7 @@ struct range_entry fsp_mem; /* Only add dram resources once. */ - if (dev->bus->secondary != 0) + if (dev->upstream->secondary != 0) return; /* Read in the MAP registers and report their values. */ diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index e2b47329..75b281b 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -225,7 +225,7 @@ uint32_t pcie_seg, bool is_atsr, bool *first) { - const uint32_t bus = bridge_dev->bus->secondary; + const uint32_t bus = bridge_dev->upstream->secondary; const uint32_t dev = PCI_SLOT(bridge_dev->path.pci.devfn); const uint32_t func = PCI_FUNC(bridge_dev->path.pci.devfn); diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 7246fe1..d5193c2 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -171,8 +171,8 @@ reg_var[0] = pci_read_config16(dev, 0x64); struct device *child; - if (dev->link_list) { - for (child = dev->link_list->children; child; child = child->sibling) { + if (dev->downstream) { + for (child = dev->downstream->children; child; child = child->sibling) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; for (res = child->resource_list; res; res = res->next) { diff --git a/src/superio/common/generic.c b/src/superio/common/generic.c index c690340..e4e2042 100644 --- a/src/superio/common/generic.c +++ b/src/superio/common/generic.c @@ -13,8 +13,8 @@ if (!dev) return; - if (dev->link_list) - assign_resources(dev->link_list); + if (dev->downstream) + assign_resources(dev->downstream); for (res = dev->resource_list; res; res = res->next) { if (!(res->flags & IORESOURCE_ASSIGNED)) @@ -159,8 +159,8 @@ acpigen_write_acquire(mutex, 0xffff); /* Pick one of the children as the generic SIO doesn't have config mode */ - if (dev->link_list && dev->link_list->children) - pnp_ssdt_enter_conf_mode(dev->link_list->children, "^INDX", "^DATA"); + if (dev->downstream && dev->downstream->children) + pnp_ssdt_enter_conf_mode(dev->downstream->children, "^INDX", "^DATA"); /* Backup LDN */ acpigen_write_store(); @@ -178,8 +178,8 @@ acpigen_emit_namestring("^LDN"); /* Pick one of the children as the generic SIO doesn't have config mode */ - if (dev->link_list && dev->link_list->children) - pnp_ssdt_exit_conf_mode(dev->link_list->children, "^INDX", "^DATA"); + if (dev->downstream && dev->downstream->children) + pnp_ssdt_exit_conf_mode(dev->downstream->children, "^INDX", "^DATA"); acpigen_write_release(mutex); } diff --git a/src/superio/common/ssdt.c b/src/superio/common/ssdt.c index 47fbf0c..fd55792 100644 --- a/src/superio/common/ssdt.c +++ b/src/superio/common/ssdt.c @@ -161,7 +161,7 @@ void superio_common_fill_ssdt_generator(const struct device *dev) { - if (!dev || !dev->bus || !dev->bus->dev) { + if (!dev || !dev->upstream || !dev->upstream->dev) { printk(BIOS_CRIT, "BUG: Invalid argument in %s!\n", __func__); return; } @@ -174,11 +174,11 @@ /* Validate devicetree settings */ bool bug = false; - if (dev->bus->dev->path.type != DEVICE_PATH_PNP) { + if (dev->upstream->dev->path.type != DEVICE_PATH_PNP) { bug = true; printk(BIOS_CRIT, "BUG: Parent of device %s is not a PNP device\n", dev_path(dev)); - } else if (dev->bus->dev->path.pnp.port != dev->path.pnp.port) { + } else if (dev->upstream->dev->path.pnp.port != dev->path.pnp.port) { bug = true; printk(BIOS_CRIT, "BUG: Parent of device %s has wrong I/O port\n", dev_path(dev)); diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 7befb1e..591593d 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -1226,7 +1226,7 @@ else fprintf(fil, "\t.ops = NULL,\n"); fprintf(fil, "#endif\n"); - fprintf(fil, "\t.bus = &%s_bus,\n", ptr->parent->dev->name); + fprintf(fil, "\t.upstream = &%s_bus,\n", ptr->parent->dev->name); fprintf(fil, "\t.path = {"); fprintf(fil, ptr->path, ptr->path_a, ptr->path_b); fprintf(fil, "},\n"); @@ -1247,10 +1247,10 @@ ptr->name); } if (has_children) - fprintf(fil, "\t.link_list = &%s_bus,\n", + fprintf(fil, "\t.downstream = &%s_bus,\n", ptr->name); else - fprintf(fil, "\t.link_list = NULL,\n"); + fprintf(fil, "\t.downstream = NULL,\n"); if (ptr->sibling) fprintf(fil, "\t.sibling = &%s,\n", ptr->sibling->name); else -- To view, visit https://review.coreboot.org/c/coreboot/+/78330?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Gerrit-Change-Number: 78330 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: device/device.h: Fix outdated comment
by Arthur Heymans (Code Review) 12 Oct '23

12 Oct '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78329?usp=email ) Change subject: device/device.h: Fix outdated comment ...................................................................... device/device.h: Fix outdated comment LAPIC devices in devicetree is not possible any longer since 3eba665 "util/sconfig: Remove lapic devices from devicetree parsers". Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I02192c9a11c35d9625837a8a9f3ba798ff0ae611 --- M src/include/device/device.h 1 file changed, 1 insertion(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/78329/1 diff --git a/src/include/device/device.h b/src/include/device/device.h index 5d7d06d..a55ca82 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -227,14 +227,7 @@ void mp_init_cpus(DEVTREE_CONST struct bus *cpu_bus); static inline void mp_cpu_bus_init(struct device *dev) { - /* - * When no LAPIC device is specified in the devietree inside the CPU cluster device, - * neither a LAPIC device nor the link/bus between the CPU cluster and the LAPIC device - * will be present in the static device tree and the link_list struct element of the - * CPU cluster device will be NULL. In this case add one link, so that the - * alloc_find_dev calls in init_bsp and allocate_cpu_devices will be able to add a - * LAPIC device for the BSP and the APs on this link/bus. - */ + /* Make sure the cpu cluster has a downstream bus for LAPICs to be allocated. */ if (!dev->link_list) { struct bus *bus = calloc(1, sizeof(struct bus)); if (!bus) -- To view, visit https://review.coreboot.org/c/coreboot/+/78329?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I02192c9a11c35d9625837a8a9f3ba798ff0ae611 Gerrit-Change-Number: 78329 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[main]: device/device.h: Drop multiple links
by Arthur Heymans (Code Review) 12 Oct '23

12 Oct '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78328?usp=email ) Change subject: device/device.h: Drop multiple links ...................................................................... device/device.h: Drop multiple links Multiple links are unused throughout the tree and make the code more confusing as an iteration over all busses is needed to get downstream devices. This also not done consistently e.g. the allocator does not care about multiple links on busses. A better way of dealing multiple links below a device is to feature dummy devices with each their respective bus. This drops the sconfig capability to declare the same device multiple times which was previously used to declare multiple links. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Iab6fe269faef46ae77ed1ea425440cf5c7dbd49b --- M src/arch/x86/mpspec.c M src/device/device.c M src/device/device_util.c M src/device/pci_device.c M src/device/root_device.c M src/include/device/device.h M src/northbridge/amd/pi/00730F01/northbridge.c M src/soc/amd/common/block/acpi/ivrs.c M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/intel/common/block/lpc/lpc.c M src/southbridge/amd/pi/hudson/lpc.c M util/sconfig/main.c M util/sconfig/sconfig.h M util/sconfig/sconfig.tab.c_shipped M util/sconfig/sconfig.y 16 files changed, 187 insertions(+), 388 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/78328/1 diff --git a/src/arch/x86/mpspec.c b/src/arch/x86/mpspec.c index 64712c7..3ecb42b 100644 --- a/src/arch/x86/mpspec.c +++ b/src/arch/x86/mpspec.c @@ -281,48 +281,46 @@ int srcbus; int slot; - struct bus *link; unsigned char dstirq_x[4]; - for (link = dev->link_list; link; link = link->next) { + if (!dev->link_list) + return; - child = link->children; - srcbus = link->secondary; + child = dev->link_list->children; + srcbus = dev->link_list->secondary; - while (child) { - if (child->path.type != DEVICE_PATH_PCI) - goto next; + while (child) { + if (child->path.type != DEVICE_PATH_PCI) + goto next; - slot = (child->path.pci.devfn >> 3); - /* round pins */ + slot = (child->path.pci.devfn >> 3); + /* round pins */ + for (i = 0; i < 4; i++) + dstirq_x[i] = dstirq[(i + slot) % 4]; + + if ((child->class >> 16) != PCI_BASE_CLASS_BRIDGE) { + /* pci device */ + printk(BIOS_DEBUG, "route irq: %s\n", + dev_path(child)); for (i = 0; i < 4; i++) - dstirq_x[i] = dstirq[(i + slot) % 4]; - - if ((child->class >> 16) != PCI_BASE_CLASS_BRIDGE) { - /* pci device */ - printk(BIOS_DEBUG, "route irq: %s\n", - dev_path(child)); - for (i = 0; i < 4; i++) - smp_write_intsrc(mc, irqtype, irqflag, - srcbus, (slot<<2)|i, dstapic, - dstirq_x[i]); - goto next; - } - - switch (child->class>>8) { - case PCI_CLASS_BRIDGE_PCI: - case PCI_CLASS_BRIDGE_PCMCIA: - case PCI_CLASS_BRIDGE_CARDBUS: - printk(BIOS_DEBUG, "route irq bridge: %s\n", - dev_path(child)); - smp_write_intsrc_pci_bridge(mc, irqtype, - irqflag, child, dstapic, dstirq_x); - } - -next: - child = child->sibling; + smp_write_intsrc(mc, irqtype, irqflag, + srcbus, (slot<<2)|i, dstapic, + dstirq_x[i]); + goto next; } + switch (child->class>>8) { + case PCI_CLASS_BRIDGE_PCI: + case PCI_CLASS_BRIDGE_PCMCIA: + case PCI_CLASS_BRIDGE_CARDBUS: + printk(BIOS_DEBUG, "route irq bridge: %s\n", + dev_path(child)); + smp_write_intsrc_pci_bridge(mc, irqtype, + irqflag, child, dstapic, dstirq_x); + } + +next: + child = child->sibling; } } @@ -477,17 +475,16 @@ memset(buses, 0, sizeof(buses)); for (dev = all_devices; dev; dev = dev->next) { - struct bus *bus; - for (bus = dev->link_list; bus; bus = bus->next) { - if (bus->secondary > 255) { - printk(BIOS_ERR, - "A bus claims to have a bus ID > 255?!? Aborting"); - return; - } - buses[bus->secondary] = 1; - if (highest < bus->secondary) - highest = bus->secondary; + struct bus *bus = dev->link_list; + if (!bus) + continue; + if (bus->secondary > 255) { + printk(BIOS_ERR, "A bus claims to have a bus ID > 255?!? Aborting"); + return; } + buses[bus->secondary] = 1; + if (highest < bus->secondary) + highest = bus->secondary; } for (i = 0; i <= highest; i++) { if (buses[i]) { diff --git a/src/device/device.c b/src/device/device.c index a635e73..6bdbccf 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -152,13 +152,10 @@ { struct device *curdev; - printk(BIOS_SPEW, "%s %s bus %d link: %d\n", dev_path(bus->dev), - __func__, bus->secondary, bus->link_num); + printk(BIOS_SPEW, "%s %s bus %d\n", dev_path(bus->dev), __func__, bus->secondary); /* Walk through all devices and find which resources they need. */ for (curdev = bus->children; curdev; curdev = curdev->sibling) { - struct bus *link; - if (!curdev->enabled) continue; @@ -172,12 +169,11 @@ curdev->ops->read_resources(curdev); /* Read in the resources behind the current device's links. */ - for (link = curdev->link_list; link; link = link->next) - read_resources(link); + if (curdev->link_list) + read_resources(curdev->link_list); } post_log_clear(); - printk(BIOS_SPEW, "%s %s bus %d link: %d done\n", - dev_path(bus->dev), __func__, bus->secondary, bus->link_num); + printk(BIOS_SPEW, "%s %s bus %d done\n", dev_path(bus->dev), __func__, bus->secondary); } struct device *vga_pri = NULL; @@ -266,8 +262,7 @@ { struct device *curdev; - printk(BIOS_SPEW, "%s %s, bus %d link: %d\n", - dev_path(bus->dev), __func__, bus->secondary, bus->link_num); + printk(BIOS_SPEW, "%s %s, bus %d\n", dev_path(bus->dev), __func__, bus->secondary); for (curdev = bus->children; curdev; curdev = curdev->sibling) { if (!curdev->enabled || !curdev->resource_list) @@ -282,8 +277,7 @@ curdev->ops->set_resources(curdev); } post_log_clear(); - printk(BIOS_SPEW, "%s %s, bus %d link: %d done\n", - dev_path(bus->dev), __func__, bus->secondary, bus->link_num); + printk(BIOS_SPEW, "%s %s, bus %d done\n", dev_path(bus->dev), __func__, bus->secondary); } /** @@ -301,7 +295,6 @@ static void enable_resources(struct bus *link) { struct device *dev; - struct bus *c_link; for (dev = link->children; dev; dev = dev->sibling) { if (dev->enabled && dev->ops && dev->ops->enable_resources) { @@ -311,8 +304,8 @@ } for (dev = link->children; dev; dev = dev->sibling) { - for (c_link = dev->link_list; c_link; c_link = c_link->next) - enable_resources(c_link); + if (dev->link_list) + enable_resources(dev->link_list); } post_log_clear(); } @@ -359,16 +352,14 @@ do_scan_bus = 1; while (do_scan_bus) { - struct bus *link; + struct bus *link = busdev->link_list; busdev->ops->scan_bus(busdev); do_scan_bus = 0; - for (link = busdev->link_list; link; link = link->next) { - if (link->reset_needed) { - if (reset_bus(link)) - do_scan_bus = 1; - else - busdev->bus->reset_needed = 1; - } + if (link && link->reset_needed) { + if (reset_bus(link)) + do_scan_bus = 1; + else + busdev->bus->reset_needed = 1; } } @@ -488,13 +479,11 @@ */ void dev_enable(void) { - struct bus *link; - printk(BIOS_INFO, "Enabling resources...\n"); /* Now enable everything. */ - for (link = dev_root.link_list; link; link = link->next) - enable_resources(link); + if (dev_root.link_list) + enable_resources(dev_root.link_list); printk(BIOS_INFO, "done.\n"); } @@ -518,8 +507,7 @@ long init_time; if (dev->path.type == DEVICE_PATH_I2C) { - printk(BIOS_DEBUG, "smbus: %s[%d]->", - dev_path(dev->bus->dev), dev->bus->link_num); + printk(BIOS_DEBUG, "smbus: %s->", dev_path(dev->bus->dev)); } printk(BIOS_DEBUG, "%s init\n", dev_path(dev)); @@ -537,7 +525,6 @@ static void init_link(struct bus *link) { struct device *dev; - struct bus *c_link; for (dev = link->children; dev; dev = dev->sibling) { post_code(POSTCODE_BS_DEV_INIT); @@ -545,10 +532,9 @@ init_dev(dev); } - for (dev = link->children; dev; dev = dev->sibling) { - for (c_link = dev->link_list; c_link; c_link = c_link->next) - init_link(c_link); - } + for (dev = link->children; dev; dev = dev->sibling) + if (dev->link_list) + init_link(dev->link_list); } /** @@ -559,16 +545,14 @@ */ void dev_initialize(void) { - struct bus *link; - printk(BIOS_INFO, "Initializing devices...\n"); /* First call the mainboard init. */ init_dev(&dev_root); /* Now initialize everything. */ - for (link = dev_root.link_list; link; link = link->next) - init_link(link); + if (dev_root.link_list) + init_link(dev_root.link_list); post_log_clear(); printk(BIOS_INFO, "Devices initialized\n"); @@ -598,15 +582,13 @@ static void final_link(struct bus *link) { struct device *dev; - struct bus *c_link; for (dev = link->children; dev; dev = dev->sibling) final_dev(dev); - for (dev = link->children; dev; dev = dev->sibling) { - for (c_link = dev->link_list; c_link; c_link = c_link->next) - final_link(c_link); - } + for (dev = link->children; dev; dev = dev->sibling) + if (dev->link_list) + final_link(dev->link_list); } /** * Finalize all devices in the global device tree. @@ -616,16 +598,13 @@ */ void dev_finalize(void) { - struct bus *link; - printk(BIOS_INFO, "Finalize devices...\n"); /* First call the mainboard finalize. */ final_dev(&dev_root); /* Now finalize everything. */ - for (link = dev_root.link_list; link; link = link->next) - final_link(link); + final_link(dev_root.link_list); printk(BIOS_INFO, "Devices finalized\n"); } diff --git a/src/device/device_util.c b/src/device/device_util.c index b37d1d9..a0824bd 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -248,14 +248,6 @@ return "unknown"; } -const char *bus_path(struct bus *bus) -{ - static char buffer[BUS_PATH_MAX]; - snprintf(buffer, sizeof(buffer), - "%s,%d", dev_path(bus->dev), bus->link_num); - return buffer; -} - /** * Allocate 64 more resources to the free list. * @@ -553,15 +545,7 @@ /* If it is a subtractive resource recurse. */ if (res->flags & IORESOURCE_SUBTRACTIVE) { - struct bus *subbus; - for (subbus = curdev->link_list; subbus; - subbus = subbus->next) - if (subbus->link_num - == IOINDEX_SUBTRACTIVE_LINK(res->index)) - break; - if (!subbus) /* Why can subbus be NULL? */ - break; - search_bus_resources(subbus, type_mask, type, + search_bus_resources(curdev->link_list, type_mask, type, search, gp); continue; } @@ -617,9 +601,8 @@ struct device *child; for (child = bus->children; child; child = child->sibling) { - struct bus *link; - for (link = child->link_list; link; link = link->next) - disable_children(link); + if (child->link_list) + disable_children(child->link_list); dev_set_enabled(child, 0); } } @@ -630,7 +613,6 @@ */ bool dev_is_active_bridge(struct device *dev) { - struct bus *link; struct device *child; if (!dev || !dev->enabled) @@ -639,71 +621,20 @@ if (!dev->link_list || !dev->link_list->children) return 0; - for (link = dev->link_list; link; link = link->next) { - for (child = link->children; child; child = child->sibling) { - if (child->path.type == DEVICE_PATH_NONE) - continue; - - if (child->enabled) - return 1; - } + for (child = dev->link_list->children; child; child = child->sibling) { + if (child->path.type == DEVICE_PATH_NONE) + continue; + if (child->enabled) + return 1; } return 0; } -/** - * Ensure the device has a minimum number of bus links. - * - * @param dev The device to add links to. - * @param total_links The minimum number of links to have. - */ -void add_more_links(struct device *dev, unsigned int total_links) -{ - struct bus *link, *last = NULL; - int link_num = -1; - - for (link = dev->link_list; link; link = link->next) { - if (link_num < link->link_num) - link_num = link->link_num; - last = link; - } - - if (last) { - int links = total_links - (link_num + 1); - if (links > 0) { - link = malloc(links * sizeof(*link)); - if (!link) - die("Couldn't allocate more links!\n"); - memset(link, 0, links * sizeof(*link)); - last->next = link; - } else { - /* No more links to add */ - return; - } - } else { - link = malloc(total_links * sizeof(*link)); - if (!link) - die("Couldn't allocate more links!\n"); - memset(link, 0, total_links * sizeof(*link)); - dev->link_list = link; - } - - for (link_num = link_num + 1; link_num < total_links; link_num++) { - link->link_num = link_num; - link->dev = dev; - link->next = link + 1; - last = link; - link = link->next; - } - last->next = NULL; -} - static void resource_tree(const struct device *root, int debug_level, int depth) { int i = 0; struct device *child; - struct bus *link; struct resource *res; char indent[30]; /* If your tree has more levels, it's wrong. */ @@ -725,10 +656,11 @@ res->index); } - for (link = root->link_list; link; link = link->next) { - for (child = link->children; child; child = child->sibling) - resource_tree(child, debug_level, depth + 1); - } + if (!root->link_list) + return; + + for (child = root->link_list->children; child; child = child->sibling) + resource_tree(child, debug_level, depth + 1); } void print_resource_tree(const struct device *root, int debug_level, @@ -753,7 +685,6 @@ char depth_str[20]; int i; struct device *sibling; - struct bus *link; for (i = 0; i < depth; i++) depth_str[i] = ' '; @@ -762,11 +693,11 @@ printk(debug_level, "%s%s: enabled %d\n", depth_str, dev_path(dev), dev->enabled); - for (link = dev->link_list; link; link = link->next) { - for (sibling = link->children; sibling; - sibling = sibling->sibling) - show_devs_tree(sibling, debug_level, depth + 1); - } + if (!dev->link_list) + return; + + for (sibling = dev->link_list->children; sibling; sibling = sibling->sibling) + show_devs_tree(sibling, debug_level, depth + 1); } void show_all_devs_tree(int debug_level, const char *msg) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 295e518..dcf4ce3 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -754,16 +754,13 @@ void pci_dev_set_resources(struct device *dev) { struct resource *res; - struct bus *bus; u8 line; for (res = dev->resource_list; res; res = res->next) pci_set_resource(dev, res); - for (bus = dev->link_list; bus; bus = bus->next) { - if (bus->children) - assign_resources(bus); - } + if (dev->link_list && dev->link_list->children) + assign_resources(dev->link_list); /* Set a default latency timer. */ pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40); diff --git a/src/device/root_device.c b/src/device/root_device.c index d8edbd5..cf5ffb7 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -38,31 +38,24 @@ void enable_static_devices(struct device *bus) { struct device *child; - struct bus *link; - for (link = bus->link_list; link; link = link->next) { - for (child = link->children; child; child = child->sibling) { - enable_static_device(child); - } - } + for (child = bus->link_list->children; child; child = child->sibling) + enable_static_device(child); } void scan_generic_bus(struct device *bus) { struct device *child; - struct bus *link; static int bus_max = 0; printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); - for (link = bus->link_list; link; link = link->next) { + if (bus->link_list) { + bus->link_list->secondary = ++bus_max; - link->secondary = ++bus_max; - - for (child = link->children; child; child = child->sibling) { + for (child = bus->link_list->children; child; child = child->sibling) { enable_static_device(child); - printk(BIOS_DEBUG, "bus: %s[%d]->", dev_path(child->bus->dev), - child->bus->link_num); + printk(BIOS_DEBUG, "bus: %s->", dev_path(child->bus->dev)); } } @@ -82,18 +75,16 @@ * given by the mainboard's `devicetree.cb`. * * First, all direct descendants of the given device are - * enabled. Then, downstream buses are scanned. + * enabled. Then, link_list buses are scanned. */ void scan_static_bus(struct device *bus) { - struct bus *link; - printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); enable_static_devices(bus); - for (link = bus->link_list; link; link = link->next) - scan_bridges(link); + if (bus->link_list) + scan_bridges(bus->link_list); printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); } diff --git a/src/include/device/device.h b/src/include/device/device.h index 1aa03d0..5d7d06d 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -4,11 +4,13 @@ #define DEVICE_H -#include <device/resource.h> +#include <console/console.h> #include <device/path.h> #include <device/pci_type.h> +#include <device/resource.h> #include <smbios.h> #include <static.h> +#include <stdlib.h> #include <types.h> struct fw_config; @@ -80,10 +82,8 @@ struct bus { DEVTREE_CONST struct device *dev; /* This bridge device */ DEVTREE_CONST struct device *children; /* devices behind this bridge */ - DEVTREE_CONST struct bus *next; /* The next bridge on this device */ unsigned int bridge_ctrl; /* Bridge control register */ uint16_t bridge_cmd; /* Bridge command register */ - unsigned char link_num; /* The index of this link */ uint16_t secondary; /* secondary bus number */ uint16_t subordinate; /* subordinate bus number */ uint16_t max_subordinate; /* max subordinate bus number */ @@ -189,11 +189,9 @@ const char *dev_name(const struct device *dev); const char *dev_path(const struct device *dev); u32 dev_path_encode(const struct device *dev); -const char *bus_path(struct bus *bus); void dev_set_enabled(struct device *dev, int enable); void disable_children(struct bus *bus); bool dev_is_active_bridge(struct device *dev); -void add_more_links(struct device *dev, unsigned int total_links); bool is_dev_enabled(const struct device *const dev); bool is_devfn_enabled(unsigned int devfn); bool is_cpu(const struct device *cpu); @@ -237,8 +235,12 @@ * alloc_find_dev calls in init_bsp and allocate_cpu_devices will be able to add a * LAPIC device for the BSP and the APs on this link/bus. */ - if (!dev->link_list) - add_more_links(dev, 1); + if (!dev->link_list) { + struct bus *bus = calloc(1, sizeof(struct bus)); + if (!bus) + die("Couldn't allocate downstream bus!\n"); + dev->link_list = bus; + } mp_init_cpus(dev->link_list); } diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index bafe5a5..f471a00 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -173,29 +173,14 @@ static void create_vga_resource(struct device *dev, unsigned int nodeid) { - struct bus *link; unsigned int sblink; sblink = (pci_read_config32(get_mc_dev(), 0x64) >> 8) & 7; // don't forget sublink1 - /* find out which link the VGA card is connected, - * we only deal with the 'first' vga card */ - for (link = dev->link_list; link; link = link->next) { - if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG(MULTIPLE_VGA_ADAPTERS) - extern struct device *vga_pri; // the primary vga device, defined in device.c - printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, - link->secondary, link->subordinate); - /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary) && - (vga_pri->bus->secondary <= link->subordinate)) -#endif - break; - } - } + if (!dev->link_list) + return; - /* no VGA card installed */ - if (link == NULL) + if (!(dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA)) return; printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink); @@ -363,7 +348,6 @@ unsigned long *current, uint16_t *ivhd_length) { struct device *sibling; - struct bus *link; if (!root_level) { root_level = malloc(sizeof(int8_t)); @@ -382,11 +366,11 @@ } } - for (link = dev->link_list; link; link = link->next) - for (sibling = link->children; sibling; sibling = - sibling->sibling) + if (dev->link_list) { + for (sibling = dev->link_list->children; sibling; sibling = sibling->sibling) add_ivhd_device_entries(dev, sibling, depth + 1, depth, root_level, current, ivhd_length); + } free(root_level); } diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index 814f514..03e1fae 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -142,7 +142,6 @@ unsigned long *current, uint16_t nb_bus) { struct device *sibling; - struct bus *link; if (!root_level) return; @@ -157,11 +156,11 @@ ivrs_add_device_or_bridge(parent, dev, current); } - for (link = dev->link_list; link; link = link->next) - for (sibling = link->children; sibling; sibling = - sibling->sibling) - add_ivhd_device_entries(dev, sibling, depth + 1, depth, root_level, - current, nb_bus); + if (!dev->link_list) + return; + for (sibling = dev->link_list->children; sibling; sibling = sibling->sibling) + add_ivhd_device_entries(dev, sibling, depth + 1, depth, root_level, current, + nb_bus); } static unsigned long acpi_ivhd_misc(unsigned long current, struct device *dev) diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 96b9a2c..ca881a2 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -279,20 +279,20 @@ static void lpc_enable_children_resources(struct device *dev) { - struct bus *link; struct device *child; - for (link = dev->link_list; link; link = link->next) { - for (child = link->children; child; child = child->sibling) { - if (!child->enabled) - continue; - if (child->path.type != DEVICE_PATH_PNP) - continue; - if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) - configure_child_espi_windows(child); - else - configure_child_lpc_windows(dev, child); - } + if (!dev->link_list) + return; + + for (child = dev->link_list->children; child; child = child->sibling) { + if (!child->enabled) + continue; + if (child->path.type != DEVICE_PATH_PNP) + continue; + if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) + configure_child_espi_windows(child); + else + configure_child_lpc_windows(dev, child); } } diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 081bc1f..66ebd2a 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -125,16 +125,11 @@ static void create_vga_resource(struct device *dev) { - struct bus *link; - /* find out which link the VGA card is connected, * we only deal with the 'first' vga card */ - for (link = dev->link_list ; link ; link = link->next) - if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) - break; - - /* no VGA card installed */ - if (link == NULL) + if (!dev->link_list) + return; + if (!(dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA)) return; printk(BIOS_DEBUG, "VGA: %s has VGA device\n", dev_path(dev)); @@ -144,7 +139,6 @@ static void set_resources(struct device *dev) { - struct bus *bus; struct resource *res; /* do we need this? */ @@ -154,9 +148,8 @@ for (res = dev->resource_list ; res ; res = res->next) set_resource(dev, res, 0); - for (bus = dev->link_list ; bus ; bus = bus->next) - if (bus->children) - assign_resources(bus); + if (dev->link_list && dev->link_list->children) + assign_resources(dev->link_list); } static void northbridge_init(struct device *dev) diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 0de3154..283a07e 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -100,13 +100,13 @@ */ static void pch_lpc_set_child_resources(struct device *dev) { - struct bus *link; struct device *child; - for (link = dev->link_list; link; link = link->next) { - for (child = link->children; child; child = child->sibling) - pch_lpc_loop_resources(child); - } + if (!dev->link_list) + return; + + for (child = dev->link_list->children; child; child = child->sibling) + pch_lpc_loop_resources(child); } static void pch_lpc_set_resources(struct device *dev) diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 0a4e038..7246fe1 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -134,7 +134,6 @@ */ static void hudson_lpc_enable_childrens_resources(struct device *dev) { - struct bus *link; u32 reg, reg_x; int var_num = 0; u16 reg_var[3]; @@ -171,12 +170,10 @@ reg_var[1] = pci_read_config16(dev, 0x66); reg_var[0] = pci_read_config16(dev, 0x64); - for (link = dev->link_list; link; link = link->next) { - struct device *child; - for (child = link->children; child; - child = child->sibling) { - if (child->enabled - && (child->path.type == DEVICE_PATH_PNP)) { + struct device *child; + if (dev->link_list) { + for (child = dev->link_list->children; child; child = child->sibling) { + if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; for (res = child->resource_list; res; res = res->next) { u32 base, end; /* don't need long long */ @@ -187,7 +184,7 @@ end = resource_end(res); /* find a resource size */ printk(BIOS_DEBUG, "hudson lpc decode:%s, base=0x%08x, end=0x%08x\n", - dev_path(child), base, end); + dev_path(child), base, end); switch (base) { case 0x60: /* KB */ case 0x64: /* MS */ @@ -255,16 +252,16 @@ rsize = 0; /* try AGESA allocated region in region 0 */ if ((var_num > 0) && ((base >= reg_var[0]) && - ((base + res->size) <= (reg_var[0] + reg_size[0])))) + ((base + res->size) <= (reg_var[0] + reg_size[0])))) rsize = reg_size[0]; } /* check if region found and matches the enable */ if (res->size <= rsize) { reg |= set; reg_x |= set_x; - /* check if we can fit resource in variable range */ + /* check if we can fit resource in variable range */ } else if ((var_num < 3) && - ((res->size <= 16) || (res->size == 512))) { + ((res->size <= 16) || (res->size == 512))) { /* use variable ranges if pre-defined do not match */ switch (var_num) { case 0: @@ -285,10 +282,10 @@ break; } reg_var[var_num++] = - base & 0xffff; + base & 0xffff; } else { printk(BIOS_ERR, "cannot fit LPC decode region:%s, base=0x%08x, end=0x%08x\n", - dev_path(child), base, end); + dev_path(child), base, end); } } } diff --git a/util/sconfig/main.c b/util/sconfig/main.c index dd26e07..7befb1e 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -81,7 +81,6 @@ static struct chip_instance mainboard_instance; static struct bus base_root_bus = { - .id = 0, .dev = &base_root_dev, }; @@ -95,7 +94,6 @@ }; static struct bus chipset_root_bus = { - .id = 0, .dev = &chipset_root_dev, }; @@ -109,7 +107,6 @@ }; static struct bus override_root_bus = { - .id = 0, .dev = &override_root_dev, }; @@ -723,30 +720,13 @@ bus->dev->ops_id = ops_id; } -/* - * Allocate a new bus for the provided device. - * - If this is the first bus being allocated under this device, then its id - * is set to 0 and bus and last_bus are pointed to the newly allocated bus. - * - If this is not the first bus under this device, then its id is set to 1 - * plus the id of last bus and newly allocated bus is added to the list of - * buses under the device. last_bus is updated to point to the newly - * allocated bus. - */ +/* Allocate a new bus for the provided device. */ static void alloc_bus(struct device *dev) { struct bus *bus = S_ALLOC(sizeof(*bus)); bus->dev = dev; - - if (dev->last_bus == NULL) { - bus->id = 0; - dev->bus = bus; - } else { - bus->id = dev->last_bus->id + 1; - dev->last_bus->next_bus = bus; - } - - dev->last_bus = bus; + dev->bus = bus; } /* @@ -814,14 +794,12 @@ if (parent->alias && !strcmp(parent->alias, alias)) return parent; - const struct bus *bus; - for (bus = parent->bus; bus; bus = bus->next_bus) { - const struct device *child; - for (child = bus->children; child; child = child->sibling) { - const struct device *const ret = find_alias(child, alias); - if (ret) - return ret; - } + const struct bus *bus = parent->bus; + const struct device *child; + for (child = bus->children; child; child = child->sibling) { + const struct device *const ret = find_alias(child, alias); + if (ret) + return ret; } return NULL; @@ -834,11 +812,11 @@ { struct device *new_d; - /* If device is found under parent, no need to allocate new device. */ + /* We don't allow duplicate devices in devicetree. */ new_d = get_dev(parent, path_a, path_b, bustype, chip_instance); if (new_d) { - alloc_bus(new_d); - return new_d; + printf("ERROR: Duplicate device! %s\n", new_d->name); + exit(1); } new_d = alloc_dev(parent); @@ -1084,11 +1062,8 @@ { struct bus *bus = dev->bus; - while (bus) { - if (bus->children) - return 1; - bus = bus->next_bus; - } + if (bus && bus->children) + return 1; return 0; } @@ -1098,7 +1073,7 @@ static int dev_id; if (ptr == &base_root_dev) { - fprintf(fil, "STORAGE struct bus %s_links[];\n", + fprintf(fil, "STORAGE struct bus %s_bus;\n", ptr->name); return; } @@ -1120,7 +1095,7 @@ fprintf(fil, "STORAGE struct resource %s_res[];\n", ptr->name); if (dev_has_children(ptr)) - fprintf(fil, "STORAGE struct bus %s_links[];\n", + fprintf(fil, "STORAGE struct bus %s_bus;\n", ptr->name); if (next) @@ -1192,35 +1167,18 @@ fprintf(fil, "\t };\n"); } -static void emit_bus(FILE *fil, struct bus *bus) +static void emit_dev_bus(FILE *fil, struct device *ptr) { - fprintf(fil, "\t\t[%d] = {\n", bus->id); - fprintf(fil, "\t\t\t.link_num = %d,\n", bus->id); - fprintf(fil, "\t\t\t.dev = &%s,\n", bus->dev->name); - if (bus->children) - fprintf(fil, "\t\t\t.children = &%s,\n", bus->children->name); - - if (bus->next_bus) - fprintf(fil, "\t\t\t.next=&%s_links[%d],\n", bus->dev->name, - bus->id + 1); - else - fprintf(fil, "\t\t\t.next = NULL,\n"); - fprintf(fil, "\t\t},\n"); -} - -static void emit_dev_links(FILE *fil, struct device *ptr) -{ - fprintf(fil, "STORAGE struct bus %s_links[] = {\n", + fprintf(fil, "STORAGE struct bus %s_bus = {\n", ptr->name); struct bus *bus = ptr->bus; - while (bus) { - emit_bus(fil, bus); - bus = bus->next_bus; - } + fprintf(fil, "\t.dev = &%s,\n", bus->dev->name); + if (bus->children) + fprintf(fil, "\t.children = &%s,\n", bus->children->name); - fprintf(fil, "\t};\n"); + fprintf(fil, "};\n"); } static struct chip_instance *get_chip_instance(const struct device *dev) @@ -1268,8 +1226,7 @@ else fprintf(fil, "\t.ops = NULL,\n"); fprintf(fil, "#endif\n"); - fprintf(fil, "\t.bus = &%s_links[%d],\n", ptr->parent->dev->name, - ptr->parent->id); + fprintf(fil, "\t.bus = &%s_bus,\n", ptr->parent->dev->name); fprintf(fil, "\t.path = {"); fprintf(fil, ptr->path, ptr->path_a, ptr->path_b); fprintf(fil, "},\n"); @@ -1290,7 +1247,7 @@ ptr->name); } if (has_children) - fprintf(fil, "\t.link_list = &%s_links[0],\n", + fprintf(fil, "\t.link_list = &%s_bus,\n", ptr->name); else fprintf(fil, "\t.link_list = NULL,\n"); @@ -1319,7 +1276,7 @@ emit_resources(fil, ptr); if (has_children) - emit_dev_links(fil, ptr); + emit_dev_bus(fil, ptr); } static void expose_device_names(FILE *fil, FILE *head, struct device *ptr, struct device *next) @@ -1370,11 +1327,8 @@ { struct bus *bus = d->bus; - while (bus) { - if (bus->children) - add_siblings_to_queue(bfs_q_head, bus->children); - bus = bus->next_bus; - } + if (bus && bus->children) + add_siblings_to_queue(bfs_q_head, bus->children); } static void walk_device_tree(FILE *fil, FILE *head, struct device *ptr, @@ -1722,16 +1676,6 @@ * | | and value from override register. | * | | | * +-----------------------------------------------------------------+ - * | | | - * | bus | Recursively call override_devicetree on | - * | last_bus | each bus of override device. It is assumed | - * | | that bus with id X under base device | - * | | to bus with id X under override device. If | - * | | override device has more buses than base | - * | | device, then new buses are allocated under | - * | | base device. | - * | | | - * +-----------------------------------------------------------------+ */ static void update_device(struct device *base_dev, struct device *override_dev) { @@ -1841,29 +1785,20 @@ /* * Now that the device properties are all copied over, look at each bus * of the override device and run override_devicetree in a recursive - * manner. The assumption here is that first bus of override device - * corresponds to first bus of base device and so on. If base device has - * lesser buses than override tree, then new buses are allocated for it. + * manner. If base device has no bus but the override tree has, then a new + * buses is allocated for it. */ struct bus *override_bus = override_dev->bus; struct bus *base_bus = base_dev->bus; - while (override_bus) { + /* + * If we have more buses in override tree device, then allocate + * a new bus for the base tree device as well. + */ + if (!base_bus) + alloc_bus(base_dev); - /* - * If we have more buses in override tree device, then allocate - * a new bus for the base tree device as well. - */ - if (!base_bus) { - alloc_bus(base_dev); - base_bus = base_dev->last_bus; - } - - override_devicetree(base_dev->bus, override_dev->bus); - - override_bus = override_bus->next_bus; - base_bus = base_bus->next_bus; - } + override_devicetree(base_dev->bus, override_dev->bus); } /* diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index cb8f7b3..fb49f9f 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -106,17 +106,11 @@ struct device; struct bus { - /* Instance/ID of the bus under the device. */ - int id; - /* Pointer to device to which this bus belongs. */ struct device *dev; /* Pointer to list of children. */ struct device *children; - - /* Pointer to next bus for the device. */ - struct bus *next_bus; }; struct device { diff --git a/util/sconfig/sconfig.tab.c_shipped b/util/sconfig/sconfig.tab.c_shipped index cb60fb5..5b10922 100644 --- a/util/sconfig/sconfig.tab.c_shipped +++ b/util/sconfig/sconfig.tab.c_shipped @@ -1238,7 +1238,7 @@ case 26: /* @2: %empty */ { (yyval.dev) = new_device_raw(cur_parent, cur_chip_instance, (yyvsp[-3].number), (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].number)); - cur_parent = (yyval.dev)->last_bus; + cur_parent = (yyval.dev)->bus; } break; @@ -1251,7 +1251,7 @@ case 28: /* @3: %empty */ { (yyval.dev) = new_device_reference(cur_parent, cur_chip_instance, (yyvsp[-1].string), (yyvsp[0].number)); - cur_parent = (yyval.dev)->last_bus; + cur_parent = (yyval.dev)->bus; } break; diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index 17ab9a5..8ec103c 100644 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -44,7 +44,7 @@ device: DEVICE BUS NUMBER /* == devnum */ alias status { $<dev>$ = new_device_raw(cur_parent, cur_chip_instance, $<number>2, $<string>3, $<string>4, $<number>5); - cur_parent = $<dev>$->last_bus; + cur_parent = $<dev>$->bus; } devicechildren END { cur_parent = $<dev>6->parent; @@ -52,7 +52,7 @@ device: DEVICE REFERENCE STRING status { $<dev>$ = new_device_reference(cur_parent, cur_chip_instance, $<string>3, $<number>4); - cur_parent = $<dev>$->last_bus; + cur_parent = $<dev>$->bus; } devicechildren END { cur_parent = $<dev>5->parent; -- To view, visit https://review.coreboot.org/c/coreboot/+/78328?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab6fe269faef46ae77ed1ea425440cf5c7dbd49b Gerrit-Change-Number: 78328 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation
by Arthur Heymans (Code Review) 12 Oct '23

12 Oct '23

Attention is currently required from: Christian Walter, Johnny Lin, Tim Chu. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email ) Change subject: soc/intel/xeon_sp: Redesign resource allocation ...................................................................... soc/intel/xeon_sp: Redesign resource allocation The xeon_sp code worked around the coreboot allocator rather than using it. Now the allocator is able to deal with the multiple IIOs so this is not necessary anymore. Instead do the following: - Parse the FPS HOB information about IIO into coreboot PCI domains - Use existing scan_bus and read_resource - When a stack contains multiple host bridges as sometimes the case for DINO stacks, add host bridges for each bus. TEST: See that all resources are properly allocated on intel/archercity. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 --- M src/device/pci_device.c M src/include/device/device.h M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/memmap.c M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/skx/soc_util.c M src/soc/intel/xeon_sp/spr/chip.c M src/soc/intel/xeon_sp/spr/soc_util.c M src/soc/intel/xeon_sp/util.c 14 files changed, 172 insertions(+), 534 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/78327/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 21b4352..295e518 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -588,6 +588,47 @@ assign_resources(dev->link_list); } +static void host_bridge_resources(struct device *dev) +{ + int index = 0; + struct resource *res; + res = new_resource(dev, index++); + res->base = 0; + res->limit = 0xffff; + res->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; + + res = new_resource(dev, index++); + res->base = 0; + res->limit = 0xffffffffffff; + res->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; + + res = new_resource(dev, index++); + res->base = 0; + res->limit = 0xffffffffffff; + res->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE | IORESOURCE_PREFETCH; +} + +static struct device_operations host_bridge_ops = { + .read_resources = host_bridge_resources, + .set_resources = noop_set_resources, + .scan_bus = pci_host_bridge_scan_bus, +}; + +struct device *alloc_pci_host_bridge(struct device *parent_dev, uint16_t secondary_bus) +{ + struct device_path path = { .type = DEVICE_PATH_GENERIC }; + struct device *pci_host_dev = alloc_dev(parent_dev->link_list, &path); + pci_host_dev->ops = &host_bridge_ops; + struct bus *pci_bus = calloc(1, sizeof(struct bus)); + if (pci_bus == NULL) + die("%s: out of memory.\n", __func__); + pci_bus->secondary = secondary_bus; + pci_bus->subordinate = secondary_bus; + pci_host_dev->link_list = pci_bus; + + return pci_host_dev; +} + static void pci_store_resource(const struct device *const dev, const struct resource *const resource) { diff --git a/src/include/device/device.h b/src/include/device/device.h index 68e2622..1aa03d0 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -273,6 +273,7 @@ void pci_domain_read_resources(struct device *dev); void pci_domain_set_resources(struct device *dev); void pci_host_bridge_scan_bus(struct device *dev); +struct device *alloc_pci_host_bridge(struct device *parent_dev, uint16_t secondary_bus); void mmconf_resource(struct device *dev, unsigned long index); diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 519d6c7..61d5186 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -104,7 +104,7 @@ for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; - if (!is_iio_stack_res(ri)) + if (!stack_needs_resource_alloc(ri)) continue; uint32_t ioapic_base = ri->IoApicBase; assert(index < ARRAY_SIZE(xeonsp_ioapic_bases)); diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index a9b1260..12add8e 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -9,548 +9,128 @@ #include <soc/util.h> #include <stdlib.h> -struct pci_resource { - struct device *dev; - struct resource *res; - struct pci_resource *next; -}; - -struct stack_dev_resource { - uint8_t align; - struct pci_resource *children; - struct stack_dev_resource *next; -}; - -typedef enum { - RES_TYPE_IO = 0, - RES_TYPE_NONPREF_MEM, - RES_TYPE_PREF_MEM, - MAX_RES_TYPES -} RES_TYPE; - -static RES_TYPE get_res_type(uint64_t flags) +static const STACK_RES *domain_to_stack_res(const struct device *dev) { - if (flags & IORESOURCE_IO) - return RES_TYPE_IO; - if (flags & IORESOURCE_MEM) { - if (flags & IORESOURCE_PREFETCH) { - printk(BIOS_DEBUG, "%s:%d flags: 0x%llx\n", __func__, __LINE__, flags); - return RES_TYPE_PREF_MEM; - } - /* both 64-bit and 32-bit use below 4GB address space */ - return RES_TYPE_NONPREF_MEM; - } - die("Invalid resource type 0x%llx\n", flags); -} + assert(dev->path.type != DEVICE_PATH_DOMAIN); + const unsigned int dn = dev->path.domain.domain; -static bool need_assignment(uint64_t flags) -{ - if (flags & (IORESOURCE_STORED | IORESOURCE_RESERVE | IORESOURCE_FIXED | - IORESOURCE_ASSIGNED)) - return false; - else - return true; -} - -static uint64_t get_resource_base(STACK_RES *stack, RES_TYPE res_type) -{ - if (res_type == RES_TYPE_IO) { - assert(stack->PciResourceIoBase <= stack->PciResourceIoLimit); - return stack->PciResourceIoBase; - } - if (res_type == RES_TYPE_NONPREF_MEM) { - assert(stack->PciResourceMem32Base <= stack->PciResourceMem32Limit); - return stack->PciResourceMem32Base; - } - assert(stack->PciResourceMem64Base <= stack->PciResourceMem64Limit); - return stack->PciResourceMem64Base; -} - -static void set_resource_base(STACK_RES *stack, RES_TYPE res_type, uint64_t base) -{ - if (res_type == RES_TYPE_IO) { - assert(base <= (stack->PciResourceIoLimit + 1)); - stack->PciResourceIoBase = base; - } else if (res_type == RES_TYPE_NONPREF_MEM) { - assert(base <= (stack->PciResourceMem32Limit + 1)); - stack->PciResourceMem32Base = base; - } else { - assert(base <= (stack->PciResourceMem64Limit + 1)); - stack->PciResourceMem64Base = base; - } -} - -static void assign_stack_resources(struct iiostack_resource *stack_list, - struct device *dev, struct resource *bridge); - -void xeonsp_pci_domain_scan_bus(struct device *dev) -{ - DEV_FUNC_ENTER(dev); - struct bus *link = dev->link_list; - - printk(BIOS_SPEW, "%s:%s scanning buses under device %s\n", - __FILE__, __func__, dev_path(dev)); - while (link) { - if (link->secondary == 0) { // scan only PSTACK buses - struct device *d; - for (d = link->children; d; d = d->sibling) - pci_probe_dev(d, link, d->path.pci.devfn); - scan_bridges(link); - } else { - pci_scan_bus(link, PCI_DEVFN(0, 0), 0xff); - } - link = link->next; - } - DEV_FUNC_EXIT(dev); -} - -static void xeonsp_pci_dev_iterator(struct bus *bus, - void (*dev_iterator)(struct device *, void *), - void (*res_iterator)(struct device *, struct resource *, void *), - void *data) -{ - struct device *curdev; - struct resource *res; - - /* Walk through all devices and find which resources they need. */ - for (curdev = bus->children; curdev; curdev = curdev->sibling) { - struct bus *link; - - if (!curdev->enabled) - continue; - - if (!curdev->ops || !curdev->ops->read_resources) { - if (curdev->path.type != DEVICE_PATH_APIC) - printk(BIOS_ERR, "%s missing read_resources\n", - dev_path(curdev)); - continue; - } - - if (dev_iterator) - dev_iterator(curdev, data); - - if (res_iterator) { - for (res = curdev->resource_list; res; res = res->next) - res_iterator(curdev, res, data); - } - - /* Read in the resources behind the current device's links. */ - for (link = curdev->link_list; link; link = link->next) - xeonsp_pci_dev_iterator(link, dev_iterator, res_iterator, data); - } -} - -static void xeonsp_pci_dev_read_resources(struct device *dev, void *data) -{ - post_log_path(dev); - dev->ops->read_resources(dev); -} - -static void xeonsp_pci_dev_dummy_func(struct device *dev) -{ -} - -static void xeonsp_reset_pci_op(struct device *dev, void *data) -{ - if (dev->ops) - dev->ops->read_resources = xeonsp_pci_dev_dummy_func; -} - -static STACK_RES *find_stack_for_bus(struct iiostack_resource *info, uint8_t bus) -{ - for (int i = 0; i < info->no_of_stacks; ++i) { - if (bus >= info->res[i].BusBase && bus <= info->res[i].BusLimit) - return &info->res[i]; - } - return NULL; -} - -static void add_res_to_stack(struct stack_dev_resource **root, - struct device *dev, struct resource *res) -{ - struct stack_dev_resource *cur = *root; - while (cur) { - if (cur->align == res->align || !cur->next) /* equal or last record */ - break; - else if (cur->align > res->align) { - if (cur->next->align < res->align) /* need to insert new record here */ - break; - cur = cur->next; - } else { - break; - } - } - - struct stack_dev_resource *nr; - if (!cur || cur->align != res->align) { /* need to add new record */ - nr = malloc(sizeof(struct stack_dev_resource)); - if (nr == 0) - die("assign_resource_to_stack(): out of memory.\n"); - memset(nr, 0, sizeof(struct stack_dev_resource)); - nr->align = res->align; - if (!cur) { - *root = nr; /* head node */ - } else if (cur->align > nr->align) { - if (!cur->next) { - cur->next = nr; - } else { - nr->next = cur->next; - cur->next = nr; - } - } else { /* insert in the beginning */ - nr->next = cur; - *root = nr; - } - } else { - nr = cur; - } - - assert(nr && nr->align == res->align); - - struct pci_resource *npr = malloc(sizeof(struct pci_resource)); - if (!npr) - die("%s: out of memory.\n", __func__); - npr->res = res; - npr->dev = dev; - npr->next = NULL; - - if (!nr->children) { - nr->children = npr; - } else { - struct pci_resource *pr = nr->children; - while (pr->next) - pr = pr->next; - pr->next = npr; - } -} - -static void reserve_dev_resources(STACK_RES *stack, RES_TYPE res_type, - struct stack_dev_resource *res_root, struct resource *bridge) -{ - uint64_t orig_base, base; - - orig_base = get_resource_base(stack, res_type); - - base = orig_base; - int first = 1; - while (res_root) { /* loop through all devices grouped by alignment requirements */ - struct pci_resource *pr = res_root->children; - while (pr) { - if (first) { - if (bridge) { /* takes highest alignment */ - if (bridge->align < pr->res->align) - bridge->align = pr->res->align; - orig_base = ALIGN_UP(orig_base, 1 << bridge->align); - } else { - orig_base = ALIGN_UP(orig_base, 1 << pr->res->align); - } - base = orig_base; - - if (bridge) - bridge->base = base; - pr->res->base = base; - first = 0; - } else { - pr->res->base = ALIGN_UP(base, 1 << pr->res->align); - } - pr->res->limit = pr->res->base + pr->res->size - 1; - base = pr->res->limit + 1; - pr->res->flags |= (IORESOURCE_ASSIGNED); - pr = pr->next; - } - res_root = res_root->next; - } - - if (bridge) { - /* this bridge doesn't have any resources, will set it to default window */ - if (first) { - orig_base = ALIGN_UP(orig_base, 1 << bridge->align); - bridge->base = orig_base; - base = orig_base + (1ULL << bridge->gran); - } - - bridge->size = ALIGN_UP(base, 1 << bridge->align) - bridge->base; - - bridge->limit = bridge->base + bridge->size - 1; - bridge->flags |= (IORESOURCE_ASSIGNED); - base = bridge->limit + 1; - } - - set_resource_base(stack, res_type, base); -} - -static void reclaim_resource_mem(struct stack_dev_resource *res_root) -{ - while (res_root) { /* loop through all devices grouped by alignment requirements */ - /* free pci_resource */ - struct pci_resource *pr = res_root->children; - while (pr) { - struct pci_resource *dpr = pr; - pr = pr->next; - free(dpr); - } - - /* free stack_dev_resource */ - struct stack_dev_resource *ddr = res_root; - res_root = res_root->next; - free(ddr); - } -} - -static void assign_bridge_resources(struct iiostack_resource *stack_list, - struct device *dev, struct resource *bridge) -{ - struct resource *res; - if (!dev->enabled) - return; - - for (res = dev->resource_list; res; res = res->next) { - if (!(res->flags & IORESOURCE_BRIDGE) || - (bridge && (get_res_type(bridge->flags) != get_res_type(res->flags)))) - continue; - - assign_stack_resources(stack_list, dev, res); - - if (!bridge) - continue; - - /* for 1st time update, overlading IORESOURCE_ASSIGNED */ - if (!(bridge->flags & IORESOURCE_ASSIGNED)) { - bridge->base = res->base; - bridge->limit = res->limit; - bridge->flags |= (IORESOURCE_ASSIGNED); - } else { - /* update bridge range from child bridge range */ - if (res->base < bridge->base) - bridge->base = res->base; - if (res->limit > bridge->limit) - bridge->limit = res->limit; - } - bridge->size = (bridge->limit - bridge->base + 1); - } -} - -static void assign_stack_resources(struct iiostack_resource *stack_list, - struct device *dev, struct resource *bridge) -{ - struct bus *bus; - - /* Read in the resources behind the current device's links. */ - for (bus = dev->link_list; bus; bus = bus->next) { - struct device *curdev; - STACK_RES *stack; - - /* get IIO stack for this bus */ - stack = find_stack_for_bus(stack_list, bus->secondary); - assert(stack); - - /* Assign resources to bridge */ - for (curdev = bus->children; curdev; curdev = curdev->sibling) - assign_bridge_resources(stack_list, curdev, bridge); - - /* Pick non-bridged resources for resource allocation for each resource type */ - RES_TYPE res_types[MAX_RES_TYPES] = { - RES_TYPE_IO, - RES_TYPE_NONPREF_MEM, - RES_TYPE_PREF_MEM - }; - - uint8_t no_res_types = MAX_RES_TYPES; - - /* if it is a bridge, only process matching bridge resource type */ - if (bridge) { - res_types[0] = get_res_type(bridge->flags); - no_res_types = 1; - } - - printk(BIOS_DEBUG, "%s:%d no_res_types: %d\n", __func__, __LINE__, - no_res_types); - - /* Process each resource type */ - for (int rt = 0; rt < no_res_types; ++rt) { - struct stack_dev_resource *res_root = NULL; - printk(BIOS_DEBUG, "%s:%d rt: %d\n", __func__, __LINE__, rt); - for (curdev = bus->children; curdev; curdev = curdev->sibling) { - struct resource *res; - printk(BIOS_DEBUG, "%s:%d dev: %s\n", - __func__, __LINE__, dev_path(curdev)); - if (!curdev->enabled) - continue; - - for (res = curdev->resource_list; res; res = res->next) { - printk(BIOS_DEBUG, "%s:%d dev: %s, flags: 0x%lx\n", - __func__, __LINE__, - dev_path(curdev), res->flags); - if (res->size == 0 || - get_res_type(res->flags) != res_types[rt] || - (res->flags & IORESOURCE_BRIDGE) || - !need_assignment(res->flags)) - continue; - else - add_res_to_stack(&res_root, curdev, res); - } - } - - /* Allocate resources and update bridge range */ - if (res_root || (bridge && !(bridge->flags & IORESOURCE_ASSIGNED))) { - reserve_dev_resources(stack, res_types[rt], res_root, bridge); - reclaim_resource_mem(res_root); - } - } - } -} - -static uint8_t is_pci64bit_alloc(void) -{ -/* - * For SPR-SP FSP which supports SOC_INTEL_PCIE_64BITS_ALLOC, - * Pci64BitResourceAllocation field does not exist in IIO_UDS HOB. - */ -#if CONFIG(SOC_INTEL_PCIE_64BIT_ALLOC) - return 1; -#else const IIO_UDS *hob = get_iio_uds(); - return hob->PlatformData.Pci64BitResourceAllocation; -#endif + return &hob->PlatformData.IIO_resource[dn / MAX_IIO_STACK].StackRes[dn % MAX_IIO_STACK]; } -static void xeonsp_pci_domain_read_resources(struct device *dev) +void iio_pci_domain_read_resources(struct device *dev) { - struct bus *link; + struct resource *res; + const STACK_RES *sr = domain_to_stack_res(dev); + int index = 0; - DEV_FUNC_ENTER(dev); - - pci_domain_read_resources(dev); - - /* - * Walk through all devices in this domain and read resources. - * Since there is no callback when read resource operation is - * complete for all devices, domain read resource function initiates - * read resources for all devices and swaps read resource operation - * with dummy function to avoid warning. - */ - for (link = dev->link_list; link; link = link->next) - xeonsp_pci_dev_iterator(link, xeonsp_pci_dev_read_resources, NULL, NULL); - - for (link = dev->link_list; link; link = link->next) - xeonsp_pci_dev_iterator(link, xeonsp_reset_pci_op, NULL, NULL); - - struct iiostack_resource stack_info = {0}; - get_iiostack_info(&stack_info); - if (!is_pci64bit_alloc()) { - /* - * Split 32 bit address space between prefetchable and - * non-prefetchable windows - */ - for (int s = 0; s < stack_info.no_of_stacks; ++s) { - STACK_RES *res = &stack_info.res[s]; - uint64_t length = (res->PciResourceMem32Limit - - res->PciResourceMem32Base + 1)/2; - res->PciResourceMem64Limit = res->PciResourceMem32Limit; - res->PciResourceMem32Limit = (res->PciResourceMem32Base + length - 1); - res->PciResourceMem64Base = res->PciResourceMem32Limit + 1; - } + if (dev->path.domain.domain == 0) { + /* The 0 - 0xfff IO range is not reported by the HOB but still gets decoded */ + res = new_resource(dev, index++); + res->base = 0; + res->size = 0x1000; + res->limit = 0xfff; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; } - /* assign resources */ - assign_stack_resources(&stack_info, dev, NULL); + if (sr->PciResourceIoBase < sr->PciResourceIoLimit) { + res = new_resource(dev, index++); + res->base = sr->PciResourceIoBase; + res->limit = sr->PciResourceIoLimit; + res->size = res->limit - res->base + 1; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; + } - DEV_FUNC_EXIT(dev); -} + if (sr->PciResourceMem32Base < sr->PciResourceMem32Limit) { + res = new_resource(dev, index++); + res->base = sr->PciResourceMem32Base; + res->limit = sr->PciResourceMem32Limit; + res->size = res->limit - res->base + 1; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; + } -static void reset_resource_to_unassigned(struct device *dev, struct resource *res, void *data) -{ - if ((res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) && - !(res->flags & (IORESOURCE_FIXED | IORESOURCE_RESERVE))) { - res->flags &= ~IORESOURCE_ASSIGNED; + if (sr->PciResourceMem64Base < sr->PciResourceMem64Limit) { + res = new_resource(dev, index++); + res->base = sr->PciResourceMem64Base; + res->limit = sr->PciResourceMem64Limit; + res->size = res->limit - res->base + 1; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; } } -void xeonsp_pci_domain_set_resources(struct device *dev) +void iio_pci_domain_scan_bus(struct device *dev) { - DEV_FUNC_ENTER(dev); - - print_resource_tree(dev, BIOS_SPEW, "Before xeonsp pci domain set resource"); - - /* reset bus 0 dev resource assignment - need to change them to FSP IIOStack window */ - xeonsp_pci_dev_iterator(dev->link_list, NULL, reset_resource_to_unassigned, NULL); - - /* update dev resources based on IIOStack IO/Mem32/Mem64 windows */ - xeonsp_pci_domain_read_resources(dev); - - struct bus *link = dev->link_list; - while (link) { - assign_resources(link); - link = link->next; + const STACK_RES *sr = domain_to_stack_res(dev); + if (!dev->link_list) { + dev->link_list = calloc(1, sizeof(struct bus)); + if (!dev->link_list) + die("%s: out of memory.\n", __func__); } - print_resource_tree(dev, BIOS_SPEW, "After xeonsp pci domain set resource"); + struct bus *bus = dev->link_list; + bus->secondary = sr->BusBase; + bus->subordinate = sr->BusBase; + bus->max_subordinate = sr->BusLimit; - DEV_FUNC_EXIT(dev); + printk(BIOS_SPEW, "Scanning IIO stack %d: busses %x-%x\n", dev->path.domain.domain, + dev->link_list->secondary, dev->link_list->max_subordinate); + pci_host_bridge_scan_bus(dev); } -/* Attach IIO stack bus numbers with dummy device to PCI DOMAIN 0000 device */ +static void non_iio_pci_domain_scan_bus(struct device *dev) +{ + const STACK_RES *sr = domain_to_stack_res(dev); + struct bus *bus = calloc(1, sizeof(struct bus)); + if (bus == NULL) + die("%s: out of memory.\n", __func__); + bus->secondary = sr->BusBase; + bus->subordinate = sr->BusBase; + bus->max_subordinate = sr->BusLimit; + dev->link_list = bus; + + /* Add host_bridge devices for each PCI BUS */ + for (int i = sr->BusBase; i <= sr->BusLimit; i++) { + if (pci_s_read_config16(PCI_DEV(i, 0, 0), PCI_VENDOR_ID) == 0xffff) + continue; + printk(BIOS_SPEW, "Scanning nonIIO stack %d: Found host bridge at bus %d\n", + dev->path.domain.domain, i); + struct device *host_bridge = alloc_pci_host_bridge(dev, i); + /* We only expect bridges on IIO stacks so set this to secondary */ + host_bridge->link_list->max_subordinate = i; + } +} + +static struct device_operations iiostack_pci_domain_ops = { + .read_resources = iio_pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .scan_bus = iio_pci_domain_scan_bus, +}; + +static struct device_operations non_iiostack_pci_domain_ops = { + .read_resources = iio_pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .scan_bus = non_iio_pci_domain_scan_bus, +}; + +/* Attach IIO stack as domains */ void attach_iio_stacks(struct device *dev) { - struct device dummy; - struct iiostack_resource stack_info = {0}; - - DEV_FUNC_ENTER(dev); - - get_iiostack_info(&stack_info); - - for (int s = 0; s < stack_info.no_of_stacks; ++s) { - STACK_RES *sr = &stack_info.res[s]; - /* only non zero bus no. needs to be enumerated */ - if (sr->BusBase == 0) { - /* Update BUS 0 BusLimit */ - dev->link_list->max_subordinate = sr->BusLimit; - continue; - } - - for (int b = sr->BusBase; b <= sr->BusLimit; ++b) { - struct bus tmp_bus; - memset(&tmp_bus, 0, sizeof(tmp_bus)); - memcpy(&tmp_bus, dev->bus, sizeof(tmp_bus)); - tmp_bus.secondary = b; - tmp_bus.subordinate = b; - tmp_bus.max_subordinate = sr->BusLimit; - tmp_bus.dev = NULL; - tmp_bus.children = NULL; - tmp_bus.next = NULL; - tmp_bus.link_num = 1; - - dummy.bus = &tmp_bus; - dummy.path.type = DEVICE_PATH_PCI; - dummy.path.pci.devfn = 0; - uint32_t id = pci_read_config32(&dummy, PCI_VENDOR_ID); - if (id == 0xffffffff) { - printk(BIOS_DEBUG, "IIO Stack device %s not visible\n", - dev_path(&dummy)); + const IIO_UDS *hob = get_iio_uds(); + for (int s = 0; s < hob->PlatformData.numofIIO; ++s) { + for (int x = 0; x < MAX_IIO_STACK; ++x) { + if (s == 0 && x == 0) continue; - } - printk(BIOS_DEBUG, "%s Attaching IIO Bus %s\n", __func__, - dev_path(&dummy)); - printk(BIOS_DEBUG, " %s attach secondary: 0x%x, subordinate: 0x%x, dev: %s\n", - __func__, tmp_bus.secondary, - tmp_bus.subordinate, dev_path(&dummy)); - - struct bus *iiostack_bus = malloc(sizeof(struct bus)); - if (iiostack_bus == NULL) + const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; + if (!stack_needs_resource_alloc(ri)) + continue; + struct device_path path; + path.type = DEVICE_PATH_DOMAIN; + path.domain.domain = s * MAX_IIO_STACK + x; + struct device *iio_domain = alloc_dev(dev->bus, &path); + if (iio_domain == NULL) die("%s: out of memory.\n", __func__); - memcpy(iiostack_bus, &tmp_bus, sizeof(*iiostack_bus)); - - if (dev->link_list == NULL) { - dev->link_list = iiostack_bus; - } else { - struct bus *nlink = dev->link_list; - while (nlink->next != NULL) - nlink = nlink->next; - nlink->next = iiostack_bus; - } + iio_domain->ops = is_iio_stack_res(ri) ? &iiostack_pci_domain_ops : &non_iiostack_pci_domain_ops; } } - - DEV_FUNC_EXIT(dev); } diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index dd9c113..9f0c846 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -36,9 +36,9 @@ #endif static struct device_operations pci_domain_ops = { - .read_resources = &pci_domain_read_resources, - .set_resources = &xeonsp_pci_domain_set_resources, - .scan_bus = &xeonsp_pci_domain_scan_bus, + .read_resources = iio_pci_domain_read_resources, + .set_resources = noop_set_resources, + .scan_bus = iio_pci_domain_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = &northbridge_write_acpi_tables, .acpi_name = soc_acpi_name diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index 64efb61..fb76014 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -25,11 +25,16 @@ return *memmap_addr; } -bool is_iio_stack_res(const STACK_RES *res) +bool stack_needs_resource_alloc(const STACK_RES *res) { return res->Personality == TYPE_UBOX_IIO; } +bool is_iio_stack_res(const STACK_RES *res) +{ + return stack_needs_resource_alloc(res); +} + uint8_t get_stack_busno(const uint8_t stack) { if (stack >= MAX_IIO_STACK) { diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index 339da07..989c622 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -3,8 +3,8 @@ #ifndef _CHIP_COMMON_H_ #define _CHIP_COMMON_H_ -void xeonsp_pci_domain_set_resources(struct device *dev); -void xeonsp_pci_domain_scan_bus(struct device *dev); +void iio_pci_domain_read_resources(struct device *dev); +void iio_pci_domain_scan_bus(struct device *dev); void attach_iio_stacks(struct device *dev); #endif /* _CHIP_COMMON_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index 8e80c64..8482efd 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -23,6 +23,7 @@ }; void get_iiostack_info(struct iiostack_resource *info); +bool stack_needs_resource_alloc(const STACK_RES *res); bool is_iio_stack_res(const STACK_RES *res); void bios_done_msr(void *unused); diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c index 8562eb1..e73143f 100644 --- a/src/soc/intel/xeon_sp/memmap.c +++ b/src/soc/intel/xeon_sp/memmap.c @@ -74,7 +74,7 @@ for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; - if (!is_iio_stack_res(ri)) + if (!stack_needs_resource_alloc(ri)) continue; uint8_t bus = ri->BusBase; dev = VTD_DEV(bus); diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index a113d5a..a2e0e95 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -23,9 +23,9 @@ #endif static struct device_operations pci_domain_ops = { - .read_resources = &pci_domain_read_resources, - .set_resources = &xeonsp_pci_domain_set_resources, - .scan_bus = &xeonsp_pci_domain_scan_bus, + .read_resources = iio_pci_domain_read_resources, + .set_resources = noop_set_resources, + .scan_bus = iio_pci_domain_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = &northbridge_write_acpi_tables, .acpi_name = soc_acpi_name diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index b501a3e..d7e3efc1 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -54,12 +54,17 @@ return memmap_addr; } -bool is_iio_stack_res(const STACK_RES *res) +bool stack_needs_resource_alloc(const STACK_RES *res) { // TODO: do we have situation with only bux 0 and one stack? return res->BusBase < res->BusLimit; } +bool is_iio_stack_res(const STACK_RES *res) +{ + return stack_needs_resource_alloc(res); +} + uint8_t get_stack_busno(const uint8_t stack) { if (stack >= MAX_IIO_STACK) { diff --git a/src/soc/intel/xeon_sp/spr/chip.c b/src/soc/intel/xeon_sp/spr/chip.c index f9c43db..86c3b3c 100644 --- a/src/soc/intel/xeon_sp/spr/chip.c +++ b/src/soc/intel/xeon_sp/spr/chip.c @@ -47,9 +47,9 @@ #endif static struct device_operations pci_domain_ops = { - .read_resources = &pci_domain_read_resources, - .set_resources = &xeonsp_pci_domain_set_resources, - .scan_bus = &xeonsp_pci_domain_scan_bus, + .read_resources = iio_pci_domain_read_resources, + .set_resources = noop_set_resources, + .scan_bus = iio_pci_domain_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = &northbridge_write_acpi_tables, .acpi_name = soc_acpi_name diff --git a/src/soc/intel/xeon_sp/spr/soc_util.c b/src/soc/intel/xeon_sp/spr/soc_util.c index f352145..e885bba 100644 --- a/src/soc/intel/xeon_sp/spr/soc_util.c +++ b/src/soc/intel/xeon_sp/spr/soc_util.c @@ -68,11 +68,16 @@ return hob->Element; } -bool is_iio_stack_res(const STACK_RES *res) +bool stack_needs_resource_alloc(const STACK_RES *res) { return res->Personality == TYPE_UBOX_IIO || res->Personality == TYPE_DINO; } +bool is_iio_stack_res(const STACK_RES *res) +{ + return res->Personality == TYPE_UBOX_IIO; +} + /* * Given a stack resource, figure out whether the corresponding stack has * CXL device. diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index 86dcb97..c9f4c55 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -114,7 +114,7 @@ for (int x = 0; x < MAX_IIO_STACK; ++x) { const STACK_RES *ri; ri = &hob->PlatformData.IIO_resource[socket].StackRes[x]; - if (!is_iio_stack_res(ri)) + if (!stack_needs_resource_alloc(ri)) continue; assert(info->no_of_stacks < (CONFIG_MAX_SOCKET * MAX_IIO_STACK)); memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES)); -- To view, visit https://review.coreboot.org/c/coreboot/+/78327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 Gerrit-Change-Number: 78327 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: device/device.h: Rename pci_domain_scan_bus
by Arthur Heymans (Code Review) 12 Oct '23

12 Oct '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78326?usp=email ) Change subject: device/device.h: Rename pci_domain_scan_bus ...................................................................... device/device.h: Rename pci_domain_scan_bus On all targets the domain works as a host bridge. Xeon-sp code intends to feature multiple host bridges below a domain, hence rename the function to pci_host_bridge_scan_bus. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I4e65fdbaf0b42c5f4f62297a60d818d299d76f73 --- M src/device/pci_device.c M src/include/device/device.h M src/mainboard/emulation/qemu-aarch64/mainboard.c M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i440bx/northbridge.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/ironlake/northbridge.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/x4x/northbridge.c M src/soc/amd/common/block/data_fabric/domain.c M src/soc/amd/stoneyridge/chip.c M src/soc/cavium/cn81xx/ecam0.c M src/soc/intel/alderlake/chip.c M src/soc/intel/apollolake/chip.c M src/soc/intel/baytrail/chip.c M src/soc/intel/braswell/chip.c M src/soc/intel/broadwell/northbridge.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/denverton_ns/chip.c M src/soc/intel/elkhartlake/chip.c M src/soc/intel/jasperlake/chip.c M src/soc/intel/meteorlake/chip.c M src/soc/intel/skylake/chip.c M src/soc/intel/tigerlake/chip.c M src/soc/mediatek/mt8195/soc.c M src/soc/qualcomm/sc7280/soc.c 31 files changed, 32 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/78326/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 60339e3..21b4352 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1662,7 +1662,7 @@ * * @param dev Pointer to the domain. */ -void pci_domain_scan_bus(struct device *dev) +void pci_host_bridge_scan_bus(struct device *dev) { struct bus *link = dev->link_list; pci_scan_bus(link, PCI_DEVFN(0, 0), 0xff); diff --git a/src/include/device/device.h b/src/include/device/device.h index bbad3c7..68e2622 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -272,7 +272,7 @@ extern struct device_operations default_dev_ops_root; void pci_domain_read_resources(struct device *dev); void pci_domain_set_resources(struct device *dev); -void pci_domain_scan_bus(struct device *dev); +void pci_host_bridge_scan_bus(struct device *dev); void mmconf_resource(struct device *dev, unsigned long index); diff --git a/src/mainboard/emulation/qemu-aarch64/mainboard.c b/src/mainboard/emulation/qemu-aarch64/mainboard.c index 481745f..a655989 100644 --- a/src/mainboard/emulation/qemu-aarch64/mainboard.c +++ b/src/mainboard/emulation/qemu-aarch64/mainboard.c @@ -49,5 +49,5 @@ struct device_operations qemu_aarch64_pci_domain_ops = { .read_resources = qemu_aarch64_domain_read_resources, .set_resources = pci_domain_set_resources, - .scan_bus = pci_domain_scan_bus, + .scan_bus = pci_host_bridge_scan_bus, }; diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 5d24c5b..5fe12e7 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -230,7 +230,7 @@ static struct device_operations pci_domain_ops = { .read_resources = cpu_pci_domain_read_resources, .set_resources = cpu_pci_domain_set_resources, - .scan_bus = pci_domain_scan_bus, + .scan_bus = pci_host_bridge_scan_bus, #if CONFIG(GENERATE_SMBIOS_TABLES) .get_smbios_data = qemu_get_smbios_data, #endif diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 0c389d5..bafe5a5 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -840,7 +840,7 @@ static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = pci_domain_set_resources, - .scan_bus = pci_domain_scan_bus, + .scan_bus = pci_host_bridge_scan_bus, .acpi_name = domain_acpi_name, }; diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index b51b2ab..65a0212 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -58,7 +58,7 @@ struct device_operations e7505_pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, - .scan_bus = pci_domain_scan_bus, + .scan_bus = pci_host_bridge_scan_bus, .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 07dba86..4bddf20 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -183,7 +183,7 @@ .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, .init = mch_domain_init, - .scan_bus = pci_domain_scan_bus, + .scan_bus = pci_host_bridge_scan_bus, .write_acpi_tables = northbridge_write_acpi_tables, .acpi_fill_ssdt = pci_domain_ssdt, .acpi_name = northbridge_acpi_name, diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 73afe07..ef5b9e9 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -36,7 +36,7 @@ struct device_operations haswell_pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, - .scan_bus = pci_domain_scan_bus, + .scan_bus = pci_host_bridge_scan_bus, .acpi_name = northbridge_acpi_name, .write_acpi_tables = northbridge_write_acpi_tables, }; diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index bc6541f..0670f72 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -69,7 +69,7 @@ static struct device_operations pci_domain_ops = { .read_resources = i440bx_domain_read_resources, .set_resources = pci_domain_set_resources, - .scan_bus = pci_domain_scan_bus, + .scan_bus = pci_host_bridge_scan_bus, }; static int get_cpu_count(void) diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 47c14f7..1dfcc40 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -97,7 +97,7 @@ struct device_operations i945_pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, - .scan_bus = pci_domain_scan_bus, + .scan_bus = pci_host_bridge_scan_bus, .acpi_name = northbridge_acpi_name, }; diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index 8c434aa..74ddee2 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -71,7 +71,7 @@ struct device_operations ironlake_pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, - .scan_bus = pci_domain_scan_bus, + .scan_bus = pci_host_bridge_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = northbridge_acpi_name, #endif diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 7689d34..a23a0d5 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -137,7 +137,7 @@ .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, .init = mch_domain_init, - .scan_bus = pci_domain_scan_bus, + .scan_bus = pci_host_bridge_scan_bus, .acpi_fill_ssdt = generate_cpu_entries, .acpi_name = northbridge_acpi_name, }; diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index ee4ddc5..9511cc3 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -55,7 +55,7 @@ struct device_operations sandybridge_pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, - .scan_bus = pci_domain_scan_bus, + .scan_bus = pci_host_bridge_scan_bus, .write_acpi_tables = northbridge_write_acpi_tables, .acpi_name = northbridge_acpi_name, }; diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index a3e1bd2..12a7a40 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -111,7 +111,7 @@ .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, .init = mch_domain_init, - .scan_bus = pci_domain_scan_bus, + .scan_bus = pci_host_bridge_scan_bus, .write_acpi_tables = northbridge_write_acpi_tables, .acpi_fill_ssdt = generate_cpu_entries, .acpi_name = northbridge_acpi_name, diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c index 01fad99..4ec52fc 100644 --- a/src/soc/amd/common/block/data_fabric/domain.c +++ b/src/soc/amd/common/block/data_fabric/domain.c @@ -28,12 +28,12 @@ /* Set bus first number of PCI root */ domain->link_list->secondary = bus; - /* subordinate needs to be the same as secondary before pci_domain_scan_bus call. */ + /* subordinate needs to be the same as secondary before pci_host_bridge_scan_bus call. */ domain->link_list->subordinate = bus; /* Tell allocator about maximum PCI bus number in domain */ domain->link_list->max_subordinate = limit; - pci_domain_scan_bus(domain); + pci_host_bridge_scan_bus(domain); } static void print_df_mmio_outside_of_cpu_mmio_error(unsigned int reg) diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index eaa0e9a..09cede3 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -84,7 +84,7 @@ .read_resources = domain_read_resources, .set_resources = pci_domain_set_resources, .enable_resources = domain_enable_resources, - .scan_bus = pci_domain_scan_bus, + .scan_bus = pci_host_bridge_scan_bus, .acpi_name = soc_acpi_name, }; diff --git a/src/soc/cavium/cn81xx/ecam0.c b/src/soc/cavium/cn81xx/ecam0.c index e789fd8..d02e884 100644 --- a/src/soc/cavium/cn81xx/ecam0.c +++ b/src/soc/cavium/cn81xx/ecam0.c @@ -312,5 +312,5 @@ struct device_operations pci_domain_ops_ecam0 = { .read_resources = ecam0_read_resources, .init = ecam0_init, - .scan_bus = pci_domain_scan_bus, + .scan_bus = pci_host_bridge_scan_bus, }; diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 8b32b96..0639157 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -248,7 +248,7 @@ static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, - .scan_bus = &pci_domain_scan_bus, + .scan_bus = &pci_host_bridge_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = &soc_acpi_name, .acpi_fill_ssdt = ssdt_set_above_4g_pci, diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 37b3186..07c2637 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -202,7 +202,7 @@ static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, - .scan_bus = pci_domain_scan_bus, + .scan_bus = pci_host_bridge_scan_bus, .acpi_name = &soc_acpi_name, .acpi_fill_ssdt = ssdt_set_above_4g_pci, }; diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index 1f72dc4..592e178 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -11,7 +11,7 @@ static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, - .scan_bus = pci_domain_scan_bus, + .scan_bus = pci_host_bridge_scan_bus, }; static struct device_operations cpu_bus_ops = { diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index e2ee0a9..ce394d0 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -13,7 +13,7 @@ static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, - .scan_bus = pci_domain_scan_bus, + .scan_bus = pci_host_bridge_scan_bus, }; static struct device_operations cpu_bus_ops = { diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c index d3c899e..6525275 100644 --- a/src/soc/intel/broadwell/northbridge.c +++ b/src/soc/intel/broadwell/northbridge.c @@ -400,7 +400,7 @@ struct device_operations broadwell_pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, - .scan_bus = &pci_domain_scan_bus, + .scan_bus = &pci_host_bridge_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = &northbridge_write_acpi_tables, #endif diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 19b8c39..0ece32c 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -174,7 +174,7 @@ static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, - .scan_bus = &pci_domain_scan_bus, + .scan_bus = &pci_host_bridge_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = &soc_acpi_name, .acpi_fill_ssdt = ssdt_set_above_4g_pci, diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index 3d974a2..1a4341e 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -109,7 +109,7 @@ static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, - .scan_bus = &pci_domain_scan_bus, + .scan_bus = &pci_host_bridge_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = &soc_acpi_name, #endif diff --git a/src/soc/intel/elkhartlake/chip.c b/src/soc/intel/elkhartlake/chip.c index 4d61c3b..20e46c0 100644 --- a/src/soc/intel/elkhartlake/chip.c +++ b/src/soc/intel/elkhartlake/chip.c @@ -132,7 +132,7 @@ static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, - .scan_bus = &pci_domain_scan_bus, + .scan_bus = &pci_host_bridge_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = &soc_acpi_name, .acpi_fill_ssdt = ssdt_set_above_4g_pci, diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c index e51a601..c049163f 100644 --- a/src/soc/intel/jasperlake/chip.c +++ b/src/soc/intel/jasperlake/chip.c @@ -139,7 +139,7 @@ static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, - .scan_bus = &pci_domain_scan_bus, + .scan_bus = &pci_host_bridge_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = &soc_acpi_name, .acpi_fill_ssdt = ssdt_set_above_4g_pci, diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c index 954c32b..a1b1968 100644 --- a/src/soc/intel/meteorlake/chip.c +++ b/src/soc/intel/meteorlake/chip.c @@ -203,7 +203,7 @@ static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, - .scan_bus = &pci_domain_scan_bus, + .scan_bus = &pci_host_bridge_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = &soc_acpi_name, .acpi_fill_ssdt = ssdt_set_above_4g_pci, diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 70d12e4..8df1ad3 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -189,7 +189,7 @@ struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, - .scan_bus = &pci_domain_scan_bus, + .scan_bus = &pci_host_bridge_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = &soc_acpi_name, .acpi_fill_ssdt = ssdt_set_above_4g_pci, diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 15281c8..024763d 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -179,7 +179,7 @@ static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, - .scan_bus = &pci_domain_scan_bus, + .scan_bus = &pci_host_bridge_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = &soc_acpi_name, .acpi_fill_ssdt = ssdt_set_above_4g_pci, diff --git a/src/soc/mediatek/mt8195/soc.c b/src/soc/mediatek/mt8195/soc.c index 2ecc31e..5425695 100644 --- a/src/soc/mediatek/mt8195/soc.c +++ b/src/soc/mediatek/mt8195/soc.c @@ -53,7 +53,7 @@ static struct device_operations pci_domain_ops = { .read_resources = &mtk_pcie_domain_read_resources, .set_resources = &mtk_pcie_domain_set_resources, - .scan_bus = &pci_domain_scan_bus, + .scan_bus = &pci_host_bridge_scan_bus, .enable = &mtk_pcie_domain_enable, }; diff --git a/src/soc/qualcomm/sc7280/soc.c b/src/soc/qualcomm/sc7280/soc.c index 268f080..e6dbf21 100644 --- a/src/soc/qualcomm/sc7280/soc.c +++ b/src/soc/qualcomm/sc7280/soc.c @@ -10,7 +10,7 @@ static struct device_operations pci_domain_ops = { .read_resources = &qcom_pci_domain_read_resources, .set_resources = &pci_domain_set_resources, - .scan_bus = &pci_domain_scan_bus, + .scan_bus = &pci_host_bridge_scan_bus, .enable = &qcom_setup_pcie_host, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/78326?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e65fdbaf0b42c5f4f62297a60d818d299d76f73 Gerrit-Change-Number: 78326 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[main]: device/device.h: Rename busses for clarity
by Arthur Heymans (Code Review) 12 Oct '23

12 Oct '23

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/77402?usp=email ) Change subject: device/device.h: Rename busses for clarity ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/77402?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaac28057076f38dd1941639e48fdb8ff019e6b3b Gerrit-Change-Number: 77402 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: abandon

1 0

[XS] Change in coreboot[main]: device/device.h: Fix outdated comment
by Arthur Heymans (Code Review) 12 Oct '23

12 Oct '23

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/77429?usp=email ) Change subject: device/device.h: Fix outdated comment ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/77429?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I45d401e6a649f7fd26f45f6d671b4d95a5836a6c Gerrit-Change-Number: 77429 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: abandon

1 0

[L] Change in coreboot[main]: device/device.h: Drop multiple links
by Arthur Heymans (Code Review) 12 Oct '23

12 Oct '23

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/77400?usp=email ) Change subject: device/device.h: Drop multiple links ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/77400?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I47e027f83a35da21fda23c56bc3068ef9384c5b6 Gerrit-Change-Number: 77400 Gerrit-PatchSet: 15 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: abandon

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2023