coreboot-gerrit January 2023

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[S] Change in coreboot[master]: Documentation/acronyms: Add acronyms
by Maximilian Brune (Code Review) 04 Jan '23

04 Jan '23

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71665 ) Change subject: Documentation/acronyms: Add acronyms ...................................................................... Documentation/acronyms: Add acronyms Change-Id: I3d925516e48231b15d9aa78c5ef05b6de1ef42ca Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M Documentation/acronyms.md 1 file changed, 23 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/71665/1 diff --git a/Documentation/acronyms.md b/Documentation/acronyms.md index 6b88b4c..940766d 100644 --- a/Documentation/acronyms.md +++ b/Documentation/acronyms.md @@ -247,6 +247,7 @@ Graphics Card, Sound Card. DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load. + DMI - Direct Media Interface is a link/bus between CPU and PCH * DMI - [**Desktop Management Interface**](Desktop_Management_Interface) * DMIC - Digital Microphone * DMTF - [**Distributed Management Task Force**](https://en.wikipedia.org/wiki/Distributed_Management_Task_Force) @@ -377,6 +378,7 @@ Real Time Clock, and maybe a few other registers running. * GART - AMD: [**Graphics Address Remapping Table**](https://en.wikipedia.org/wiki/Graphics_address_remapping_table) * GATT - Graphics Aperture Translation Table +* GDT - [Global Descriptor Table](https://wiki.osdev.org/Global_Descriptor_Table) * GLK - Intel: [**Gemini Lake**](https://en.wikichip.org/wiki/intel/cores/gemini_lake) * GMA - Intel: [**Graphics Media Accelerator**](https://en.wikipedia.org/wiki/Intel_GMA) @@ -450,6 +452,7 @@ * IDSEL/AD - Initialization Device SELect/Address and Data. Each PCI slot has a signal called IDSEL. It is used to differentiate between the different slots. +* IDT - [Interrupt Descriptor Table](https://en.wikipedia.org/wiki/Interrupt_descriptor_table) * IF - AMD: [**Infinity Fabric**](https://en.wikipedia.org/wiki/HyperTransport#Infinity_Fabric) is a superset of AMD's earlier Hypertransport interconnect. @@ -561,6 +564,7 @@ * MCU - Memory Control Unit * MCU - [**MicroController Unit**](https://en.wikipedia.org/wiki/Microcontroller) +* MCTP - [**Management Component Transport Protocol**](https://en.wikipedia.org/wiki/Management_Component_Transport_Pr… * MDFIO - Intel: Multi-Die Fabric IO * MDN - AMD: Mendocino * ME - Intel: Management Engine @@ -611,6 +615,12 @@ * MTL - ARM: MHU Transport Layer * MTRR - [**Memory Type and Range Register**](http://en.wikipedia.org/wiki/MTRR) + allows to set the cache behaviour on memory memory access in x86. + basically it tells the CPU how to cache certain ranges of memory + (e.g. write-through, write-combining, write-back...). memory ranges are + specified over physical address ranges. In Linux they can be looked at + (and modified) easily with 'cat /proc/mtrr' [**Memory Type + and Range Register**](https://www.kernel.org/doc/html/v5.19/x86/pat.html) ## N @@ -664,7 +674,8 @@ * PAT - [**Page Attribute Table**](https://en.wikipedia.org/wiki/Page_attribute_table) This can be used independently or in combination with MTRR to setup memory type - access ranges. Allows more finely-grained control than MTRR. + access ranges. Allows more finely-grained control than MTRR. compared to MTRR + which set's memory types by physicall address ranges, PAT set's them at Page level * PAT - Intel: [**Performance Acceleration Technology**](https://en.wikipedia.org/wiki/Performance_acceleration_techno… * PATA - Parallel Advanced Technology Attachment - A renaming of ATA @@ -858,6 +869,7 @@ * SEEP - Serial EEPROM (Electrically Erasable Programmable Read-Only Memory) * SEV - AMD: Secure Encrypted Virtualization +* SF - Snoop Filter * Shadow RAM - RAM which content is copied from ROM residing at the same address for speedup purposes. * Shim - A small piece of code whose only purpose is to act as an -- To view, visit https://review.coreboot.org/c/coreboot/+/71665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d925516e48231b15d9aa78c5ef05b6de1ef42ca Gerrit-Change-Number: 71665 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: device/xhci: Add functions to work with resource pointers
by build bot (Jenkins) (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Robert Zieba, Raul Rangel, Karthik Ramasubramanian. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69914 ) Change subject: device/xhci: Add functions to work with resource pointers ...................................................................... Patch Set 8: Verified+1 (2 comments) File src/device/xhci_resource.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167658): https://review.coreboot.org/c/coreboot/+/69914/comment/16d8c3cc_96a5e137 PS8, Line 18: enum cb_err xhci_resource_for_each_ext_cap(const struct resource *res, void *context, that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167658): https://review.coreboot.org/c/coreboot/+/69914/comment/b73253fc_6bb5a18c PS8, Line 95: enum cb_err xhci_resource_for_each_supported_usb_cap( that open brace { should be on the previous line -- To view, visit https://review.coreboot.org/c/coreboot/+/69914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5a74f9529d5dc6031ec968ef5f40a9cad5ffbc4 Gerrit-Change-Number: 69914 Gerrit-PatchSet: 8 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 04 Jan 2023 18:46:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/cezanne: Set up SoC-specific XHCI definitions
by Robert Zieba (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Robert Zieba, Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Martin Roth, Fred Reitberger, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67939 to look at the new patch set (#16). Change subject: soc/amd/cezanne: Set up SoC-specific XHCI definitions ...................................................................... soc/amd/cezanne: Set up SoC-specific XHCI definitions Set up SoC-specific XHCI defines and enable SOC_AMD_COMMON_BLOCK_XHCI. BRANCH=guybrush BUG=b:186792595 TEST=builds Signed-off-by: Robert Zieba <robertzieba(a)google.com> Change-Id: I15e9c06cd38ac858b861a4d19626664704af7541 --- M src/soc/amd/cezanne/Kconfig A src/soc/amd/cezanne/include/soc/xhci.h 2 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/67939/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/67939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15e9c06cd38ac858b861a4d19626664704af7541 Gerrit-Change-Number: 67939 Gerrit-PatchSet: 16 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: cpu/x86/smm: Add PCI resource store functionality
by Robert Zieba (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Arthur Heymans, Robert Zieba, Raul Rangel, Nico Huber, Angel Pons, Karthik Ramasubramanian, Felix Held. Hello Arthur Heymans, build bot (Jenkins), Martin Roth, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67931 to look at the new patch set (#15). Change subject: cpu/x86/smm: Add PCI resource store functionality ...................................................................... cpu/x86/smm: Add PCI resource store functionality In certain cases data within protected memmory areas like SMRAM could be leaked or modified if an attacker remaps PCI BARs to point within that area. Add support to the existing SMM runtime to allow storing PCI resources in SMRAM and then later retrieving them. BRANCH=guybrush BUG=b:186792595 TEST=builds Signed-off-by: Robert Zieba <robertzieba(a)google.com> Change-Id: I23fb1e935dd1b89f1cc5c834cc2025f0fe5fda37 --- M src/cpu/x86/Kconfig M src/cpu/x86/smm/Makefile.inc A src/cpu/x86/smm/pci_resource_store.c M src/cpu/x86/smm/smm_module_handler.c M src/cpu/x86/smm/smm_module_loader.c M src/include/cpu/x86/smm.h 6 files changed, 143 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/67931/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/67931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23fb1e935dd1b89f1cc5c834cc2025f0fe5fda37 Gerrit-Change-Number: 67931 Gerrit-PatchSet: 15 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: ec/google/chromeec: Add retimer flag for mux device
by Robert Zieba (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Caveh Jalali, Prashant Malani, Boris Mittelberg. Robert Zieba has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71663 ) Change subject: ec/google/chromeec: Add retimer flag for mux device ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/71663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I754323236d2912777b63cede0fce2ccf7882cfea Gerrit-Change-Number: 71663 Gerrit-PatchSet: 1 Gerrit-Owner: Prashant Malani <pmalani(a)chromium.org> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Prashant Malani <pmalani(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Wed, 04 Jan 2023 18:44:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: src/soc/intel: Add in-code documentation
by Maximilian Brune (Code Review) 04 Jan '23

04 Jan '23

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71664 ) Change subject: src/soc/intel: Add in-code documentation ...................................................................... src/soc/intel: Add in-code documentation Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Iaf88f34cedd09e2461bb05050392e178ec84d5d0 --- M src/soc/intel/alderlake/chip.h M src/soc/intel/common/block/include/intelblocks/meminit.h M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 3 files changed, 15 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/71664/1 diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 82493a7..8deeb96 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -152,8 +152,8 @@ }; enum ddi_port_flags { - DDI_ENABLE_DDC = 1 << 0, - DDI_ENABLE_HPD = 1 << 1, + DDI_ENABLE_DDC = 1 << 0, // Display Data Channel + DDI_ENABLE_HPD = 1 << 1, // Hot Plug Detect }; /* diff --git a/src/soc/intel/common/block/include/intelblocks/meminit.h b/src/soc/intel/common/block/include/intelblocks/meminit.h index 3ebf536..a4fb9fa 100644 --- a/src/soc/intel/common/block/include/intelblocks/meminit.h +++ b/src/soc/intel/common/block/include/intelblocks/meminit.h @@ -22,8 +22,8 @@ /* Different memory topologies supported by the platform. */ enum mem_topology { - MEM_TOPO_MEMORY_DOWN = BIT(0), - MEM_TOPO_DIMM_MODULE = BIT(1), + MEM_TOPO_MEMORY_DOWN = BIT(0), // memory is soldered onto board + MEM_TOPO_DIMM_MODULE = BIT(1), // memory is composed of DIMM modules MEM_TOPO_MIXED = MEM_TOPO_MEMORY_DOWN | MEM_TOPO_DIMM_MODULE, }; diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index a4e3500..be7c5f9 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -15,6 +15,7 @@ enum pcie_rp_flags { PCIE_RP_HOTPLUG = (1 << 0), + /* PCIE RP Latency Tolerance Report */ PCIE_RP_LTR = (1 << 1), /* PCIE RP Advanced Error Report */ PCIE_RP_AER = (1 << 2), -- To view, visit https://review.coreboot.org/c/coreboot/+/71664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf88f34cedd09e2461bb05050392e178ec84d5d0 Gerrit-Change-Number: 71664 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/common/block: Add Intel VGA early graphics support
by Jérémy Compostella (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Bora Guvendik, Zhixing Ma, Anil Kumar K, Hannah Williams, Cliff Huang, Tarun Tuli, Nico Huber, Michał Żygowski, Subrata Banik, Paul Menzel, Arthur Heymans, Swift Geek (Sebastian Grzywna). Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70299 ) Change subject: soc/intel/common/block: Add Intel VGA early graphics support ...................................................................... Patch Set 26: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/70299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4ad1215e5fadd0adc1271b6bd6ddb0ea258cb5b Gerrit-Change-Number: 70299 Gerrit-PatchSet: 26 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Comment-Date: Wed, 04 Jan 2023 18:15:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: ec/google/chromeec: Add retimer flag for mux device
by Prashant Malani (Code Review) 04 Jan '23

04 Jan '23

Prashant Malani has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71663 ) Change subject: ec/google/chromeec: Add retimer flag for mux device ...................................................................... ec/google/chromeec: Add retimer flag for mux device Not all ports have retimers. Add a property to denote that a particular port has a retimer (instead of assuming that all ports have retimers). BUG=b:263964979 TEST=Verified on guybrush; SSDT shows retimer-switch on port1 when device tree is updated accordingly. Change-Id: I754323236d2912777b63cede0fce2ccf7882cfea Signed-off-by: Prashant Malani <pmalani(a)chromium.org> --- M src/ec/google/chromeec/mux/conn/chip.h M src/ec/google/chromeec/mux/conn/conn.c 2 files changed, 28 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/71663/1 diff --git a/src/ec/google/chromeec/mux/conn/chip.h b/src/ec/google/chromeec/mux/conn/chip.h index 953b625..fd0ccf8 100644 --- a/src/ec/google/chromeec/mux/conn/chip.h +++ b/src/ec/google/chromeec/mux/conn/chip.h @@ -5,9 +5,11 @@ struct ec_google_chromeec_mux_conn_config { /* When set to true, this signifies that the mux device - * is used as a Type-C mode switch in addition to - * a retimer switch. */ + * is used as a Type-C mode switch. */ bool mode_switch; + /* When set to true, this signifies that the mux device + * is used as a Type-C retimer switch. */ + bool retimer_switch; }; #endif /* EC_GOOGLE_CHROMEEC_MUX_CONN_CHIP_H */ diff --git a/src/ec/google/chromeec/mux/conn/conn.c b/src/ec/google/chromeec/mux/conn/conn.c index cb7478a..e179c33 100644 --- a/src/ec/google/chromeec/mux/conn/conn.c +++ b/src/ec/google/chromeec/mux/conn/conn.c @@ -24,9 +24,14 @@ acpigen_write_name_integer("_ADR", dev->path.generic.id); - if (config && config->mode_switch) { + if (config) { struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); - acpi_dp_add_integer(dsd, "mode-switch", 1); + + if (config->mode_switch) + acpi_dp_add_integer(dsd, "mode-switch", 1); + if (config->retimer_switch) + acpi_dp_add_integer(dsd, "retimer-switch", 1); + acpi_dp_write(dsd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/71663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I754323236d2912777b63cede0fce2ccf7882cfea Gerrit-Change-Number: 71663 Gerrit-PatchSet: 1 Gerrit-Owner: Prashant Malani <pmalani(a)chromium.org> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/common/block/early_graphics: Introduce a 200 ms delay
by Jérémy Compostella (Code Review) 04 Jan '23

04 Jan '23

Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71656 ) Change subject: soc/intel/common/block/early_graphics: Introduce a 200 ms delay ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/71656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de1 Gerrit-Change-Number: 71656 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Jan 2023 18:15:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common/block/early_graphics: Introduce a 200 ms delay
by build bot (Jenkins) (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Jérémy Compostella. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71656 ) Change subject: soc/intel/common/block/early_graphics: Introduce a 200 ms delay ...................................................................... Patch Set 2: Verified-1 (1 comment) File src/soc/intel/common/block/graphics/early_graphics.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167652): https://review.coreboot.org/c/coreboot/+/71656/comment/97136ecb_507da3eb PS2, Line 48: udelay(200000); long udelay - prefer mdelay; see arch/arm/include/asm/delay.h -- To view, visit https://review.coreboot.org/c/coreboot/+/71656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de1 Gerrit-Change-Number: 71656 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Wed, 04 Jan 2023 18:15:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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2016

2015

2014

2013

coreboot-gerrit January 2023