coreboot-gerrit January 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/brya/var/omnigul: use RPL FSP headers
by Felix Held (Code Review) 06 Jan '23

06 Jan '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71702 ) Change subject: mb/google/brya/var/omnigul: use RPL FSP headers ...................................................................... mb/google/brya/var/omnigul: use RPL FSP headers To support an RPL SKU on omnigul, omnigul must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for omnigul so that it will use the RPL FSP headers for omnigul. BUG=b:263060849 BRANCH=None TEST=FW_NAME=omnigul emerge-brya intel-rplfsp coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Change-Id: If3cfbaeff0472012cb8f30ed8fff3bf5cac23f85 Signed-off-by: jamie_chen <jamie_chen(a)compal.corp-partner.google.com> Change-Id: I6a0afb04bea4940e13ea62c2cd0a09500b8b5335 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71702 Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/Kconfig.name 1 file changed, 25 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Dtrain Hsu: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index e5cfe3a..37610f3 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -321,3 +321,4 @@ config BOARD_GOOGLE_OMNIGUL bool "-> Omnigul" select BOARD_GOOGLE_BASEBOARD_BRYA + select SOC_INTEL_RAPTORLAKE -- To view, visit https://review.coreboot.org/c/coreboot/+/71702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a0afb04bea4940e13ea62c2cd0a09500b8b5335 Gerrit-Change-Number: 71702 Gerrit-PatchSet: 2 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/nissa/var/craask: Modify GPIOs for NVMe
by Felix Held (Code Review) 06 Jan '23

06 Jan '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71170 ) ( 10 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/nissa/var/craask: Modify GPIOs for NVMe ...................................................................... mb/google/nissa/var/craask: Modify GPIOs for NVMe Modify NVMe clkreq pin to GPP_D7 from GPP_D6.The design change is for commonality of GPIO settings. To reserve craask GPIO table and add craaskneto/craaskino's NVMe GPIO setting. In the change, clkreq# will be 2 and clksrc is still 1. BUG=b:259211172 TEST=Verify on reworked craask DUT to boot up from NVMe. Change-Id: If45c1a87144d5370b1ca2525295fb7947639362f Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71170 Reviewed-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/craask/fw_config.c M src/mainboard/google/brya/variants/craask/gpio.c M src/mainboard/google/brya/variants/craask/overridetree.cb 3 files changed, 30 insertions(+), 39 deletions(-) Approvals: build bot (Jenkins): Verified Ren Kuo: Looks good to me, but someone else must approve Dtrain Hsu: Looks good to me, approved Reka Norman: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/craask/fw_config.c b/src/mainboard/google/brya/variants/craask/fw_config.c index d667910..937e90d 100644 --- a/src/mainboard/google/brya/variants/craask/fw_config.c +++ b/src/mainboard/google/brya/variants/craask/fw_config.c @@ -50,39 +50,16 @@ static const struct pad_config nvme_disable_pads[] = { /* B4 : SSD_PERST_L */ PAD_NC_LOCK(GPP_B4, NONE, LOCK_CONFIG), + /* D7 : SSD_CLKREQ_ODL */ + PAD_NC(GPP_D7, NONE), /* D11 : EN_PP3300_SSD */ PAD_NC_LOCK(GPP_D11, NONE, LOCK_CONFIG), /* E17 : SSD_PLN_L */ PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG), - /* - * Note: don't disable GPP_D6 = SSD_CLKREQ_ODL, since this is used as - * WWAN_EN on LTE variants. - */ -}; - -/* - * GPP_D6 is used as WWAN_EN on LTE variants and SSD_CLKREQ_ODL on NVMe - * variants (there is no craask variant supporting both LTE and NVMe). - * In craask/gpio.c, it's set to WWAN_EN since this needs to be done in - * bootblock. So we override it to SSD_CLKREQ_ODL here for NVMe variants. - */ -static const struct pad_config nvme_enable_pads[] = { - /* D6 : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */ - PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), }; void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { - /* - * Since GPP_D6 is used as WWAN_EN on LTE variants and SSD_CLKREQ_ODL on - * NVMe variants, we don't support both together. If there's a variant - * using both in the future, this GPIO handling will need to be updated. - */ - if (fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE)) && - fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) { - printk(BIOS_ERR, "LTE and NVMe together is not supported on craask\n"); - } - if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { printk(BIOS_INFO, "Disable LTE-related GPIO pins on craask.\n"); gpio_padbased_override(padbased_table, lte_disable_pads, @@ -107,16 +84,7 @@ ARRAY_SIZE(stylus_disable_pads)); } - if (!fw_config_is_provisioned() || - fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) { - /* - * Note: this must be done after lte_disable_pads, otherwise - * GPP_D6 will be disabled again. - */ - printk(BIOS_INFO, "Enable NVMe SSD GPIO pins.\n"); - gpio_padbased_override(padbased_table, nvme_enable_pads, - ARRAY_SIZE(nvme_enable_pads)); - } else { + if (fw_config_is_provisioned() && !fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) { printk(BIOS_INFO, "Disable NVMe SSD GPIO pins.\n"); gpio_padbased_override(padbased_table, nvme_disable_pads, ARRAY_SIZE(nvme_disable_pads)); diff --git a/src/mainboard/google/brya/variants/craask/gpio.c b/src/mainboard/google/brya/variants/craask/gpio.c index 5d0db35..bebc8d2 100644 --- a/src/mainboard/google/brya/variants/craask/gpio.c +++ b/src/mainboard/google/brya/variants/craask/gpio.c @@ -13,8 +13,8 @@ PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG), /* D6 : WWAN_EN */ PAD_CFG_GPO(GPP_D6, 1, DEEP), - /* D7 : WLAN_CLKREQ_ODL */ - PAD_NC(GPP_D7, NONE), + /* D7 : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* D11 : EN_PP3300_SSD */ PAD_CFG_GPO_LOCK(GPP_D11, 1, LOCK_CONFIG), /* E17 : SSD_PLN_L */ diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb index 1a733fb..19cf876 100644 --- a/src/mainboard/google/brya/variants/craask/overridetree.cb +++ b/src/mainboard/google/brya/variants/craask/overridetree.cb @@ -447,10 +447,10 @@ probe SD_CARD SD_GL9750S end device ref pcie_rp9 on - # Enable NVMe SSD PCIe 9-12 using clk 1 + # Enable NVMe SSD PCIe 9-12 using clk 2 register "pch_pcie_rp[PCH_RP(9)]" = "{ .clk_src = 1, - .clk_req = 1, + .clk_req = 2, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end -- To view, visit https://review.coreboot.org/c/coreboot/+/71170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If45c1a87144d5370b1ca2525295fb7947639362f Gerrit-Change-Number: 71170 Gerrit-PatchSet: 15 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: post_codes: Add an optional "Prefix" to post codes sent to IO
by Felix Held (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Matt DeVillier, Martin Roth, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71712 ) Change subject: post_codes: Add an optional "Prefix" to post codes sent to IO ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: wouldn't be adding 4 bit post code support to coreboot and then adding a coreboot-specific prefix in the upper byte be a better solution? sure, that will only work with 4 byte post code support, but at least on current AMD platforms that's the standard -- To view, visit https://review.coreboot.org/c/coreboot/+/71712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8a518b8ecd2a00b7a7e2109036bc9b7ea8de0cf Gerrit-Change-Number: 71712 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 06 Jan 2023 11:42:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/morgana: update morgana cpuid
by Felix Held (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Jason Glenesk, ritul guru, Matt DeVillier, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71689 ) Change subject: soc/amd/morgana: update morgana cpuid ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/soc/amd/morgana/include/soc/cpu.h: https://review.coreboot.org/c/coreboot/+/71689/comment/32264b0e_333ed3b5 PS1, Line 6: #define MORGANA_A0_CPUID 0x00A70F80 the hex digits should be lower case -- To view, visit https://review.coreboot.org/c/coreboot/+/71689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaad72a6b964f4b2ab572733694def88e30888a3 Gerrit-Change-Number: 71689 Gerrit-PatchSet: 1 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 06 Jan 2023 11:40:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/morgana: update max number of cpus to 16 for morgana
by Felix Held (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Jason Glenesk, ritul guru, Matt DeVillier, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71688 ) Change subject: soc/amd/morgana: update max number of cpus to 16 for morgana ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71688 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5169a900345e2aabefcf1e2c249ee4bce6dc8fc5 Gerrit-Change-Number: 71688 Gerrit-PatchSet: 3 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 06 Jan 2023 11:38:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: drivers/amd: Update to use defined post codes
by Felix Held (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Martin L Roth, Matt DeVillier, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71591 ) Change subject: drivers/amd: Update to use defined post codes ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d5700534c07e89b3908a2e6b827db919a48795d Gerrit-Change-Number: 71591 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 06 Jan 2023 11:38:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/amd: Update pademelon to eval board
by Felix Held (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Martin L Roth, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71580 ) Change subject: mb/amd: Update pademelon to eval board ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5038935bb6f2ba530ea6e16ac84c1746efec8e48 Gerrit-Change-Number: 71580 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 06 Jan 2023 11:37:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Disable Intel TXT
by Sridhar Siricilla (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Angel Pons, Lean Sheng Tan, Werner Zeh. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71575 ) Change subject: soc/intel/alderlake: Disable Intel TXT ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/alderlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/71575/comment/2852b358_228c726b PS4, Line 140: unsupported `unsupported` in the context of CPU capability? -- To view, visit https://review.coreboot.org/c/coreboot/+/71575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dd7c5492a5f45eef0dd9e836cc2da1844c78919 Gerrit-Change-Number: 71575 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 06 Jan 2023 11:22:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: security/intel/txt: Helper function to disable TXT
by Sridhar Siricilla (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Angel Pons, Lean Sheng Tan, Werner Zeh. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71574 ) Change subject: security/intel/txt: Helper function to disable TXT ...................................................................... Patch Set 3: Code-Review+2 (1 comment) File src/include/cpu/x86/msr.h: https://review.coreboot.org/c/coreboot/+/71574/comment/7a5d5154_83a1a4e1 PS3, Line 84: 0x2e6 nit:one more tab to align with earlier line? -- To view, visit https://review.coreboot.org/c/coreboot/+/71574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27f613428e82a1dd924172eab853d2ce9c32b473 Gerrit-Change-Number: 71574 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 06 Jan 2023 11:19:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: post_codes: Add an optional "Prefix" to post codes sent to IO
by Paul Menzel (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Matt DeVillier, Martin Roth, Fred Reitberger, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71712 ) Change subject: post_codes: Add an optional "Prefix" to post codes sent to IO ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Looks useful to me. -- To view, visit https://review.coreboot.org/c/coreboot/+/71712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8a518b8ecd2a00b7a7e2109036bc9b7ea8de0cf Gerrit-Change-Number: 71712 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 06 Jan 2023 11:18:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit January 2023