coreboot-gerrit January 2023

coreboot-gerrit@coreboot.org

1 participants
5879 discussions

[M] Change in coreboot[master]: soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM
by Kapil Porwal (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Sean Rhodes, Tarun Tuli, Martin L Roth, Subrata Banik, Matt DeVillier, John Zhao, Tim Wawrzynczak. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64561 ) Change subject: soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM ...................................................................... Patch Set 10: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/64561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac31d37c0873f41f7b14e1051fe214466d1ebdd8 Gerrit-Change-Number: 64561 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Fri, 06 Jan 2023 11:16:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/starlabs/starbook/adl: Enable the PchHdaAudioLinkHdaEnable UPD
by Sean Rhodes (Code Review) 06 Jan '23

06 Jan '23

Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71716 ) Change subject: mb/starlabs/starbook/adl: Enable the PchHdaAudioLinkHdaEnable UPD ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/71716 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id53c9a6495d584c374e89b76d1fd4258654b6f95 Gerrit-Change-Number: 71716 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Fri, 06 Jan 2023 11:14:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/intel/common: Fix cpu index calculation
by Kapil Porwal (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Subrata Banik, Ravishankar Sarawadi, Sridhar Siricilla, Angel Pons, Lean Sheng Tan, Werner Zeh, Sukumar Ghorai, Raj Astekar. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70751 ) Change subject: soc/intel/common: Fix cpu index calculation ...................................................................... Patch Set 8: Code-Review+2 (1 comment) Patchset: PS8: Seems like it is fixing _CPC as well. Output of `grep "GCPC \[0x03\]" SSDT.dsl` Before this patch: ``` GCPC [0x03] = 0x0C \_SB.CP00.GCPC [0x03] = 0x0C \_SB.CP00.GCPC [0x03] = 0x0F \_SB.CP00.GCPC [0x03] = 0x0C \_SB.CP00.GCPC [0x03] = 0x0C \_SB.CP00.GCPC [0x03] = 0x0C \_SB.CP00.GCPC [0x03] = 0x0C \_SB.CP00.GCPC [0x03] = 0x0C \_SB.CP00.GCPC [0x03] = 0x0C \_SB.CP00.GCPC [0x03] = 0x0C \_SB.CP00.GCPC [0x03] = 0x0C \_SB.CP00.GCPC [0x03] = 0x0C \_SB.CP00.GCPC [0x03] = 0x0C \_SB.CP00.GCPC [0x03] = 0x0C \_SB.CP00.GCPC [0x03] = 0x0C \_SB.CP00.GCPC [0x03] = 0x0C \_SB.CP00.GCPC [0x03] = 0x0C \_SB.CP00.GCPC [0x03] = 0x0C \_SB.CP00.GCPC [0x03] = 0x0C \_SB.CP00.GCPC [0x03] = 0x0C ``` After this patch: ``` GCPC [0x03] = 0x0C \_SB.CP00.GCPC [0x03] = 0x0C \_SB.CP00.GCPC [0x03] = 0x0C \_SB.CP00.GCPC [0x03] = 0x0C \_SB.CP00.GCPC [0x03] = 0x0C \_SB.CP00.GCPC [0x03] = 0x0C \_SB.CP00.GCPC [0x03] = 0x0C \_SB.CP00.GCPC [0x03] = 0x0C \_SB.CP00.GCPC [0x03] = 0x0F \_SB.CP00.GCPC [0x03] = 0x0F \_SB.CP00.GCPC [0x03] = 0x0F \_SB.CP00.GCPC [0x03] = 0x0F \_SB.CP00.GCPC [0x03] = 0x0F \_SB.CP00.GCPC [0x03] = 0x0F \_SB.CP00.GCPC [0x03] = 0x0F \_SB.CP00.GCPC [0x03] = 0x0F \_SB.CP00.GCPC [0x03] = 0x0F \_SB.CP00.GCPC [0x03] = 0x0F \_SB.CP00.GCPC [0x03] = 0x0F \_SB.CP00.GCPC [0x03] = 0x0F ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/70751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69e5e6231dd18b43d439340aaed50eb9edeca3b7 Gerrit-Change-Number: 70751 Gerrit-PatchSet: 8 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Comment-Date: Fri, 06 Jan 2023 11:10:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: security/intel/txt: Create Intel TXT lib with helper functions
by Sridhar Siricilla (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Angel Pons, Lean Sheng Tan, Werner Zeh. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71573 ) Change subject: security/intel/txt: Create Intel TXT lib with helper functions ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff5b4e705e18cbaf181b4c71bfed368c3ed047ed Gerrit-Change-Number: 71573 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 06 Jan 2023 11:08:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/alderlake: Hook up PchHdaAudioLinkHdaEnable to devicetree
by Sean Rhodes (Code Review) 06 Jan '23

06 Jan '23

Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71715 ) Change subject: soc/intel/alderlake: Hook up PchHdaAudioLinkHdaEnable to devicetree ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/71715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f27f41a4a4b3844a65d45d36aba37c3af1050a0 Gerrit-Change-Number: 71715 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Fri, 06 Jan 2023 11:00:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/google/nissa: Disable stage cache
by Subrata Banik (Code Review) 06 Jan '23

06 Jan '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71677 ) Change subject: mb/google/nissa: Disable stage cache ...................................................................... mb/google/nissa: Disable stage cache Although S3 is supported on nissa, only S0ix is used on user devices, so we can ignore optimising the S3 resume time. Disable the stage cache to save boot time at the cost on increasing the S3 resume time. Boot time is reduced by ~6 ms. This is mostly from adding postcar to the stage cache, which is slow since TSEG is not cached in romstage. Adding ramstage and FSP-S take negligible time. The S3 resume time is increased by ~89 ms total from loading and decompressing ramstage and FSP-S. Boot time before: 3:after RAM initialization 573,295 (931) 4:end of romstage 583,569 (10,274) 100:start of postcar 587,729 (4,160) Boot time after: 3:after RAM initialization 571,527 (830) 4:end of romstage 575,712 (4,185) 100:start of postcar 579,866 (4,153) S3 resume time before: 101:end of postcar 368,904 (0) 10:start of ramstage 369,165 (260) 971:loading FSP-S 385,742 (16,577) 30:device enumeration 407,105 (21,362) S3 resume time after: 101:end of postcar 363,101 (0) 8:starting to load ramstage 363,101 (0) 15:starting LZMA decompress (ignore for x86) 382,802 (19,701) 16:finished LZMA decompress (ignore for x86) 431,620 (48,817) 9:finished loading ramstage 431,850 (230) 10:start of ramstage 431,927 (76) 971:loading FSP-S 448,357 (16,430) 17:starting LZ4 decompress (ignore for x86) 474,420 (26,062) 18:finished LZ4 decompress (ignore for x86) 474,627 (206) BUG=b:247940538, b:192032803 TEST=Boot and S3 suspend/resume on craask Change-Id: I8015dc0808ee19cac67c2a6573d52781c6120e8c Signed-off-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71677 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 57 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sridhar Siricilla: Looks good to me, approved Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 9f0c223..112c7df 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -68,6 +68,7 @@ select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768 select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS select DRIVERS_INTEL_ISH + select MAINBOARD_DISABLE_STAGE_CACHE select MEMORY_SOLDERDOWN select SOC_INTEL_ALDERLAKE_PCH_N select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW -- To view, visit https://review.coreboot.org/c/coreboot/+/71677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8015dc0808ee19cac67c2a6573d52781c6120e8c Gerrit-Change-Number: 71677 Gerrit-PatchSet: 5 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: Kconfig: Allow mainboards to disable stage cache
by Subrata Banik (Code Review) 06 Jan '23

06 Jan '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71676 ) Change subject: Kconfig: Allow mainboards to disable stage cache ...................................................................... Kconfig: Allow mainboards to disable stage cache On recent Intel ChromeOS devices, although S3 is still supported, only S0ix is used on user devices, so we don't care about optimising S3 resume time. Disabing the stage cache saves boot time at the cost of increasing the S3 resume time. E.g. on nissa this reduces boot time by 6 ms and increases S3 resume time by 89 ms. BUG=b:247940538, b:192032803 TEST=Build and boot on nissa with MAINBOARD_DISABLE_STAGE_CACHE selected. Change-Id: I243a401a112a12bb824c5447a8fecc99500f7739 Signed-off-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71676 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/Kconfig 1 file changed, 32 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Sridhar Siricilla: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/Kconfig b/src/Kconfig index f16b53c..f68553c 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -347,7 +347,7 @@ choice prompt "Stage Cache for ACPI S3 resume" - default NO_STAGE_CACHE if !HAVE_ACPI_RESUME + default NO_STAGE_CACHE if !HAVE_ACPI_RESUME || MAINBOARD_DISABLE_STAGE_CACHE default TSEG_STAGE_CACHE if SMM_TSEG config NO_STAGE_CACHE @@ -380,6 +380,13 @@ endchoice +config MAINBOARD_DISABLE_STAGE_CACHE + bool + help + Selected by mainboards which wish to disable the stage cache. + E.g. mainboards which don't use S3 resume in the field may wish to + disable it to save boot time at the cost of increasing S3 resume time. + config UPDATE_IMAGE bool "Update existing coreboot.rom image" help -- To view, visit https://review.coreboot.org/c/coreboot/+/71676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I243a401a112a12bb824c5447a8fecc99500f7739 Gerrit-Change-Number: 71676 Gerrit-PatchSet: 4 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: soc/intel/alderlake: Disable Intel TXT
by Subrata Banik (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Tarun Tuli, Angel Pons, Lean Sheng Tan, Werner Zeh. Hello build bot (Jenkins), Tarun Tuli, Angel Pons, Arthur Heymans, Lean Sheng Tan, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/71575 to look at the new patch set (#4). Change subject: soc/intel/alderlake: Disable Intel TXT ...................................................................... soc/intel/alderlake: Disable Intel TXT This patch makes the call into TXT lib in order to disable the TXT. TEST=Able to perform disable_txt and unlock memory which helped to access VGA framebuffer prior calling into FSP-M. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I9dd7c5492a5f45eef0dd9e836cc2da1844c78919 --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/romstage/romstage.c 2 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/71575/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/71575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dd7c5492a5f45eef0dd9e836cc2da1844c78919 Gerrit-Change-Number: 71575 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: security/intel/txt: Helper function to disable TXT
by build bot (Jenkins) (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Tarun Tuli, Angel Pons, Lean Sheng Tan, Werner Zeh. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71574 ) Change subject: security/intel/txt: Helper function to disable TXT ...................................................................... Patch Set 3: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167793): https://review.coreboot.org/c/coreboot/+/71574/comment/82c415da_3cf2d490 PS3, Line 6: Possible long commit subject (prefer a maximum 65 characters) -- To view, visit https://review.coreboot.org/c/coreboot/+/71574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27f613428e82a1dd924172eab853d2ce9c32b473 Gerrit-Change-Number: 71574 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 06 Jan 2023 10:29:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/alderlake: Disable Intel TXT
by Subrata Banik (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Tarun Tuli, Angel Pons, Lean Sheng Tan, Werner Zeh. Hello build bot (Jenkins), Tarun Tuli, Angel Pons, Arthur Heymans, Lean Sheng Tan, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/71575 to look at the new patch set (#3). Change subject: soc/intel/alderlake: Disable Intel TXT ...................................................................... soc/intel/alderlake: Disable Intel TXT This patch makes the call into TXT lib in order to disable the TXT. TEST=Able to perform disable_txt and unlock memory which helped to access VGA framebuffer prior calling into FSP-M. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I9dd7c5492a5f45eef0dd9e836cc2da1844c78919 --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/romstage/romstage.c 2 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/71575/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/71575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dd7c5492a5f45eef0dd9e836cc2da1844c78919 Gerrit-Change-Number: 71575 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2023