coreboot-gerrit January 2023

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[M] Change in coreboot[master]: vc/amd/*,soc/amd/*: Add SVC call to get HSP Secure State
by Jon Murphy (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Jon Murphy has uploaded a new patch set (#2) to the change originally created by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/71207 ) Change subject: vc/amd/*,soc/amd/*: Add SVC call to get HSP Secure State ...................................................................... vc/amd/*,soc/amd/*: Add SVC call to get HSP Secure State Add an SVC call to get the state of Hardware Security Processor (HSP) in AMD SoCs. This SVC call will be used from PSP verstage to get and report HSP state. BUG=b:198711349 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the HSP state is read and reported in the firmware logs. Change-Id: I7fe3363d308a80cc09e6bdadd8d0bb1d67f7d2bf Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/common/block/psp/Kconfig M src/soc/amd/mendocino/psp_verstage/svc.c M src/soc/amd/mendocino/psp_verstage/svc.h M src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h M src/vendorcode/amd/fsp/mendocino/include/bl_uapp/bl_syscall_public.h M src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h 6 files changed, 67 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/71207/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71207 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7fe3363d308a80cc09e6bdadd8d0bb1d67f7d2bf Gerrit-Change-Number: 71207 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Name of user not set #1004763 Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/amd/mandolin/Makefile.inc: Remove path to non-existent directory
by Felix Held (Code Review) 06 Jan '23

06 Jan '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71255 ) Change subject: mb/amd/mandolin/Makefile.inc: Remove path to non-existent directory ...................................................................... mb/amd/mandolin/Makefile.inc: Remove path to non-existent directory Fix: cc1: error: src/mainboard/amd/mandolin/acpi: No such file or directory [-Werror=missing-include-dirs] Change-Id: Ifbe6fda12088ddf51b6a177116aa542dbacc7672 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71255 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/mandolin/Makefile.inc 1 file changed, 16 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/amd/mandolin/Makefile.inc b/src/mainboard/amd/mandolin/Makefile.inc index 1a4740e..6d11ee0 100644 --- a/src/mainboard/amd/mandolin/Makefile.inc +++ b/src/mainboard/amd/mandolin/Makefile.inc @@ -31,5 +31,3 @@ printf "coreboot has been built without the Microchip EC.\n" printf "Do not flash this image. Your Mandolin's power button\n" printf "will not respond when you press it.\n\n" - -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/71255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbe6fda12088ddf51b6a177116aa542dbacc7672 Gerrit-Change-Number: 71255 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/amd/bilby/Makefile.inc: Remove path to non-existent directory
by Felix Held (Code Review) 06 Jan '23

06 Jan '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71254 ) Change subject: mb/amd/bilby/Makefile.inc: Remove path to non-existent directory ...................................................................... mb/amd/bilby/Makefile.inc: Remove path to non-existent directory Fix: cc1: error: src/mainboard/amd/bilby/acpi: No such file or directory [-Werror=missing-include-dirs] Change-Id: Ie167cd362b55e38870d26a877d8181b2b07b8639 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71254 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/bilby/Makefile.inc 1 file changed, 16 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/amd/bilby/Makefile.inc b/src/mainboard/amd/bilby/Makefile.inc index b7a1c23..1a812ad 100644 --- a/src/mainboard/amd/bilby/Makefile.inc +++ b/src/mainboard/amd/bilby/Makefile.inc @@ -13,5 +13,3 @@ ifeq ($(CONFIG_BOARD_AMD_BILBY),y) APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_bilby.bin endif - -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/71254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie167cd362b55e38870d26a877d8181b2b07b8639 Gerrit-Change-Number: 71254 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/amd/bilby/Makefile.inc: Remove path to non-existent directory
by Felix Held (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Jason Glenesk, Fred Reitberger, Elyes Haouas. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71254 ) Change subject: mb/amd/bilby/Makefile.inc: Remove path to non-existent directory ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie167cd362b55e38870d26a877d8181b2b07b8639 Gerrit-Change-Number: 71254 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 06 Jan 2023 13:13:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/amd/mandolin/Makefile.inc: Remove path to non-existent directory
by Felix Held (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Jason Glenesk, Fred Reitberger, Elyes Haouas. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71255 ) Change subject: mb/amd/mandolin/Makefile.inc: Remove path to non-existent directory ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbe6fda12088ddf51b6a177116aa542dbacc7672 Gerrit-Change-Number: 71255 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 06 Jan 2023 13:12:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: drivers/amd: Update to use defined post codes
by Fred Reitberger (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Martin L Roth, Matt DeVillier. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71591 ) Change subject: drivers/amd: Update to use defined post codes ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d5700534c07e89b3908a2e6b827db919a48795d Gerrit-Change-Number: 71591 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 06 Jan 2023 12:50:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: Switch from LZMA to LZ4 compression for ramstage
by Paul Menzel (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Martin L Roth, Jason Nien, Martin Roth. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71675 ) Change subject: mb/google/skyrim: Switch from LZMA to LZ4 compression for ramstage ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Thank you for adding all the data to the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/71675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedde6fc2db9d702c0ff2b0081e7baa254ac6699f Gerrit-Change-Number: 71675 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 06 Jan 2023 12:31:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Kconfig: Add option to compress ramstage with LZ4
by Paul Menzel (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Martin L Roth, Julius Werner, Arthur Heymans, Martin Roth, Fred Reitberger. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71673 ) Change subject: Kconfig: Add option to compress ramstage with LZ4 ...................................................................... Patch Set 3: Code-Review+1 (1 comment) File src/Kconfig: https://review.coreboot.org/c/coreboot/+/71673/comment/eb1893f5_2f30ebcf PS3, Line 192: Compress ramstage with LZ4. Add a blank line below? (Or remove it, as it’s the string already?) -- To view, visit https://review.coreboot.org/c/coreboot/+/71673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27dd1a8def024e0efd466cef9ffd9ca71717486a Gerrit-Change-Number: 71673 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 06 Jan 2023 12:28:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/meteorlake: Enable support for common IRQ block
by Felix Held (Code Review) 06 Jan '23

06 Jan '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71113 ) Change subject: soc/intel/meteorlake: Enable support for common IRQ block ...................................................................... soc/intel/meteorlake: Enable support for common IRQ block Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch allows MTL boards to dynamically assign PCI IRQs. This means not relying on FSP defaults, which eliminates the problem of PCI IRQs interfering with GPIO IRQs routed to the same IRQ, when both have selected IO-APIC routing. BUG=none TEST=Build and boot to google/rex. Check dmesg and make sure that there is no regression. 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0x00000011 Package (0x04) ==> 0x0006FFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x0007FFFF, 0x00, 0x00, 0x00000013 Package (0x04) ==> 0x0007FFFF, 0x01, 0x00, 0x00000014 Package (0x04) ==> 0x0007FFFF, 0x02, 0x00, 0x00000015 Package (0x04) ==> 0x0007FFFF, 0x03, 0x00, 0x00000016 Package (0x04) ==> 0x0008FFFF, 0x00, 0x00, 0x00000017 Package (0x04) ==> 0x000BFFFF, 0x00, 0x00, 0x00000013 Package (0x04) ==> 0x000DFFFF, 0x00, 0x00, 0x00000014 Package (0x04) ==> 0x000DFFFF, 0x01, 0x00, 0x00000015 Package (0x04) ==> 0x0010FFFF, 0x00, 0x00, 0x00000016 Package (0x04) ==> 0x0010FFFF, 0x01, 0x00, 0x00000017 Package (0x04) ==> 0x0012FFFF, 0x00, 0x00, 0x00000018 Package (0x04) ==> 0x0012FFFF, 0x01, 0x00, 0x00000019 Package (0x04) ==> 0x0012FFFF, 0x02, 0x00, 0x00000011 Package (0x04) ==> 0x0014FFFF, 0x01, 0x00, 0x00000012 Package (0x04) ==> 0x0014FFFF, 0x00, 0x00, 0x0000001A Package (0x04) ==> 0x0014FFFF, 0x02, 0x00, 0x00000013 Package (0x04) ==> 0x0015FFFF, 0x00, 0x00, 0x0000001B Package (0x04) ==> 0x0015FFFF, 0x01, 0x00, 0x0000001C Package (0x04) ==> 0x0015FFFF, 0x02, 0x00, 0x0000001D Package (0x04) ==> 0x0015FFFF, 0x03, 0x00, 0x0000001E Package (0x04) ==> 0x0016FFFF, 0x00, 0x00, 0x00000014 Package (0x04) ==> 0x0016FFFF, 0x01, 0x00, 0x00000015 Package (0x04) ==> 0x0016FFFF, 0x02, 0x00, 0x00000016 Package (0x04) ==> 0x0016FFFF, 0x03, 0x00, 0x00000017 Package (0x04) ==> 0x0017FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0019FFFF, 0x00, 0x00, 0x0000001F Package (0x04) ==> 0x0019FFFF, 0x01, 0x00, 0x00000020 Package (0x04) ==> 0x0019FFFF, 0x02, 0x00, 0x00000021 Package (0x04) ==> 0x001CFFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x001CFFFF, 0x01, 0x00, 0x00000011 Package (0x04) ==> 0x001CFFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x001CFFFF, 0x03, 0x00, 0x00000013 Package (0x04) ==> 0x001EFFFF, 0x00, 0x00, 0x00000014 Package (0x04) ==> 0x001EFFFF, 0x01, 0x00, 0x00000015 Package (0x04) ==> 0x001EFFFF, 0x02, 0x00, 0x00000022 Package (0x04) ==> 0x001EFFFF, 0x03, 0x00, 0x00000023 Package (0x04) ==> 0x001FFFFF, 0x01, 0x00, 0x00000017 Package (0x04) ==> 0x001FFFFF, 0x02, 0x00, 0x00000014 Package (0x04) ==> 0x001FFFFF, 0x03, 0x00, 0x00000015 Package (0x04) ==> 0x001FFFFF, 0x00, 0x00, 0x00000016 Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I013cd5faab6f425ab1af91fe2a36ac3b8aeef443 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71113 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/meteorlake/Kconfig D src/soc/intel/meteorlake/acpi/pci_irqs.asl M src/soc/intel/meteorlake/acpi/southbridge.asl M src/soc/intel/meteorlake/chip.c M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/meteorlake/include/soc/irq.h M src/soc/intel/meteorlake/include/soc/pci_devs.h 7 files changed, 409 insertions(+), 164 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 4d69566..a612846 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -67,6 +67,7 @@ select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_COMMON_BLOCK_IOE_P2SB + select SOC_INTEL_COMMON_BLOCK_IRQ select SOC_INTEL_COMMON_BLOCK_MEMINIT select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_COMMON_BLOCK_PMC_EPOC diff --git a/src/soc/intel/meteorlake/acpi/pci_irqs.asl b/src/soc/intel/meteorlake/acpi/pci_irqs.asl deleted file mode 100644 index 70e9f3d..0000000 --- a/src/soc/intel/meteorlake/acpi/pci_irqs.asl +++ /dev/null @@ -1,155 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -Name (PICP, Package () { - /* D31 */ - Package(){0x001FFFFF, 0, 0, 16 }, - Package(){0x001FFFFF, 1, 0, 17 }, - Package(){0x001FFFFF, 2, 0, 18 }, - Package(){0x001FFFFF, 3, 0, 19 }, - /* D30 */ - Package(){0x001EFFFF, 0, 0, 16 }, - Package(){0x001EFFFF, 1, 0, 17 }, - Package(){0x001EFFFF, 2, 0, 27 }, - Package(){0x001EFFFF, 3, 0, 28 }, - /* D28 */ - Package(){0x001CFFFF, 0, 0, 16 }, - Package(){0x001CFFFF, 1, 0, 17 }, - Package(){0x001CFFFF, 2, 0, 18 }, - Package(){0x001CFFFF, 3, 0, 19 }, - /* D25 */ - Package(){0x0019FFFF, 0, 0, 29 }, - Package(){0x0019FFFF, 1, 0, 30 }, - Package(){0x0019FFFF, 2, 0, 31 }, - /* D23 */ - Package(){0x0017FFFF, 0, 0, 16 }, - /* D22 */ - Package(){0x0016FFFF, 0, 0, 16 }, - Package(){0x0016FFFF, 1, 0, 17 }, - Package(){0x0016FFFF, 2, 0, 18 }, - Package(){0x0016FFFF, 3, 0, 19 }, - /* D21 */ - Package(){0x0015FFFF, 0, 0, 32 }, - Package(){0x0015FFFF, 1, 0, 33 }, - Package(){0x0015FFFF, 2, 0, 34 }, - Package(){0x0015FFFF, 3, 0, 35 }, - /* D20 */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - /* D18 */ - Package(){0x0012FFFF, 0, 0, 26 }, - Package(){0x0012FFFF, 1, 0, 37 }, - Package(){0x0012FFFF, 2, 0, 25 }, - /* D16 */ - Package(){0x0010FFFF, 0, 0, 23 }, - Package(){0x0010FFFF, 1, 0, 22 }, - /* D13 */ - Package(){0x000DFFFF, 0, 0, 16 }, - Package(){0x000DFFFF, 1, 0, 17 }, - /* D11 */ - Package(){0x000BFFFF, 0, 0, 16 }, - /* D8 */ - Package(){0x0008FFFF, 0, 0, 16 }, - /* D7 */ - Package(){0x0007FFFF, 0, 0, 16 }, - Package(){0x0007FFFF, 1, 0, 17 }, - Package(){0x0007FFFF, 2, 0, 18 }, - Package(){0x0007FFFF, 3, 0, 19 }, - /* D6 */ - Package(){0x0006FFFF, 0, 0, 16 }, - Package(){0x0006FFFF, 1, 0, 17 }, - Package(){0x0006FFFF, 2, 0, 18 }, - Package(){0x0006FFFF, 3, 0, 19 }, - /* D5 */ - Package(){0x0005FFFF, 0, 0, 16 }, - /* D4 */ - Package(){0x0004FFFF, 0, 0, 16 }, - /* D2 */ - Package(){0x0002FFFF, 0, 0, 16 }, - /* D1 */ - Package(){0x0001FFFF, 0, 0, 16 }, - Package(){0x0001FFFF, 1, 0, 17 }, - Package(){0x0001FFFF, 2, 0, 18 }, - Package(){0x0001FFFF, 3, 0, 19 }, -}) - -Name (PICN, Package () { - /* D31 */ - Package(){0x001FFFFF, 0, 0, 11 }, - Package(){0x001FFFFF, 1, 0, 10 }, - Package(){0x001FFFFF, 2, 0, 11 }, - Package(){0x001FFFFF, 3, 0, 11 }, - /* D30 */ - Package(){0x001EFFFF, 0, 0, 11 }, - Package(){0x001EFFFF, 1, 0, 10 }, - Package(){0x001EFFFF, 2, 0, 11 }, - Package(){0x001EFFFF, 3, 0, 11 }, - /* D28 */ - Package(){0x001CFFFF, 0, 0, 11 }, - Package(){0x001CFFFF, 1, 0, 10 }, - Package(){0x001CFFFF, 2, 0, 11 }, - Package(){0x001CFFFF, 3, 0, 11 }, - /* D25 */ - Package(){0x0019FFFF, 0, 0, 11 }, - Package(){0x0019FFFF, 1, 0, 10 }, - Package(){0x0019FFFF, 2, 0, 11 }, - /* D23 */ - Package(){0x0017FFFF, 0, 0, 11 }, - /* D22 */ - Package(){0x0016FFFF, 0, 0, 11 }, - Package(){0x0016FFFF, 1, 0, 10 }, - Package(){0x0016FFFF, 2, 0, 11 }, - Package(){0x0016FFFF, 3, 0, 11 }, - /* D21 */ - Package(){0x0015FFFF, 0, 0, 11 }, - Package(){0x0015FFFF, 1, 0, 10 }, - Package(){0x0015FFFF, 2, 0, 11 }, - Package(){0x0015FFFF, 3, 0, 11 }, - /* D20 */ - Package(){0x0014FFFF, 0, 0, 11 }, - Package(){0x0014FFFF, 1, 0, 10 }, - Package(){0x0014FFFF, 2, 0, 11 }, - /* D18 */ - Package(){0x0012FFFF, 0, 0, 11 }, - Package(){0x0012FFFF, 1, 0, 10 }, - Package(){0x0012FFFF, 2, 0, 11 }, - /* D16 */ - Package(){0x0010FFFF, 0, 0, 11 }, - Package(){0x0010FFFF, 1, 0, 10 }, - /* D13 */ - Package(){0x000DFFFF, 0, 0, 11 }, - /* D11 */ - Package(){0x000BFFFF, 0, 0, 11 }, - /* D8 */ - Package(){0x0008FFFF, 0, 0, 11 }, - /* D7 */ - Package(){0x0007FFFF, 0, 0, 11 }, - Package(){0x0007FFFF, 1, 0, 10 }, - Package(){0x0007FFFF, 2, 0, 11 }, - Package(){0x0007FFFF, 3, 0, 11 }, - /* D6 */ - Package(){0x0006FFFF, 0, 0, 11 }, - Package(){0x0006FFFF, 1, 0, 10 }, - Package(){0x0006FFFF, 2, 0, 11 }, - Package(){0x0006FFFF, 3, 0, 11 }, - /* D5 */ - Package(){0x0005FFFF, 0, 0, 11 }, - /* D4 */ - Package(){0x0004FFFF, 0, 0, 11 }, - /* D2 */ - Package(){0x0002FFFF, 0, 0, 11 }, - /* D1 */ - Package(){0x0001FFFF, 0, 0, 11 }, - Package(){0x0001FFFF, 1, 0, 10 }, - Package(){0x0001FFFF, 2, 0, 11 }, - Package(){0x0001FFFF, 3, 0, 11 }, -}) - -Method (_PRT) -{ - If (PICM) { - Return (^PICP) - } Else { - Return (^PICN) - } -} diff --git a/src/soc/intel/meteorlake/acpi/southbridge.asl b/src/soc/intel/meteorlake/acpi/southbridge.asl index 448cbf5..6ecadbb 100644 --- a/src/soc/intel/meteorlake/acpi/southbridge.asl +++ b/src/soc/intel/meteorlake/acpi/southbridge.asl @@ -5,9 +5,6 @@ #include <soc/itss.h> #include <soc/pcr_ids.h> -/* PCI IRQ assignment */ -#include "pci_irqs.asl" - /* PCR access */ #include <soc/intel/common/acpi/pcr.asl> diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c index 041b16d..332c0f8 100644 --- a/src/soc/intel/meteorlake/chip.c +++ b/src/soc/intel/meteorlake/chip.c @@ -7,6 +7,7 @@ #include <intelblocks/acpi.h> #include <intelblocks/cfg.h> #include <intelblocks/gpio.h> +#include <intelblocks/irq.h> #include <intelblocks/itss.h> #include <intelblocks/p2sb.h> #include <intelblocks/pcie_rp.h> @@ -151,6 +152,19 @@ pcie_rp_update_devicetree(get_pcie_rp_table()); } +static void cpu_fill_ssdt(const struct device *dev) +{ + if (!generate_pin_irq_map()) + printk(BIOS_ERR, "Failed to generate ACPI _PRT table!\n"); + + generate_cpu_entries(dev); +} + +static void cpu_set_north_irqs(struct device *dev) +{ + irq_program_non_pch(); +} + static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, @@ -164,8 +178,9 @@ static struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, + .enable_resources = cpu_set_north_irqs, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_fill_ssdt = generate_cpu_entries, + .acpi_fill_ssdt = cpu_fill_ssdt, #endif }; diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index d40779a..0cf221b 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -13,6 +13,7 @@ #include <fsp/util.h> #include <option.h> #include <intelblocks/cse.h> +#include <intelblocks/irq.h> #include <intelblocks/lpss.h> #include <intelblocks/mp_init.h> #include <intelblocks/systemagent.h> @@ -27,6 +28,7 @@ #include <soc/ramstage.h> #include <soc/soc_chip.h> #include <soc/soc_info.h> +#include <stdlib.h> #include <string.h> #include <types.h> @@ -39,6 +41,219 @@ #define DEF_DMVAL 15 #define DEF_DITOVAL 625 +static const struct slot_irq_constraints irq_constraints[] = { + { + .slot = PCI_DEV_SLOT_PCIE_3, + .fns = { + FIXED_INT_PIRQ(PCI_DEVFN_PCIE12, PCI_INT_A, PIRQ_A), + }, + }, + { + .slot = PCI_DEV_SLOT_IGD, + .fns = { + /* INTERRUPT_PIN is RO/0x01 */ + FIXED_INT_ANY_PIRQ(PCI_DEV_SLOT_IGD, PCI_INT_A), + }, + }, + { + .slot = PCI_DEV_SLOT_DPTF, + .fns = { + ANY_PIRQ(PCI_DEVFN_DPTF), + }, + }, + { + .slot = PCI_DEV_SLOT_IPU, + .fns = { + /* INTERRUPT_PIN is RO/0x01, and INTERRUPT_LINE is RW, + but S0ix fails when not set to 16 (b/193434192) */ + FIXED_INT_PIRQ(PCI_DEVFN_IPU, PCI_INT_A, PIRQ_A), + }, + }, + { + .slot = PCI_DEV_SLOT_PCIE_2, + .fns = { + FIXED_INT_PIRQ(PCI_DEVFN_PCIE9, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE10, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE11, PCI_INT_C, PIRQ_C), + }, + }, + { + .slot = PCI_DEV_SLOT_TBT, + .fns = { + ANY_PIRQ(PCI_DEVFN_TBT0), + ANY_PIRQ(PCI_DEVFN_TBT1), + ANY_PIRQ(PCI_DEVFN_TBT2), + ANY_PIRQ(PCI_DEVFN_TBT3), + }, + }, + { + .slot = PCI_DEV_SLOT_GNA, + .fns = { + /* INTERRUPT_PIN is RO/0x01 */ + FIXED_INT_ANY_PIRQ(PCI_DEVFN_GNA, PCI_INT_A), + }, + }, + { + .slot = PCI_DEV_SLOT_VPU, + .fns = { + /* INTERRUPT_PIN is RO/0x01 */ + FIXED_INT_ANY_PIRQ(PCI_DEVFN_VPU, PCI_INT_A), + }, + }, + { + .slot = PCI_DEV_SLOT_TCSS, + .fns = { + ANY_PIRQ(PCI_DEVFN_TCSS_XHCI), + ANY_PIRQ(PCI_DEVFN_TCSS_XDCI), + }, + }, + { + .slot = PCI_DEV_SLOT_THC, + .fns = { + ANY_PIRQ(PCI_DEVFN_THC0), + ANY_PIRQ(PCI_DEVFN_THC1), + }, + }, + { + .slot = PCI_DEV_SLOT_ISH, + .fns = { + DIRECT_IRQ(PCI_DEVFN_ISH), + DIRECT_IRQ(PCI_DEVFN_GSPI2), + ANY_PIRQ(PCI_DEVFN_UFS), + }, + }, + { + .slot = PCI_DEV_SLOT_XHCI, + .fns = { + ANY_PIRQ(PCI_DEVFN_XHCI), + DIRECT_IRQ(PCI_DEVFN_USBOTG), + ANY_PIRQ(PCI_DEVFN_CNVI_WIFI), + }, + }, + { + .slot = PCI_DEV_SLOT_SIO0, + .fns = { + DIRECT_IRQ(PCI_DEVFN_I2C0), + DIRECT_IRQ(PCI_DEVFN_I2C1), + DIRECT_IRQ(PCI_DEVFN_I2C2), + DIRECT_IRQ(PCI_DEVFN_I2C3), + }, + }, + { + .slot = PCI_DEV_SLOT_CSE, + .fns = { + ANY_PIRQ(PCI_DEVFN_CSE), + ANY_PIRQ(PCI_DEVFN_CSE_2), + ANY_PIRQ(PCI_DEVFN_CSE_IDER), + ANY_PIRQ(PCI_DEVFN_CSE_KT), + ANY_PIRQ(PCI_DEVFN_CSE_3), + ANY_PIRQ(PCI_DEVFN_CSE_4), + }, + }, + { + .slot = PCI_DEV_SLOT_SATA, + .fns = { + ANY_PIRQ(PCI_DEVFN_SATA), + }, + }, + { + .slot = PCI_DEV_SLOT_SIO1, + .fns = { + DIRECT_IRQ(PCI_DEVFN_I2C4), + DIRECT_IRQ(PCI_DEVFN_I2C5), + DIRECT_IRQ(PCI_DEVFN_UART2), + }, + }, + { + .slot = PCI_DEV_SLOT_PCIE_1, + .fns = { + FIXED_INT_PIRQ(PCI_DEVFN_PCIE1, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE2, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE3, PCI_INT_C, PIRQ_C), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE4, PCI_INT_D, PIRQ_D), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE5, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE6, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE7, PCI_INT_C, PIRQ_C), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE8, PCI_INT_D, PIRQ_D), + }, + }, + { + .slot = PCI_DEV_SLOT_SIO2, + .fns = { + /* UART0 shares an interrupt line with TSN0, so must use + a PIRQ */ + FIXED_INT_ANY_PIRQ(PCI_DEVFN_UART0, PCI_INT_A), + /* UART1 shares an interrupt line with TSN1, so must use + a PIRQ */ + FIXED_INT_ANY_PIRQ(PCI_DEVFN_UART1, PCI_INT_B), + DIRECT_IRQ(PCI_DEVFN_GSPI0), + DIRECT_IRQ(PCI_DEVFN_GSPI1), + }, + }, + { + .slot = PCI_DEV_SLOT_ESPI, + .fns = { + ANY_PIRQ(PCI_DEVFN_HDA), + ANY_PIRQ(PCI_DEVFN_SMBUS), + ANY_PIRQ(PCI_DEVFN_GBE), + /* INTERRUPT_PIN is RO/0x01 */ + FIXED_INT_ANY_PIRQ(PCI_DEVFN_NPK, PCI_INT_A), + }, + }, +}; + +bool is_pch_slot(unsigned int devfn) +{ + if (PCI_SLOT(devfn) >= MIN_PCH_SLOT) + return true; + const struct pcie_rp_group *group; + for (group = get_pcie_rp_table(); group->count; ++group) { + if (PCI_SLOT(devfn) == group->slot) + return true; + } + return false; +} + +static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count) +{ + const struct pci_irq_entry *entry = get_cached_pci_irqs(); + SI_PCH_DEVICE_INTERRUPT_CONFIG *config; + size_t pch_total = 0; + size_t cfg_count = 0; + + if (!entry) + return NULL; + + /* Count PCH devices */ + while (entry) { + if (is_pch_slot(entry->devfn)) + ++pch_total; + entry = entry->next; + } + + /* Convert PCH device entries to FSP format */ + config = calloc(pch_total, sizeof(*config)); + entry = get_cached_pci_irqs(); + while (entry) { + if (!is_pch_slot(entry->devfn)) { + entry = entry->next; + continue; + } + + config[cfg_count].Device = PCI_SLOT(entry->devfn); + config[cfg_count].Function = PCI_FUNC(entry->devfn); + config[cfg_count].IntX = (SI_PCH_INT_PIN)entry->pin; + config[cfg_count].Irq = entry->irq; + ++cfg_count; + + entry = entry->next; + } + + *out_count = cfg_count; + + return config; +} + /* * ME End of Post configuration * 0 - Disable EOP. @@ -442,6 +657,20 @@ s_cfg->VpuEnable = is_devfn_enabled(PCI_DEVFN_VPU); } +static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg, + const struct soc_intel_meteorlake_config *config) +{ + if (!assign_pci_irqs(irq_constraints, ARRAY_SIZE(irq_constraints))) + die("ERROR: Unable to assign PCI IRQs, and no _PRT table available\n"); + + size_t pch_count = 0; + const SI_PCH_DEVICE_INTERRUPT_CONFIG *upd_irqs = pci_irq_to_fsp(&pch_count); + + s_cfg->DevIntConfigPtr = (UINT32)((uintptr_t)upd_irqs); + s_cfg->NumOfDevIntConfig = pch_count; + printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n"); +} + static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg) { /* @@ -484,6 +713,7 @@ fill_fsps_misc_power_params, fill_fsps_ufs_params, fill_fsps_ai_params, + fill_fsps_irq_params, }; for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++) diff --git a/src/soc/intel/meteorlake/include/soc/irq.h b/src/soc/intel/meteorlake/include/soc/irq.h index edc09a1..59727a6 100644 --- a/src/soc/intel/meteorlake/include/soc/irq.h +++ b/src/soc/intel/meteorlake/include/soc/irq.h @@ -9,8 +9,4 @@ #define PCH_IRQ10 10 #define PCH_IRQ11 11 -#define LPSS_UART0_IRQ 16 -#define LPSS_UART1_IRQ 17 -#define LPSS_UART2_IRQ 31 - #endif diff --git a/src/soc/intel/meteorlake/include/soc/pci_devs.h b/src/soc/intel/meteorlake/include/soc/pci_devs.h index 9cea98e..5c584b0 100644 --- a/src/soc/intel/meteorlake/include/soc/pci_devs.h +++ b/src/soc/intel/meteorlake/include/soc/pci_devs.h @@ -221,7 +221,8 @@ #endif /* for common code */ -#define PCH_DEV_SLOT_CSE PCI_DEV_SLOT_CSE +#define MIN_PCH_SLOT PCI_DEV_SLOT_THC +#define PCH_DEV_SLOT_CSE PCI_DEV_SLOT_CSE #define PCH_DEVFN_CSE PCI_DEVFN_CSE #define PCH_DEV_CSE PCI_DEV_CSE #define PCH_DEV_SPI PCI_DEV_SPI -- To view, visit https://review.coreboot.org/c/coreboot/+/71113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I013cd5faab6f425ab1af91fe2a36ac3b8aeef443 Gerrit-Change-Number: 71113 Gerrit-PatchSet: 4 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: mb/google/brya/var/omnigul: use i2c1 for TPM
by Felix Held (Code Review) 06 Jan '23

06 Jan '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71703 ) Change subject: mb/google/brya/var/omnigul: use i2c1 for TPM ...................................................................... mb/google/brya/var/omnigul: use i2c1 for TPM This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the omnigul variant. BUG=b:263060849 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I42528d73a4f83bd409cb4a1bd51f2e4e82ee7804 Signed-off-by: jamie_chen <jamie_chen(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71703 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 20 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Dtrain Hsu: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 112c7df..c171f85 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -154,6 +154,7 @@ default 0x1 if BOARD_GOOGLE_GLADIOS default 0x1 if BOARD_GOOGLE_MARASOV default 0x1 if BOARD_GOOGLE_GAELIN + default 0x1 if BOARD_GOOGLE_OMNIGUL config DRIVER_TPM_I2C_ADDR hex -- To view, visit https://review.coreboot.org/c/coreboot/+/71703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42528d73a4f83bd409cb4a1bd51f2e4e82ee7804 Gerrit-Change-Number: 71703 Gerrit-PatchSet: 4 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit January 2023