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Change subject: soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM
......................................................................
Patch Set 10: Code-Review+2
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Change subject: soc/intel/meteorlake: Add support to configure package c-state demotion
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
@Sukumar, can you please check if C-state demotion is supported on MTL else, we need to disable this feature.
ref: https://review.coreboot.org/c/coreboot/+/65664/7/src/mainboard/google/brya/…
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Change subject: soc/intel/meteorlake: Set max Pkg C-states to Auto
......................................................................
Patch Set 1: Code-Review+2
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Hello Tarun Tuli, Reka Norman, Kapil Porwal, Ivy Jian, Eric Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/71695
to look at the new patch set (#2).
Change subject: mb/google/rex: Disable stage cache
......................................................................
mb/google/rex: Disable stage cache
This patch disables the stage cache to save boot time.
Note: S3 is not POR for Intel MTL mobile skus.
Boot time is reduced by ~8ms.
Boot time before:
4:end of romstage 1,391,225 (13,724)
100:start of postcar 1,403,339 (12,114)
Boot time after:
4:end of romstage 1,380,262 (5,618)
100:start of postcar 1,392,323 (12,060)
Change-Id: I9775fc628f345a514894f30435a374e2ffa057c1
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/rex/Kconfig
1 file changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/71695/2
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Hello build bot (Jenkins), Tarun Tuli, Angel Pons, Arthur Heymans, Lean Sheng Tan, Werner Zeh,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/alderlake: Disable Intel TXT
......................................................................
soc/intel/alderlake: Disable Intel TXT
This patch makes the call into TXT lib in order to disable the TXT.
TEST=Able to perform disable_txt and unlock memory which helped to
access VGA framebuffer prior calling into FSP-M.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I9dd7c5492a5f45eef0dd9e836cc2da1844c78919
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/romstage/romstage.c
2 files changed, 23 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/71575/5
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Change subject: security/intel/txt: Helper function to disable TXT
......................................................................
Patch Set 3:
(1 comment)
File src/include/cpu/x86/msr.h:
https://review.coreboot.org/c/coreboot/+/71574/comment/647418b3_8fee1df9
PS3, Line 84: 0x2e6
> nit:one more tab to align with earlier line?
I guess the alignment is actually proper the line before is register bit definition.
The IA32_xxx macros are all aligned with col 33.
Please check and confirm.
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Change subject: mb/google/rex: Disable stage cache
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167810):
https://review.coreboot.org/c/coreboot/+/71695/comment/a7ae321a_4a19bd5a
PS1, Line 15: Boot time before:
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167810):
https://review.coreboot.org/c/coreboot/+/71695/comment/011a5ef0_95031c37
PS1, Line 16: 4:end of romstage 1,391,225 (13,724)
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167810):
https://review.coreboot.org/c/coreboot/+/71695/comment/f553e444_dc3b06a1
PS1, Line 20: 4:end of romstage 1,380,262 (5,618)
Possible unwrapped commit description (prefer a maximum 72 chars per line)
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