coreboot-gerrit January 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/intel/alderlake: Disable Intel TXT based on `INTEL_TXT` config
by Subrata Banik (Code Review) 09 Jan '23

09 Jan '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71575 ) Change subject: soc/intel/alderlake: Disable Intel TXT based on `INTEL_TXT` config ...................................................................... soc/intel/alderlake: Disable Intel TXT based on `INTEL_TXT` config This patch makes the call into TXT lib in order to disable the TXT if SoC user haven't selected the `INTEL_TXT` config. Disabling TXT would be helpful to access VGA framebuffer prior calling into FSP-M. TEST=Able to perform disable_txt and unlock memory which helped to access VGA framebuffer prior calling into FSP-M. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I9dd7c5492a5f45eef0dd9e836cc2da1844c78919 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71575 Reviewed-by: Tarun Tuli <taruntuli(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/romstage/romstage.c 2 files changed, 30 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Tarun Tuli: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 1b2f695..132e812 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -73,6 +73,7 @@ select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select INTEL_GMA_OPREGION_2_1 + select INTEL_TXT_LIB select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_2 diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index 3ee83bd..b305806 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -19,6 +19,7 @@ #include <cpu/intel/cpu_ids.h> #include <timestamp.h> #include <string.h> +#include <security/intel/txt/txt.h> #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ @@ -135,6 +136,13 @@ smbus_common_init(); /* Initialize HECI interface */ cse_init(HECI1_BASE_ADDRESS); + /* + * Disable Intel TXT if `CPU is unsupported` or `SoC haven't selected the config`. + * + * It would help to access VGA framebuffer prior calling into FSP-M. + */ + if (!CONFIG(INTEL_TXT)) + disable_intel_txt(); if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE)) dbg_feature_cntrl_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/71575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dd7c5492a5f45eef0dd9e836cc2da1844c78919 Gerrit-Change-Number: 71575 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: security/intel/txt: Add helper function to disable TXT
by Subrata Banik (Code Review) 09 Jan '23

09 Jan '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71574 ) Change subject: security/intel/txt: Add helper function to disable TXT ...................................................................... security/intel/txt: Add helper function to disable TXT Add a function to disable TXT as per TXT BIOS spec Section 6.2.5. AP firmware can disable TXT if TXT fails or TPM is already enabled. On platforms with TXT disabled, the memory can be unlocked using MSR 0x2e6. TEST=Able to perform disable_txt on SoC SKUs with TXT enabled. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I27f613428e82a1dd924172eab853d2ce9c32b473 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71574 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/include/cpu/x86/msr.h M src/security/intel/txt/txt.h M src/security/intel/txt/txtlib.c 3 files changed, 51 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sridhar Siricilla: Looks good to me, approved Eric Lai: Looks good to me, approved Tarun Tuli: Looks good to me, approved diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 33eb457..d369972 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -81,6 +81,7 @@ #define MCA_STATUS_LO_ERRCODE_EXT_SH 16 #define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH) #define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0) +#define IA32_LT_UNLOCK_MEMORY 0x2e6 #define IA32_MC0_ADDR 0x402 #define IA32_MC_ADDR(bank) (IA32_MC0_ADDR + 4 * (bank)) #define IA32_MC0_MISC 0x403 diff --git a/src/security/intel/txt/txt.h b/src/security/intel/txt/txt.h index 64e507d..63e5bcd 100644 --- a/src/security/intel/txt/txt.h +++ b/src/security/intel/txt/txt.h @@ -30,5 +30,6 @@ /* Allow platform override to skip TXT lockdown, e.g. required for RAS error injection. */ bool skip_intel_txt_lockdown(void); const char *intel_txt_processor_error_type(uint8_t type); +void disable_intel_txt(void); #endif /* SECURITY_INTEL_TXT_H_ */ diff --git a/src/security/intel/txt/txtlib.c b/src/security/intel/txt/txtlib.c index 3ec2322..5478206 100644 --- a/src/security/intel/txt/txtlib.c +++ b/src/security/intel/txt/txtlib.c @@ -44,3 +44,29 @@ return (ecx & (CPUID_SMX | CPUID_VMX)) == (CPUID_SMX | CPUID_VMX); } + +static void unlock_txt_memory(void) +{ + msr_t msrval = {0}; + + wrmsr(IA32_LT_UNLOCK_MEMORY, msrval); +} + +void disable_intel_txt(void) +{ + /* Return if the CPU doesn't support TXT */ + if (!is_txt_cpu()) { + printk(BIOS_DEBUG, "Abort disabling TXT, as CPU is not TXT capable.\n"); + return; + } + + /* + * Memory is supposed to be locked if system is TXT capable + * As per TXT BIOS spec Section 6.2.5 unlock memory + * when security (TPM) is set and TXT is not enabled. + */ + if (!is_establishment_bit_asserted()) { + unlock_txt_memory(); + printk(BIOS_INFO, "TXT disabled successfully - Unlocked memory\n"); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/71574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27f613428e82a1dd924172eab853d2ce9c32b473 Gerrit-Change-Number: 71574 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts
by Subrata Banik (Code Review) 09 Jan '23

09 Jan '23

Attention is currently required from: Ashish Kumar Mishra, Wonkyu Kim, Ravishankar Sarawadi, Rizwan Qureshi, Angel Pons, Tarun Tuli, Jamie Ryu, Tim Wawrzynczak, Harsha B R, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Raj Astekar, Elyes Haouas. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66190 ) Change subject: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts ...................................................................... Patch Set 23: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/66190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e1a26d99e170311a89412f44b7cbb0430788f58 Gerrit-Change-Number: 66190 Gerrit-PatchSet: 23 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 09 Jan 2023 04:30:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts
by Subrata Banik (Code Review) 09 Jan '23

09 Jan '23

Attention is currently required from: Ashish Kumar Mishra, Wonkyu Kim, Ravishankar Sarawadi, Rizwan Qureshi, Angel Pons, Tarun Tuli, Jamie Ryu, Tim Wawrzynczak, Harsha B R, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Raj Astekar, Elyes Haouas. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66190 ) Change subject: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts ...................................................................... Patch Set 23: (1 comment) File src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/memory.c: https://review.coreboot.org/c/coreboot/+/66190/comment/799de222_bc557115 PS20, Line 16: .targets = {50, 30, 30, 30, 25}, > Removed these overridden values in coreboot (with patchset#23). Below is the values configured as part of FSP, > > [SPEW ] Updating Rcomp Targets: > [SPEW ] RcompTarget[RdOdt]: 60 > [SPEW ] RcompTarget[WrDS]: 30 > [SPEW ] RcompTarget[WrDSCmd]: 30 > [SPEW ] RcompTarget[WrDSCtl]: 30 > [SPEW ] RcompTarget[WrDSClk]: 25 thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/66190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e1a26d99e170311a89412f44b7cbb0430788f58 Gerrit-Change-Number: 66190 Gerrit-PatchSet: 23 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 09 Jan 2023 04:30:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Harsha B R <harsha.b.r(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts
by Harsha B R (Code Review) 09 Jan '23

09 Jan '23

Attention is currently required from: Ashish Kumar Mishra, Wonkyu Kim, Ravishankar Sarawadi, Rizwan Qureshi, Angel Pons, Tarun Tuli, Jamie Ryu, Subrata Banik, Tim Wawrzynczak, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Raj Astekar, Elyes Haouas. Harsha B R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66190 ) Change subject: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts ...................................................................... Patch Set 23: (1 comment) File src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/memory.c: https://review.coreboot.org/c/coreboot/+/66190/comment/33e0d5ad_2064f6c5 PS20, Line 16: .targets = {50, 30, 30, 30, 25}, > yes, it uses the below values for DDR5, […] Removed these overridden values in coreboot (with patchset#23). Below is the values configured as part of FSP, [SPEW ] Updating Rcomp Targets: [SPEW ] RcompTarget[RdOdt]: 60 [SPEW ] RcompTarget[WrDS]: 30 [SPEW ] RcompTarget[WrDSCmd]: 30 [SPEW ] RcompTarget[WrDSCtl]: 30 [SPEW ] RcompTarget[WrDSClk]: 25 -- To view, visit https://review.coreboot.org/c/coreboot/+/66190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e1a26d99e170311a89412f44b7cbb0430788f58 Gerrit-Change-Number: 66190 Gerrit-PatchSet: 23 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 09 Jan 2023 04:16:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Harsha B R <harsha.b.r(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Documentation/releases: Start getting ready for the 4.19 release
by Felix Singer (Code Review) 09 Jan '23

09 Jan '23

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[M] Change in coreboot[master]: Documentation/releases: Start getting ready for the 4.19 release
by Felix Singer (Code Review) 09 Jan '23

09 Jan '23

Attention is currently required from: Jason Glenesk, Martin L Roth, Angel Pons. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71590 ) Change subject: Documentation/releases: Start getting ready for the 4.19 release ...................................................................... Patch Set 3: (6 comments) File Documentation/releases/coreboot-4.19-relnotes.md: https://review.coreboot.org/c/coreboot/+/71590/comment/e75e39d1_5f0670be PS1, Line 13: relevent > typo: relev*a*nt Done https://review.coreboot.org/c/coreboot/+/71590/comment/1f596a07_63e9f873 PS1, Line 42: optoins > typo: options Done https://review.coreboot.org/c/coreboot/+/71590/comment/04bf2e39_947a3550 PS1, Line 46: > nit: remove one space Done https://review.coreboot.org/c/coreboot/+/71590/comment/f8eae743_735214ef PS1, Line 64: * AMD: Mayan for Morgana SoC : * GIGABYTE: GA-H61M-DS2 : * Google: Crystaldrift : * Google: Gladios : * Google: Marasov : * Google: Voltorb : * Intel: Meteorlake-P RVP : * Siemens: MC_EHL3 : * Star Labs: StarBook Mk VI (i3-1220P and i7-1260P) : * System76: darp8 : * System76: galp6 > nit: Please be consistent with the spacing after the colon: some lines have one space, whereas other […] Done https://review.coreboot.org/c/coreboot/+/71590/comment/0ebf6a7a_1eb06f7f PS1, Line 114: * src/soc/intel/xeon_sp/lbg > This isn't a new platform, it's just a result of restructuring the code as part of CB:70009. […] Done https://review.coreboot.org/c/coreboot/+/71590/comment/52583d91_59d85bd7 PS1, Line 110: New SoCs : ------------------- : : * src/soc/amd/glinda : * src/soc/intel/xeon_sp/lbg : : : Removed processors : ------------------- : : * src/cpu/amd/agesa/family14 : * src/cpu/amd/agesa/family15tn : * src/cpu/amd/agesa/family16kb > nit: drop the `src/` prefix? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/71590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3edbf3ebc74ebae5896196b43dd5be014f27a0ec Gerrit-Change-Number: 71590 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 09 Jan 2023 04:00:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Documentation/releases: Start getting ready for the 4.19 release
by Felix Singer (Code Review) 09 Jan '23

09 Jan '23

Attention is currently required from: Felix Singer, Jason Glenesk. Felix Singer has uploaded a new patch set (#3) to the change originally created by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/71590 ) Change subject: Documentation/releases: Start getting ready for the 4.19 release ...................................................................... Documentation/releases: Start getting ready for the 4.19 release Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I3edbf3ebc74ebae5896196b43dd5be014f27a0ec --- M Documentation/releases/coreboot-4.19-relnotes.md 1 file changed, 136 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/71590/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/71590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3edbf3ebc74ebae5896196b43dd5be014f27a0ec Gerrit-Change-Number: 71590 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/brya/var/marasov: Remove wlan RTD3 driver for meet design c...
by Frank Chu (Code Review) 09 Jan '23

09 Jan '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Eric Lai. Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71693 ) Change subject: mb/google/brya/var/marasov: Remove wlan RTD3 driver for meet design change ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/brya/variants/marasov/overridetree.cb: https://review.coreboot.org/c/coreboot/+/71693/comment/15afdacc_30f30179 PS4, Line 187: register "wake" = "GPE0_DW1_03" > oh, okay. I can't access your issue. Then you should keep entry for wifi sar table. […] John Lin <john_lin(a)pegatron.corp-partner.google.com> #4Dec 21, 2022 01:37PM Reassigned to mavis1_yang(a)asus.corp-partner.google.com. 01:36PM Assignee:marasov-odm-external@google.com mavis1_yang(a)asus.corp-partner.google.com Hi Mavis, please check if marasov should no need wakeup by WLAN, 01:37PM mavis1_yang(a)asus.corp-partner.google.com <mavis1_yang(a)asus.corp-partner.google.com> #5Jan 5, 2023 03:29PM Marasov no needs this feature. Thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/71693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22448a8cb28ddadb93b114c096e364980feab6fd Gerrit-Change-Number: 71693 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 09 Jan 2023 03:53:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: docs/releases/4.19: Add toolchain updates
by Felix Singer (Code Review) 09 Jan '23

09 Jan '23

Attention is currently required from: Felix Singer, Jason Glenesk, Martin L Roth, Elyes Haouas. Felix Singer has uploaded a new patch set (#3) to the change originally created by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/71178 ) Change subject: docs/releases/4.19: Add toolchain updates ...................................................................... docs/releases/4.19: Add toolchain updates Change-Id: If8c3f8e18ccbec8770917cc97aa562eac7417aaf Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M Documentation/releases/coreboot-4.19-relnotes.md 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/71178/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/71178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8c3f8e18ccbec8770917cc97aa562eac7417aaf Gerrit-Change-Number: 71178 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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