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Change subject: utils/inteltool: Add support to print Key Locker status
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Patch Set 5: Code-Review+2
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Change subject: util/kconfig: Fix patch to be compatible with quilt
......................................................................
Patch Set 1:
(1 comment)
File util/kconfig/patches/0014-util-kconfig-Move-Kconfig-deps-back-into-build-confi.patch:
https://review.coreboot.org/c/coreboot/+/69863/comment/d499c40a_1271e044
PS1, Line 38: char *autoconf_name
> Not intentionally by any manual intervention by me; this file was just what quilt output when I got […]
Okay, thanks for the explanation. I'm not familiar with quilt. How did you reformat the patch so that it's compliant with quilt?
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Change subject: util/kconfig: Fix patch to be compatible with quilt
......................................................................
Patch Set 1:
(1 comment)
File util/kconfig/patches/0014-util-kconfig-Move-Kconfig-deps-back-into-build-confi.patch:
https://review.coreboot.org/c/coreboot/+/69863/comment/ab0d2bbb_5da3cbeb
PS1, Line 38: char *autoconf_name
> Is this intended?
Not intentionally by any manual intervention by me; this file was just what quilt output when I got it to reformat the original patch. Based on this line as well as line 24, it seems like quilt only outputs the first 40 characters for the section heading in the range information line. It doesn't seem to affect quilt's functionality if I add the removed parts back in though. It also seems like `diff --unified --show-c-function` has that behavior as well, and I think that's what quilt uses to format it's diffs.
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Change subject: mb/google/dedede: Use runtime detection for touchscreens
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Change subject: mb/google/dedede: Set touchscreen IRQs to LEVEL vs EDGE
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Sridhar Siricilla has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70751 )
(
8 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: soc/intel/common: Fix cpu index calculation
......................................................................
soc/intel/common: Fix cpu index calculation
get_cpu_index() helper function returns cpu's index based on it's APIC
id position from the ascending order list of cpus' APIC IDs.
In order to calculate the cpu's index, the helper function needs to
traverse through each cpu node to find their APIC IDs. So, the function
traverse the CPU node list from the cpu whose APIC ID is 0 assuming it
is the first cpu node in the list. This logic works fine where BSP's
APIC ID is 0. But, starting from MTL, APIC ID for BSP need not be 0 as
APIC ID numbering first get assigned for CPU Die Efficient cores, then
Performance cores.
Please refer section# 6.1 of doc#643504 for more details on APIC IDs.
Considering the APIC Id allotment for MTL cores, as existing code
traversing begins from the cpu that has APIC Id#0 which may not be the
first cpu node in the list so index calculation results in wrong value.
The patch addresses above described issue by traversing all the CPU
nodes to calculate the cpu index. Also, prevents inconsistent report
of /sys/devices/system/cpu/cpu*/cpufreq/* and
/sys/devices/system/cpu/cpuXX/acpi_cppc on each reboot.
TEST=Verified that the get_cpu_index helper function returns the correct
index id for a CPU on Rex.
The coreboot log with code instrumentation, before this patch:
[DEBUG] my_apic_id:0x10 cpu_index: 0x6
[DEBUG] my_apic_id:0x11 cpu_index: 0x6
[DEBUG] my_apic_id:0x42 cpu_index: 0x6
[DEBUG] my_apic_id:0x21 cpu_index: 0x6
[DEBUG] my_apic_id:0x40 cpu_index: 0x6
[DEBUG] my_apic_id:0x31 cpu_index: 0x6
[DEBUG] my_apic_id:0x39 cpu_index: 0x6
[DEBUG] my_apic_id:0xa cpu_index: 0x3
[DEBUG] my_apic_id:0x0 cpu_index: 0x0
[DEBUG] my_apic_id:0x8 cpu_index: 0x2
[DEBUG] my_apic_id:0x4 cpu_index: 0x2
[DEBUG] my_apic_id:0x28 cpu_index: 0x6
[DEBUG] my_apic_id:0x2 cpu_index: 0x1
[DEBUG] my_apic_id:0x38 cpu_index: 0x6
[DEBUG] my_apic_id:0x29 cpu_index: 0x6
[DEBUG] my_apic_id:0xe cpu_index: 0x5
[DEBUG] my_apic_id:0x6 cpu_index: 0x2
[DEBUG] my_apic_id:0x20 cpu_index: 0x6
[DEBUG] my_apic_id:0x30 cpu_index: 0x6
[DEBUG] my_apic_id:0x19 cpu_index: 0x6
[DEBUG] my_apic_id:0xc cpu_index: 0x4
[DEBUG] my_apic_id:0x18 cpu_index: 0x6
We can see same cpu_index for multiple cores before fix.
After this patch..
[DEBUG] my_apic_id:0x10 cpu_index: 0x8
[DEBUG] my_apic_id:019 cpu_index: 0xb
[DEBUG] my_apic_id:0x11 cpu_index: 0x9
[DEBUG] my_apic_id:0x18 cpu_index: 0xa
[DEBUG] my_apic_id:0x40 cpu_index: 0x14
[DEBUG] my_apic_id:0x30 cpu_index: 0x10
[DEBUG] my_apic_id:0x42 cpu_index: 0x15
[DEBUG] my_apic_id:0xc cpu_index: 0x6
[DEBUG] my_apic_id:0x2 cpu_index: 0x1
[DEBUG] my_apic_id:0x29 cpu_index: 0xf
[DEBUG] my_apic_id:0xe cpu_index: 0x7
[DEBUG] my_apic_id:0x20 cpu_index: 0xc
[DEBUG] my_apic_id:0x0 cpu_index: 0x0
[DEBUG] my_apic_id:0x31 cpu_index: 0x11
[DEBUG] my_apic_id:0x28 cpu_index: 0xe
[DEBUG] my_apic_id:0x21 cpu_index: 0xd
[DEBUG] my_apic_id:0xa cpu_index: 0x5
[DEBUG] my_apic_id:0x38 cpu_index: 0x12
[DEBUG] my_apic_id:0x8 cpu_index: 0x4
[DEBUG] my_apic_id:0x4 cpu_index: 0x2
[DEBUG] my_apic_id:0x39 cpu_index: 0x13
Change-Id: I69e5e6231dd18b43d439340aaed50eb9edeca3b7
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70751
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-by: Kapil Porwal <kapilporwal(a)google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/intel/common/block/acpi/cpu_hybrid.c
1 file changed, 96 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Arthur Heymans: Looks good to me, approved
Sukumar Ghorai: Looks good to me, but someone else must approve
Kapil Porwal: Looks good to me, approved
diff --git a/src/soc/intel/common/block/acpi/cpu_hybrid.c b/src/soc/intel/common/block/acpi/cpu_hybrid.c
index e5ccf46..8f0da02 100644
--- a/src/soc/intel/common/block/acpi/cpu_hybrid.c
+++ b/src/soc/intel/common/block/acpi/cpu_hybrid.c
@@ -24,16 +24,22 @@
return get_soc_cpu_type() == CPUID_CORE_TYPE_INTEL_CORE;
}
+static struct device *get_cpu_bus_first_child(void)
+{
+ struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER);
+ assert(dev != NULL);
+ return (dev->link_list)->children;
+}
+
static u32 get_cpu_index(void)
{
u32 cpu_index = 0;
struct device *dev;
u32 my_apic_id = lapicid();
- for (dev = dev_find_lapic(0); dev; dev = dev->next) {
+ for (dev = get_cpu_bus_first_child(); dev; dev = dev->sibling)
if (my_apic_id > dev->path.apic.apic_id)
cpu_index++;
- }
return cpu_index;
}
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Change subject: mb/google/dedede: Add method to set GPIOs in romstage
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Patch Set 1: Code-Review+2
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Change subject: mb/google/dedede: Implement touchscreen power sequencing
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/71187/comment/71f171ba_6d3dcf08
PS2, Line 14: and
Exceeding 72 chars limit
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Change subject: util/kconfig: Fix patch to be compatible with quilt
......................................................................
Patch Set 1:
(1 comment)
File util/kconfig/patches/0014-util-kconfig-Move-Kconfig-deps-back-into-build-confi.patch:
https://review.coreboot.org/c/coreboot/+/69863/comment/520e1778_17c5432a
PS1, Line 38: char *autoconf_name
Is this intended?
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Change subject: docs/releases/4.19: Add note about ASL 2.0 conversion
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Set Ready For Review
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