coreboot-gerrit August 2022

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Change in coreboot[master]: [WIP] Documentation/basics: Add Super I/O section
by Christoph Pomaska (Code Review) 07 Aug '23

07 Aug '23

Christoph Pomaska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35912 ) Change subject: [WIP] Documentation/basics: Add Super I/O section ...................................................................... [WIP] Documentation/basics: Add Super I/O section This file contains and is supposed to contain basic information about what a Super I/O is and what it does. Change-Id: If288dcd79c4622a712868229b18f8b38e71d4af9 Signed-off-by: Christoph Pomaska <c.pomaska(a)hosting.de> --- A Documentation/basics/superio.md 1 file changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/35912/1 diff --git a/Documentation/basics/superio.md b/Documentation/basics/superio.md new file mode 100644 index 0000000..5f17a4c --- /dev/null +++ b/Documentation/basics/superio.md @@ -0,0 +1,29 @@ +# What is super I/O? + +Super I/O chips are a component that exist in PCs since the 1980s +and are usually connected via ISA/LPC. They are specific to x86 based platforms. + +Super I/O components have a wide range of tasks, from which the most widely known are: +- serial (e.g. RS232) +- PS/2 +- parallel (IEEE 1284) +- floppy-disk-controller +- PECI (Platform Enviroment Controller Interface) + +They can also act as an EC (Embedded Controller) managing things like: +- fancontrol +- battery charge controlling (on laptops) +- LED control + +BMC (Board Management Controller) and manage IPMI (Intelligent Platform Management Interface). +Very most x86 mainboards have at least one Super I/O chip. + +In case of the Supermicro [X10SLM+-F](https://www.supermicro.com/en/products/motherboard/x10slm+-f) there is a Nuvoton NCT6776 and an Aspeed AST2400 used. +The Nuvoton chip manages serial, PS/2 and hardware monitoring while the Aspeed chip manages the BMC functionality. +As another example does the Supermicro X11SSH-TF board solely use the same Aspeed chip as BMC, but also for serial. + + +## Super I/O and coreboot +The registers that need to be configured to make a Super I/O work are mostly vendor-specific, but sometimes also chip-specific. +coreboot ships a tool called [superiotool](../util.md) that reads out the most commonly used registers to determine which chip could be used on the board. +Conveniently it also prints out the registers and their contents in case a superio is detected. -- To view, visit https://review.coreboot.org/c/coreboot/+/35912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If288dcd79c4622a712868229b18f8b38e71d4af9 Gerrit-Change-Number: 35912 Gerrit-PatchSet: 1 Gerrit-Owner: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: soc/intel/baytrail: Use common sb code for SPI lockdown configuration
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36009 ) Change subject: soc/intel/baytrail: Use common sb code for SPI lockdown configuration ...................................................................... soc/intel/baytrail: Use common sb code for SPI lockdown configuration This removes the weakly linked function to configure the SPI lockdown. Change-Id: I10c00f6c8a0928210faa7c91a32a745d282088e9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/rambi/w25q64.c M src/soc/intel/baytrail/include/soc/spi.h M src/soc/intel/baytrail/southcluster.c 3 files changed, 16 insertions(+), 61 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/36009/1 diff --git a/src/mainboard/google/rambi/w25q64.c b/src/mainboard/google/rambi/w25q64.c index a9ed8ac..114c8c7 100644 --- a/src/mainboard/google/rambi/w25q64.c +++ b/src/mainboard/google/rambi/w25q64.c @@ -17,52 +17,16 @@ #include <soc/spi.h> /* - * SPI lockdown configuration W25Q64FW. + * SPI VSCC configuration W25Q64FW. */ -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ - -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ - -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ - -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ - -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ - -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ - -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ - -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ -#define SPI_OPTYPE_7 0x02 /* Read, address required */ - -#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) #define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) -static const struct spi_config spi_config = { - .preop = SPI_OPPREFIX, - .optype = SPI_OPTYPE, - .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, +static const struct vscc_config spi_config = { .lvscc = SPI_VSCC, .uvscc = SPI_VSCC, }; -int mainboard_get_spi_config(struct spi_config *cfg) +int mainboard_get_spi_vscc_config(struct vscc_config *cfg) { memcpy(cfg, &spi_config, sizeof(*cfg)); diff --git a/src/soc/intel/baytrail/include/soc/spi.h b/src/soc/intel/baytrail/include/soc/spi.h index 063dd7f..61e430b 100644 --- a/src/soc/intel/baytrail/include/soc/spi.h +++ b/src/soc/intel/baytrail/include/soc/spi.h @@ -54,17 +54,14 @@ # define BCR_WPD (0x1 << 0) /* - * SPI lockdown configuration. + * SPI VSCC configuration. */ -struct spi_config { - uint16_t preop; - uint16_t optype; - uint32_t opmenu[2]; - uint32_t lvscc; - uint32_t uvscc; -}; + struct vscc_config { + uint32_t lvscc; + uint32_t uvscc; + }; /* Return 0 on success < 0 on failure. */ -int mainboard_get_spi_config(struct spi_config *cfg); +int mainboard_get_spi_vscc_config(struct vscc_config *cfg); #endif /* _BAYTRAIL_SPI_H_ */ diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 139d2be..f5bbda6 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -42,6 +42,7 @@ #include <soc/spi.h> #include "chip.h" #include <arch/acpigen.h> +#include <southbridge/intel/common/spi.h> static inline void add_mmio_resource(struct device *dev, int i, unsigned long addr, @@ -540,11 +541,6 @@ .device = LPC_DEVID, }; -int __weak mainboard_get_spi_config(struct spi_config *cfg) -{ - return -1; -} - static void finalize_chipset(void *unused) { u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); @@ -552,7 +548,7 @@ u32 *gen_pmcon2 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2); u32 *etr = (u32 *)(PMC_BASE_ADDRESS + ETR); u8 *spi = (u8 *)SPI_BASE_ADDRESS; - struct spi_config cfg; + struct vscc_config cfg; /* Set the lock enable on the BIOS control register. */ write32(bcr, read32(bcr) | BCR_LE); @@ -566,14 +562,12 @@ /* Set the CF9 lock. */ write32(etr, read32(etr) | CF9LOCK); - if (mainboard_get_spi_config(&cfg) < 0) { - printk(BIOS_DEBUG, "No SPI lockdown configuration.\n"); + spi_finalize_ops(); + write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN); + + if (mainboard_get_spi_vscc_config(&cfg) < 0) { + printk(BIOS_DEBUG, "No SPI VSCC configuration.\n"); } else { - write16(spi + PREOP, cfg.preop); - write16(spi + OPTYPE, cfg.optype); - write32(spi + OPMENU0, cfg.opmenu[0]); - write32(spi + OPMENU1, cfg.opmenu[1]); - write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN); write32(spi + UVSCC, cfg.uvscc); write32(spi + LVSCC, cfg.lvscc | VCL); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10c00f6c8a0928210faa7c91a32a745d282088e9 Gerrit-Change-Number: 36009 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: add Gigabyte P34G v2
by Daniel Maslowski (Code Review) 07 Aug '23

07 Aug '23

Daniel Maslowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36010 ) Change subject: Documentation: add Gigabyte P34G v2 ...................................................................... Documentation: add Gigabyte P34G v2 Change-Id: Ie8025f7bf4e7b40810c97a0b5fa80fd7c41e97eb Signed-off-by: Daniel Maslowski <info(a)orangecms.org> --- A Documentation/mainboard/gigabyte/p34g-v2.md A Documentation/mainboard/gigabyte/p34g-v2_tpm_socket_spi_chip.jpg M Documentation/mainboard/index.md 3 files changed, 89 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/36010/1 diff --git a/Documentation/mainboard/gigabyte/p34g-v2.md b/Documentation/mainboard/gigabyte/p34g-v2.md new file mode 100644 index 0000000..4dfcf79 --- /dev/null +++ b/Documentation/mainboard/gigabyte/p34g-v2.md @@ -0,0 +1,88 @@ +# Gigabyte P34G v2 + +This page describes how to run coreboot on the [Gigabyte P34G v2 gaming +laptop](https://www.gigabyte.com/Laptop/P34G-v2). + +Original board name: GA-R3456R + +Rebrands: +- Schenker XMG C404 + +## Technology + +```eval_rst ++------------------+----------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/haswell/index` | ++------------------+----------------------------------------------+ +| Southbridge | Lynx Point | ++------------------+----------------------------------------------+ +| CPU | i7-4710HQ | ++------------------+----------------------------------------------+ +| EC / SuperIO | ITE IT8587E | ++------------------+----------------------------------------------+ +| Coprocessor | Intel ME, `me_cleaner` untested | ++------------------+----------------------------------------------+ +| TPM | None, but socket exists (see photo below) | ++------------------+----------------------------------------------+ +``` + +## Required proprietary blobs + +```eval_rst +Please see :doc:`../../northbridge/intel/haswell/mrc.bin`. +``` + +## Flash chip + +![SPI chip and TPM location](p34g-v2_tpm_socket_spi_chip.jpg) + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | No | ++---------------------+------------+ +| Model | MX25L6406E | ++---------------------+------------+ +| Size | 8 MiB | ++---------------------+------------+ +| In circuit flashing | Yes | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Write protection | No | ++---------------------+------------+ +| Internal flashing | Untested | ++---------------------+------------+ +``` + +## Flash layout + +```txt +00000000:00000fff fd +00400000:007fffff bios +00001000:003fffff me +``` + +## EC firmware + +There is an additional 128KiB EC firmware blob within the BIOS region at +`0x700000`. The EC has its own internal EPROM though, for which Gigabyte offers +updates in a bundle with the UEFI firmware updates based on AMI Aptio. The EC +firmware can be updated via AFU. An unmodified EC firmware version F005 seems +to work fine with coreboot even without the extra 128KiB part. It could be +extracted from a firmware update through `dd` etc and reinserted though. Other +version have not been tested. + +## Known issues + +- EC / ACPI + * no suspend on LID close + * eject, sleep, backlight up/down, external screen buttons do not work + * Bluetooth LED shows inverted state, does not turn on on first press + * battery state can not be queried +- CPU overheats on high load leading to force poweroff + +```eval_rst +Please also see :doc:`../../northbridge/intel/haswell/known-issues`. +``` diff --git a/Documentation/mainboard/gigabyte/p34g-v2_tpm_socket_spi_chip.jpg b/Documentation/mainboard/gigabyte/p34g-v2_tpm_socket_spi_chip.jpg new file mode 100644 index 0000000..9835a8a --- /dev/null +++ b/Documentation/mainboard/gigabyte/p34g-v2_tpm_socket_spi_chip.jpg Binary files differ diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 83189757..f0f8f8e 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -40,6 +40,7 @@ ## Gigabyte - [GA-H61M-S2PV](gigabyte/ga-h61m-s2pv.md) +- [P34G v2](gigabyte/p34g-v2.md) ## Google -- To view, visit https://review.coreboot.org/c/coreboot/+/36010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8025f7bf4e7b40810c97a0b5fa80fd7c41e97eb Gerrit-Change-Number: 36010 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: inteltool: gemini lake gpio support + UHD 605 graphics detection
by Name of user not set (Code Review) 07 Aug '23

07 Aug '23

coreboot(a)s.paape.io has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36033 ) Change subject: inteltool: gemini lake gpio support + UHD 605 graphics detection ...................................................................... inteltool: gemini lake gpio support + UHD 605 graphics detection Signed-off-by: lead4good <coreboot(a)s.paape.io> Change-Id: If8b04e58359bb8ff17318f86b6d9a57def94a401 --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c 5 files changed, 317 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/36033/1 diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index efeab56..da4eadd 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1035,6 +1035,7 @@ case PCI_DEVICE_ID_INTEL_QM170: case PCI_DEVICE_ID_INTEL_HM170: case PCI_DEVICE_ID_INTEL_CM236: + case PCI_DEVICE_ID_INTEL_GLK: case PCI_DEVICE_ID_INTEL_APL_LPC: case PCI_DEVICE_ID_INTEL_DNV_LPC: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 321cf97..cc1d99e 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -45,6 +45,310 @@ * (if it's the first column, GPIO is the default, no matter the name) */ +static const char *const glk_group_northwest_names[] = { + "GPIO_0", "JTAG_TCK", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_1", "JTAG_TRST_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_2", "JTAG_TMS", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_3", "JTAG_TDI", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_4", "JTAG_TDO", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_5", "JTAGX", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_6", "JTAG_PREQ_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_7", "JTAG_PRDY_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_8", "n/a", "n/a", "CNV_DEBUG_09", "CNV_DEBUG_00", "n/a", "n/a", + "GPIO_9", "n/a", "n/a", "CNV_DEBUG_10", "CNV_DEBUG_01", "n/a", "n/a", + "GPIO_10", "n/a", "n/a", "CNV_DEBUG_11", "CNV_DEBUG_02", "n/a", "n/a", + "GPIO_11", "n/a", "n/a", "CNV_DEBUG_12", "CNV_DEBUG_03", "n/a", "n/a", + "GPIO_12", "n/a", "n/a", "CNV_DEBUG_13", "CNV_DEBUG_04", "n/a", "n/a", + "GPIO_13", "n/a", "n/a", "CNV_DEBUG_14", "CNV_DEBUG_05", "n/a", "n/a", + "GPIO_14", "n/a", "n/a", "CNV_DEBUG_15", "CNV_DEBUG_06", "n/a", "n/a", + "GPIO_15", "n/a", "n/a", "CNV_DEBUG_16", "CNV_DEBUG_07", "n/a", "n/a", + "GPIO_16", "n/a", "n/a", "CNV_DEBUG_17", "CNV_DEBUG_08", "n/a", "n/a", + "GPIO_17", "n/a", "CNV_MFUART0_RXD", "CNV_DEBUG_00", "n/a", "n/a", "n/a", + "GPIO_18", "n/a", "CNV_MFUART0_TXD", "CNV_DEBUG_01", "n/a", "n/a", "n/a", + "GPIO_19", "n/a", "CNV_MFUART0_RTS_N", "CNV_DEBUG_02", "n/a", "n/a", "n/a", + "GPIO_20", "n/a", "CNV_MFUART0_CTS_N", "CNV_DEBUG_03", "n/a", "n/a", "n/a", + "GPIO_21", "n/a", "CNV_MFUART2_RXD", "CNV_DEBUG_04", "n/a", "n/a", "n/a", + "GPIO_22", "n/a", "CNV_MFUART2_TXD", "CNV_DEBUG_05", "n/a", "n/a", "n/a", + "GPIO_23", "n/a", "CNV_GNSS_PA_BLANKING", "CNV_DEBUG_06", "PMIC_STDBY", "n/a", "n/a", + "GPIO_24", "n/a", "CNV_GNSS_FTA", "CNV_DEBUG_07", "PMIC_PWRGOOD", "n/a", "n/a", + "GPIO_25", "n/a", "CNV_GNSS_SYSCK", "CNV_DEBUG_08", "PMIC_RESET_N", "n/a", "n/a", + "GPIO_26", "n/a", "SIO_UART1_RXD", "ISH_UART1_RXD", "CNV_BT_UART_RXD", "n/a", "n/a", + "GPIO_27", "n/a", "SIO_UART1_TXD", "ISH_UART1_TXD", "CNV_BT_UART_TXD", "n/a", "n/a", + "GPIO_28", "n/a", "SIO_UART1_RTS_N", "ISH_UART1_RTS_N", "CNV_BT_UART_RTS_N", "n/a", "n/a", + "GPIO_29", "n/a", "SIO_UART1_CTS_N", "ISH_UART1_CTS_N", "CNV_BT_UART_CTS_N", "n/a", "n/a", + "GPIO_30", "n/a", "SATA_GP0", "n/a", "n/a", "n/a", "n/a", + "GPIO_31", "n/a", "SATA_GP1", "n/a", "n/a", "n/a", "n/a", + "GPIO_32", "n/a", "SATA_DE_VSLP0", "n/a", "n/a", "n/a", "n/a", + "GPIO_33", "n/a", "SATA_DE_VSLP1", "SUSCLK1", "n/a", "n/a", "n/a", + "GPIO_34", "n/a", "SATA_LEDN", "SUSCLK2", "n/a", "n/a", "n/a", + "GPIO_35", "n/a", "n/a", "n/a", "SPKR", "n/a", "BSSB_CLK", + "GPIO_36", "n/a", "n/a", "CNV_BTEN", "n/a", "n/a", "BSSB_DI", + "GPIO_37", "n/a", "n/a", "CNV_GNEN", "n/a", "n/a", "n/a", + "GPIO_38", "n/a", "n/a", "CNV_WFEN", "n/a", "n/a", "n/a", + "GPIO_39", "n/a", "n/a", "CNV_WCEN", "n/a", "n/a", "n/a", + "GPIO_40", "n/a", "n/a", "CNVBT_HOST_WAKE_N", "n/a", "n/a", "n/a", + "GPIO_41", "n/a", "n/a", "CNV_GNSS_HOST_WAKE_N", "n/a", "n/a", "n/a", + "GPIO_42", "MDSI_A_TE", "PWM0", "n/a", "n/a", "n/a", "n/a", + "GPIO_43", "MDSI_C_TE", "PWM1", "n/a", "n/a", "n/a", "n/a", + "GPIO_44", "USB2_OC0_N", "PWM2", "n/a", "n/a", "n/a", "n/a", + "GPIO_45", "USB2_OC1_N", "PWM3", "n/a", "n/a", "n/a", "n/a", + "GPIO_46", "MIPI_I2C_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_47", "MIPI_I2C_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_48", "PMC_I2C_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_49", "PMC_I2C_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_50", "SIO_I2C0_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_51", "SIO_I2C0_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_52", "SIO_I2C1_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_53", "SIO_I2C1_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_54", "SIO_I2C2_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_55", "SIO_I2C2_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_56", "SIO_I2C3_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_57", "SIO_I2C3_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_58", "SIO_I2C4_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_59", "SIO_I2C4_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_60", "SIO_UART0_RXD", "ISH_UART0_RXD", "CNV_GNSS_UART_RXD", "n/a", "n/a", "n/a", + "GPIO_61", "SIO_UART0_TXD", "ISH_UART0_TXD", "CNV_GNSS_UART_TXD", "n/a", "n/a", "n/a", + "GPIO_62", "SIO_UART0_RTS_N", "ISH_UART0_RTS_N", "CNV_GNSS_UART_RTS_N", "n/a", "n/a", "n/a", + "GPIO_63", "SIO_UART0_CTS_N", "ISH_UART0_CTS_N", "CNV_GNSS_UART_CTS_N", "n/a", "n/a", "n/a", + "GPIO_64", "SIO_UART2_RXD", "ISH_UART2_RXD", "CNV_MFUART1_RXD", "n/a", "n/a", "n/a", + "GPIO_65", "SIO_UART2_TXD", "ISH_UART2_TXD", "CNV_MFUART1_TXD", "n/a", "n/a", "n/a", + "GPIO_66", "SIO_UART2_RTS_N", "ISH_UART2_RTS_N", "CNV_MFUART1_RTS_N", "n/a", "n/a", "n/a", + "GPIO_67", "SIO_UART2_CTS_N", "ISH_UART2_CTS_N", "CNV_MFUART1_CTS_N", "n/a", "n/a", "n/a", + "GPIO_68", "PMC_SPI_FS0", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_69", "PMC_SPI_FS1", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_70", "PMC_SPI_FS2", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_71", "PMC_SPI_RXD", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_72", "PMC_SPI_TXD", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_73", "PMC_SPI_CLK", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_74", "THERMTRIP_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_75", "PROCHOT_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_211","EMMC_RST_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_212", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_213", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_214", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group glk_group_northwest = { + .display = "------- GPIO Group NorthWest -------", + .pad_count = ARRAY_SIZE(glk_group_northwest_names) / 7, + .func_count = 7, + .pad_names = glk_group_northwest_names, +}; + +static const struct gpio_group *const glk_community_northwest_groups[] = { + &glk_group_northwest, +}; + +static const struct gpio_community glk_community_northwest = { + .name = "----- GPIO Community NorthWest -----", + .pcr_port_id = 0xc4, + .group_count = ARRAY_SIZE(glk_community_northwest_groups), + .groups = glk_community_northwest_groups, +}; + +static const char *const glk_group_north_names[] = { + "GPIO_76", "SVID0_ALERT_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_77", "SVID0_DATA", "n/a", "n/a", "n/a", "n/a", + "GPIO_78", "SVID0_CLK", "n/a", "n/a", "n/a", "n/a", + "GPIO_79", "SIO_SPI_0_CLK", "ISH_SPI_0_CLK", "n/a", "n/a", "n/a", + "GPIO_80", "SIO_SPI_0_FS0", "ISH_SPI_0_FS0", "n/a", "n/a", "n/a", + "GPIO_81", "SIO_SPI_0_FS1", "ISH_SPI_0_FS1", "FST_SPI_CS2_N", "n/a", "n/a", + "GPIO_82", "SIO_SPI_0_RXD", "ISH_SPI_0_RXD", "n/a", "n/a", "n/a", + "GPIO_83", "SIO_SPI_0_TXD", "ISH_SPI_0_TXD", "n/a", "n/a", "n/a", + "GPIO_84", "SIO_SPI_2_CLK", "ISH_SPI_1_CLK", "TOUCH_SPI_CLK", "n/a", "n/a", + "GPIO_85", "SIO_SPI_2_FS0", "ISH_SPI_1_FS0", "TOUCH_SPI_FS0", "n/a", "n/a", + "GPIO_86", "SIO_SPI_2_FS1", "ISH_SPI_1_FS1", "TOUCH_SPI_D0", "n/a", "n/a", + "GPIO_87", "SIO_SPI_2_FS2", "n/a", "TOUCH_SPI_D1", "n/a", "n/a", + "GPIO_88", "SIO_SPI_2_RXD", "ISH_SPI_1_RXD", "TOUCH_SPI_D2", "n/a", "n/a", + "GPIO_89", "SIO_SPI_2_TXD", "ISH_SPI_0_TXD", "TOUCH_SPI_D3", "n/a", "n/a", + "GPIO_90", "FST_SPI_CS0_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_91", "FST_SPI_CS1_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_92", "FST_SPI_MOSI_IO0", "n/a", "n/a", "n/a", "n/a", + "GPIO_93", "FST_SPI_MISO_IO1", "n/a", "n/a", "n/a", "n/a", + "GPIO_94", "FST_SPI_IO2", "n/a", "n/a", "n/a", "n/a", + "GPIO_95", "FST_SPI_IO3", "n/a", "n/a", "n/a", "n/a", + "GPIO_96", "FST_SPI_CLK", "n/a", "n/a", "n/a", "n/a", + "GPIO_97", "FST_SPI_CLK_FB", "n/a", "n/a", "n/a", "n/a", + "GPIO_98", "PMU_PLTRST_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_99", "PMU_PWRBTN_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_100", "PMU_SLP_S0_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_101", "PMU_SLP_S3_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_102", "PMU_SLP_S4_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_103", "SUSPWRDNACK", "n/a", "n/a", "n/a", "n/a", + "GPIO_104", "EMMC_PWR_EN_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_105", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_106", "PMU_BATLOW_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_107", "PMU_RSTBTN_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_108", "PMU_SUSCLK", "n/a", "n/a", "n/a", "n/a", + "GPIO_109", "SUS_STAT_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_110", "SIO_I2C5_SDA", "ISH_I2C0_SDA", "n/a", "n/a", "n/a", + "GPIO_111", "SIO_I2C5_SCL", "ISH_I2C0_SCL", "n/a", "n/a", "n/a", + "GPIO_112", "SIO_I2C6_SDA", "ISH_I2C1_SDA", "n/a", "n/a", "n/a", + "GPIO_113", "SIO_I2C6_SCL", "ISH_I2C1_ScL", "n/a", "n/a", "n/a", + "GPIO_114", "SIO_I2C7_SDA", "ISH_I2C2_SDA", "SUSCLK1", "n/a", "n/a", + "GPIO_115", "SIO_I2C7_SCL", "ISH_I2C2_SCL", "SUSCLK2", "n/a", "n/a", + "GPIO_116", "PCIE_WAKE0_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_117", "PCIE_WAKE1_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_118", "PCIE_WAKE2_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_119", "PCIE_WAKE3_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_120", "PCIE_CLKREQ0_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_121", "PCIE_CLKREQ1_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_122", "PCIE_CLKREQ2_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_123", "PCIE_CLKREQ3_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_124", "DDI0_DDC_SDA", "n/a", "n/a", "n/a", "n/a", + "GPIO_125", "DDI0_DDC_SCL", "n/a", "n/a", "n/a", "n/a", + "GPIO_126", "DDI1_DDC_SDA", "SIO_I2C5_SDA", "n/a", "n/a", "n/a", + "GPIO_127", "DDI1_DDC_SCL", "SIO_I2C5_SCL", "n/a", "n/a", "n/a", + "GPIO_128", "PNL0_VDDEN", "n/a", "n/a", "n/a", "n/a", + "GPIO_129", "PNL0_BKLTEN", "n/a", "n/a", "n/a", "n/a", + "GPIO_130", "PNL0_BKLCTL", "n/a", "n/a", "n/a", "n/a", + "GPIO_131", "DDI0_HPD", "n/a", "n/a", "n/a", "n/a", + "GPIO_132", "DDI1_HPD", "n/a", "n/a", "n/a", "n/a", + "GPIO_133", "DDI2_HPD", "n/a", "n/a", "n/a", "n/a", + "GPIO_134", "n/a", "n/a", "n/a", "ISH_GPIO_10", "n/a", + "GPIO_135", "n/a", "n/a", "n/a", "ISH_GPIO_11", "n/a", + "GPIO_136", "n/a", "n/a", "n/a", "ISH_GPIO_12", "n/a", + "GPIO_137", "n/a", "n/a", "n/a", "ISH_GPIO_13", "n/a", + "GPIO_138", "n/a", "SIO_UART3_RXD", "ISH_UART0_RXD", "ISH_GPIO_14", "SATA_GP0", + "GPIO_139", "n/a", "SIO_UART3_TXD", "ISH_UART0_TXD", "ISH_GPIO_15", "SATA_GP1", + "GPIO_140", "n/a", "SIO_UART3_RTS_N", "ISH_UART0_RTS_N", "n/a", "SATA_DEVSLP0", + "GPIO_141", "n/a", "SIO_UART3_CTS_N", "ISH_UART0_CTS_N", "n/a", "SATA_DEVSLP1", + "GPIO_142", "n/a", "SIO_SPI_1_CLK", "ISH_SPI_0_CLK", "n/a", "SATA_LEDN", + "GPIO_143", "n/a", "SIO_SPI_1_FS0", "ISH_SPI_0_FS0", "JTAG2_TCK", "n/a", + "GPIO_144", "n/a", "SIO_SPI_1_FS1", "ISH_SPI_0_FS1", "PNL1_VDDEN", "n/a", + "GPIO_145", "n/a", "SIO_SPI_1_RXD", "ISH_SPI_0_RXD", "PNL1_BKLTEN", "n/a", + "GPIO_146", "n/a", "SIO_SPI_1_TXD", "ISH_SPI_0_TXD", "PNL1_BKLTCTL", "n/a", + "GPIO_147", "LPC_SERIRQ", "ESPI_RESET_N", "n/a", "n/a", "n/a", + "GPIO_148", "LPC_CLKOUT0", "ESPI_CLK", "n/a", "n/a", "n/a", + "GPIO_149", "LPC_CLKOUT1", "n/a", "n/a", "n/a", "n/a", + "GPIO_150", "LPC_AD0", "ESPI_IO_0", "n/a", "n/a", "n/a", + "GPIO_151", "LPC_AD1", "ESPI_IO_1", "n/a", "n/a", "n/a", + "GPIO_152", "LPC_AD2", "ESPI_IO_2", "n/a", "n/a", "n/a", + "GPIO_153", "LPC_AD3", "ESPI_IO_3", "n/a", "n/a", "n/a", + "GPIO_154", "LPC_CLKRUN_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_155", "LPC_FRAME_N", "ESPI_CS_N", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group glk_group_north = { + .display = "----- GPIO Group North -----", + .pad_count = ARRAY_SIZE(glk_group_north_names) / 6, + .func_count = 6, + .pad_names = glk_group_north_names, +}; + +static const struct gpio_group *const glk_community_north_groups[] = { + &glk_group_north, +}; + +static const struct gpio_community glk_community_north = { + .name = "--- GPIO Community North ---", + .pcr_port_id = 0xc5, + .group_count = ARRAY_SIZE(glk_community_north_groups), + .groups = glk_community_north_groups, +}; + +static const char *const glk_group_audio_names[] = { + "GPIO_156", "AVS_I2S0_MCLK", "n/a", "n/a", + "GPIO_157", "AVS_I2S0_BCLK", "n/a", "n/a", + "GPIO_158", "AVS_I2S0_WS_SYNC", "n/a", "n/a", + "GPIO_159", "AVS_I2S0_SDI", "n/a", "n/a", + "GPIO_160", "AVS_I2S0_SDO", "n/a", "n/a", + "GPIO_161", "AVS_I2S1_MCLK", "n/a", "n/a", + "GPIO_162", "AVS_I2S1_BCLK", "n/a", "CNV_BT_I2S_BCLK", + "GPIO_163", "AVS_I2S1_WS_SYNC", "n/a", "CNV_BT_I2S_WS_SYNC", + "GPIO_164", "AVS_I2S1_SDI", "n/a", "CNV_BT_I2S_SDI", + "GPIO_165", "AVS_I2S1_SDO", "n/a", "CNV_BT_I2S_SDO", + "GPIO_166", "AVS_HDA_BCLK", "AVS_I2S2_BCLK", "n/a", + "GPIO_167", "AVS_HDA_WS_SYNC", "AVS_I2S2_WS_SYNC", "n/a", + "GPIO_168", "AVS_HDA_SDI", "AVS_I2S2_SDI", "n/a", + "GPIO_169", "AVS_HDA_SDO", "AVS_I2S2_SDO", "n/a", + "GPIO_170", "AVS_HDA_RST_N", "AVS_I2S1_MCLK", "n/a", + "GPIO_171", "AVS_DMIC_CLK_A1", "n/a", "n/a", + "GPIO_172", "AVS_DMIC_CLK_B1", "n/a", "n/a", + "GPIO_173", "AVS_DMIC_DATA_1", "n/a", "n/a", + "GPIO_174", "AVS_DMIC_CLK_AB2", "n/a", "n/a", + "GPIO_175", "AVS_DMIC_DATA_2", "n/a", "n/a", +}; + +static const struct gpio_group glk_group_audio = { + .display = "----- GPIO Group Audio -----", + .pad_count = ARRAY_SIZE(glk_group_audio_names) / 4, + .func_count = 4, + .pad_names = glk_group_audio_names, +}; + +static const struct gpio_group *const glk_community_audio_groups[] = { + &glk_group_audio, +}; + +static const struct gpio_community glk_community_audio = { + .name = "--- GPIO Community Audio ---", + .pcr_port_id = 0xc9, + .group_count = ARRAY_SIZE(glk_community_audio_groups), + .groups = glk_community_audio_groups, +}; + +static const char *const glk_group_scc_names[] = { + "GPIO_176", "SMB_ALERT_N", "n/a", "n/a", + "GPIO_177", "SMB_CLK", "SIO_I2C7_SCL", "n/a", + "GPIO_178", "SMB_DATA", "SIO_I2C7_SDA", "n/a", + "GPIO_187", "SDCARD_LVL_WP", "n/a", "n/a", + "GPIO_179", "SDCARD_CLK", "n/a", "n/a", + "GPIO_180", "SDCARD_CLK_FB", "n/a", "n/a", + "GPIO_181", "SDCARD_D0", "n/a", "n/a", + "GPIO_182", "SDCARD_D1", "n/a", "n/a", + "GPIO_183", "SDCARD_D2", "n/a", "n/a", + "GPIO_184", "SDCARD_D3", "n/a", "n/a", + "GPIO_185", "SDCARD_CMD", "n/a", "n/a", + "GPIO_186", "SDCARD_CD_N", "n/a", "n/a", + "GPIO_188", "SDCARD_PWR_DWN_N", "n/a", "n/a", + "GPIO_210", "n/a", "n/a", "n/a", + "GPIO_189", "OSC_CLK_OUT_0", "n/a", "n/a", + "GPIO_190", "OSC_CLK_OUT_1", "n/a", "n/a", + "GPIO_191", "CNV_BRI_DT", "n/a", "SIO_UART1_RTS_N", + "GPIO_192", "CNV_BRI_RST", "n/a", "SIO_UART1_RXD", + "GPIO_193", "CNV_RGI_DT", "n/a", "SIO_UART1_TXD", + "GPIO_194", "CNV_RGI_RST", "n/a", "SIO_UART1_CTS_N", + "GPIO_195", "CNV_RF_RESET_N", "n/a", "AVS_I2S1_WS_SYNC", + "GPIO_196", "XTAL_CLKREQ", "n/a", "AVS_I2S1_SDO", + "GPIO_197", "SDIO_CLK_FB", "n/a", "n/a", + "GPIO_198", "EMMC_CLK", "n/a", "n/a", + "GPIO_199", "EMMC_D0", "n/a", "n/a", + "GPIO_200", "EMMC_D1", "n/a", "n/a", + "GPIO_201", "EMMC_D2", "n/a", "n/a", + "GPIO_202", "EMMC_D3", "n/a", "n/a", + "GPIO_203", "EMMC_D4", "n/a", "n/a", + "GPIO_204", "EMMC_D5", "n/a", "n/a", + "GPIO_205", "EMMC_D6", "n/a", "n/a", + "GPIO_206", "EMMC_D7", "n/a", "n/a", + "GPIO_207", "EMMC_CMD", "n/a", "n/a", + "GPIO_208", "EMMC_RCLK", "n/a", "n/a", + "GPIO_209", "EMMC_RST_N", "n/a", "n/a", +}; + +static const struct gpio_group glk_group_scc = { + .display = "----- GPIO Group SCC -----", + .pad_count = ARRAY_SIZE(glk_group_scc_names) / 4, + .func_count = 4, + .pad_names = glk_group_scc_names, +}; + +static const struct gpio_group *const glk_community_scc_groups[] = { + &glk_group_scc, +}; + +static const struct gpio_community glk_community_scc = { + .name = "--- GPIO Community SCC ---", + .pcr_port_id = 0xc8, + .group_count = ARRAY_SIZE(glk_community_scc_groups), + .groups = glk_community_scc_groups, +}; + +static const struct gpio_community *const glk_communities[] = { + &glk_community_northwest, &glk_community_north, + &glk_community_audio, &glk_community_scc, +}; + static const char *const apl_group_north_names[] = { "*GPIO_0", "n/a", "n/a", "n/a", "n/a", "n/a", "*GPIO_1", "n/a", "n/a", "n/a", "n/a", "n/a", @@ -2284,6 +2588,12 @@ communities = apl_communities; pcr_init(sb); break; + case PCI_DEVICE_ID_INTEL_GLK: + community_count = ARRAY_SIZE(glk_communities); + communities = glk_communities; + pad_stepping = 16; + pcr_init(sb); + break; case PCI_DEVICE_ID_INTEL_H310: case PCI_DEVICE_ID_INTEL_H370: case PCI_DEVICE_ID_INTEL_Z390: diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index db80bd2..5aa4592 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -300,6 +300,7 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C224, "C224"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C226, "C226"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H81, "H81"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GLK, "Gemini Lake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_LPC, "Apollo Lake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_LPC, "Denverton" }, /* Intel GPUs */ @@ -395,6 +396,8 @@ "Intel(R) HD Graphics 530" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_530_2, "Intel(R) HD Graphics 530" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_605, + "Intel(R) UHD Graphics 605" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_615_1, "Intel(R) UHD Graphics 615" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_615_2, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index fc6dc4b..9ad1a5f 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -264,6 +264,7 @@ #define PCI_DEVICE_ID_INTEL_BAYTRAIL_GFX 0x0f31 #define CPUID_BAYTRAIL 0x30670 +#define PCI_DEVICE_ID_INTEL_GLK 0x31e8 #define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8 #define PCI_DEVICE_ID_INTEL_DNV_LPC 0x19dc @@ -340,6 +341,7 @@ #define PCI_DEVICE_ID_INTEL_HD_520 0x1916 #define PCI_DEVICE_ID_INTEL_HD_530_1 0x191B #define PCI_DEVICE_ID_INTEL_HD_530_2 0x1912 +#define PCI_DEVICE_ID_INTEL_UHD_605 0x3185 #define PCI_DEVICE_ID_INTEL_UHD_615_1 0x591C #define PCI_DEVICE_ID_INTEL_UHD_615_2 0x591E #define PCI_DEVICE_ID_INTEL_UHD_617 0x87C0 diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index ef6bb39..fec7457 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -120,6 +120,7 @@ p2sb = pci_get_dev(sb->access, 0, 0, 0x1f, 1); break; case PCI_DEVICE_ID_INTEL_APL_LPC: + case PCI_DEVICE_ID_INTEL_GLK: p2sb = pci_get_dev(sb->access, 0, 0, 0x0d, 0); break; case PCI_DEVICE_ID_INTEL_H310: -- To view, visit https://review.coreboot.org/c/coreboot/+/36033 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8b04e58359bb8ff17318f86b6d9a57def94a401 Gerrit-Change-Number: 36033 Gerrit-PatchSet: 1 Gerrit-Owner: coreboot(a)s.paape.io Gerrit-MessageType: newchange

6 11

Change in coreboot[master]: superio: IT8587E (WIP)
by Daniel Maslowski (Code Review) 07 Aug '23

07 Aug '23

Daniel Maslowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36071 ) Change subject: superio: IT8587E (WIP) ...................................................................... superio: IT8587E (WIP) Change-Id: I1e541daa2b3d48a4f5a0e7b7fa88a2c2f8a1b0c5 Signed-off-by: Daniel Maslowski <info(a)orangecms.org> --- A src/superio/ite/it8587e/Kconfig A src/superio/ite/it8587e/Makefile.inc A src/superio/ite/it8587e/it8587e.h A src/superio/ite/it8587e/superio.c 4 files changed, 137 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/36071/1 diff --git a/src/superio/ite/it8587e/Kconfig b/src/superio/ite/it8587e/Kconfig new file mode 100644 index 0000000..438bd3e --- /dev/null +++ b/src/superio/ite/it8587e/Kconfig @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_ITE_IT8587E + bool + select SUPERIO_ITE_COMMON_PRE_RAM diff --git a/src/superio/ite/it8587e/Makefile.inc b/src/superio/ite/it8587e/Makefile.inc new file mode 100644 index 0000000..dbde0b7 --- /dev/null +++ b/src/superio/ite/it8587e/Makefile.inc @@ -0,0 +1,15 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_ITE_IT8587E) += superio.c diff --git a/src/superio/ite/it8587e/it8587e.h b/src/superio/ite/it8587e/it8587e.h new file mode 100644 index 0000000..eab3527 --- /dev/null +++ b/src/superio/ite/it8587e/it8587e.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8587E_H +#define SUPERIO_ITE_IT8587E_H + +#define IT8528E_SP1 0x01 /* Com1 */ +#define IT8528E_SP2 0x02 /* Com2 */ +#define IT8587E_SWUC 0x04 /* System Wake-Up */ +#define IT8587E_KBCM 0x05 /* PS/2 mouse */ +#define IT8587E_KBCK 0x06 /* PS/2 keyboard */ +#define IT8587E_SMFI 0x0f /* Shared Memory/Flash Interface */ +#define IT8587E_RTCT 0x10 /* RTC-like Timer */ +#define IT8587E_PMC1 0x11 /* Power Management Channel 1 */ +#define IT8587E_PMC2 0x12 /* Power Management Channel 2 */ +#define IT8587E_SSPI 0x13 /* Serial Periphial Interface */ +#define IT8587E_PECI 0x14 /* Platform EC Interface */ +#define IT8587E_PMC3 0x17 /* Power Management Channel 3 */ +#define IT8587E_PMC4 0x18 /* Power Management Channel 4 */ +#define IT8587E_PMC5 0x19 /* Power Management Channel 5 */ + + +#endif /* SUPERIO_ITE_IT8587E_H */ diff --git a/src/superio/ite/it8587e/superio.c b/src/superio/ite/it8587e/superio.c new file mode 100644 index 0000000..cdb97e6 --- /dev/null +++ b/src/superio/ite/it8587e/superio.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> + * Copyright (C) 2017 Gergely Kiss <mail.gery(a)gmail.com> + * Copyright (C) 2019 9Elements GmbH <patrick.rudolph(a)9elements.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <stdlib.h> +#include <superio/conf_mode.h> + +#include "it8587e.h" + +static void it8587e_init(struct device *dev) +{ +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8587e_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, IT8587E_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, + { NULL, IT8587E_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, + { NULL, IT8587E_SWUC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + /* Documentation: Unused */ + { NULL, IT8587E_KBCM, PNP_IRQ0, }, + /* Documentation: Program io0 = 0x60 and io1 = 0x64 */ + { NULL, IT8587E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, }, + { NULL, IT8587E_SMFI, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + /* Documentation: Program io0 = 0x70-0x73 */ + { NULL, IT8587E_RTCT, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0, + 0xfffe, 0xfffe, 0xfffe, 0xfffe}, + /* Documentation: Program io0 = 0x62 and io1 = 0x66 */ + { NULL, IT8587E_PMC1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff }, + /* Documentation: Program io0 = 0x68 and io1 = 0x6c */ + { NULL, IT8587E_PMC2, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07fc, 0x07fc }, + /* Documentation: Program io0 = 0x6a and io1 = 0x6e */ + { NULL, IT8587E_PMC3, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff }, + { NULL, IT8587E_PMC4, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff }, + { NULL, IT8587E_PMC5, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff }, + { NULL, IT8587E_SSPI, PNP_IO0 | PNP_IRQ0, 0xfff8 }, + { NULL, IT8528E_PECI, PNP_IO0, 0xfff8 }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8587e_ops = { + CHIP_NAME("ITE IT8587E Super I/O") + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/36071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e541daa2b3d48a4f5a0e7b7fa88a2c2f8a1b0c5 Gerrit-Change-Number: 36071 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: WIP: mb/riscv-qemu: Switch to -pflash option in Qemu > 4.2
by Philipp Hug (Code Review) 07 Aug '23

07 Aug '23

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36487 ) Change subject: WIP: mb/riscv-qemu: Switch to -pflash option in Qemu > 4.2 ...................................................................... WIP: mb/riscv-qemu: Switch to -pflash option in Qemu > 4.2 Instead of loading coreboot in the RAM, newer Qemu version support providing it as flash using the -pflash option. Currently qemu limits the flash size to 2*16MiB. This will hopefully be changed to 2*32MiB before release of 4.2. Change-Id: I5dd47d55bbaf26bddfc8378e48fa247c2f4c1988 --- M Documentation/mainboard/emulation/qemu-riscv.md M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/qemu-riscv/rom_media.c 5 files changed, 22 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/36487/1 diff --git a/Documentation/mainboard/emulation/qemu-riscv.md b/Documentation/mainboard/emulation/qemu-riscv.md index 3aad816..faae1e5 100644 --- a/Documentation/mainboard/emulation/qemu-riscv.md +++ b/Documentation/mainboard/emulation/qemu-riscv.md @@ -2,7 +2,11 @@ ## Building coreboot and running it in Qemu +### Qemu >= 4.2 - Configure coreboot and run `make` as usual +- Run `qemu-system-riscv64 -M virt -m 1024M -nographic -pflash build/coreboot.rom` + +### Qemu < 4.2 - Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to convert coreboot to an ELF that Qemu can load - Run `qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf` diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index fa6dccc..7d6fe48 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -12,11 +12,6 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -# To execute, do: -# util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf -# qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf - - if BOARD_EMULATION_QEMU_RISCV_RV64 config BOARD_EMULATION_QEMU_RISCV @@ -65,19 +60,6 @@ # ugly, but CBFS is placed in DRAM... config OPENSBI_TEXT_START hex - default 0x80010000 if COREBOOT_ROMSIZE_KB_64 - default 0x80020000 if COREBOOT_ROMSIZE_KB_128 - default 0x80040000 if COREBOOT_ROMSIZE_KB_256 - default 0x80080000 if COREBOOT_ROMSIZE_KB_512 - default 0x80100000 if COREBOOT_ROMSIZE_KB_1024 - default 0x80200000 if COREBOOT_ROMSIZE_KB_2048 - default 0x80400000 if COREBOOT_ROMSIZE_KB_4096 - default 0x80600000 if COREBOOT_ROMSIZE_KB_6144 - default 0x80800000 if COREBOOT_ROMSIZE_KB_8192 - default 0x80a00000 if COREBOOT_ROMSIZE_KB_10240 - default 0x80c00000 if COREBOOT_ROMSIZE_KB_12288 - default 0x81000000 if COREBOOT_ROMSIZE_KB_16384 - default 0x82000000 if COREBOOT_ROMSIZE_KB_32768 - default 0x84000000 if COREBOOT_ROMSIZE_KB_65536 + default 0x80000000 endif # BOARD_EMULATION_QEMU_RISCV diff --git a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h index fd8c136..4bb5e98 100644 --- a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h +++ b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h @@ -17,4 +17,5 @@ #define QEMU_VIRT_PLIC 0x0c000000 #define QEMU_VIRT_UART0 0x10000000 #define QEMU_VIRT_VIRTIO 0x10001000 +#define QEMU_VIRT_FLASH 0x20000000 #define QEMU_VIRT_DRAM 0x80000000 diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index b29bc14..46f360f 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -17,26 +17,24 @@ #include <arch/header.ld> #include <mainboard/addressmap.h> -// Stages start after CBFS in DRAM -#define STAGES_START (QEMU_VIRT_DRAM + CONFIG_ROM_SIZE) +#define FLASH_START(addr) SYMBOL(flash, addr) +#define FLASH_END(addr) SYMBOL(eflash, addr) SECTIONS { - // the virt target doesn't emulate flash and just puts the CBFS into DRAM. - // fake SRAM where CBFS resides. It's only done for better integration. - SRAM_START(QEMU_VIRT_DRAM) - BOOTBLOCK(QEMU_VIRT_DRAM, 64K) - // CBFS goes here - SRAM_END(STAGES_START) - DRAM_START(STAGES_START) + FLASH_START(QEMU_VIRT_FLASH) + BOOTBLOCK(QEMU_VIRT_FLASH, 64K) + FLASH_END(QEMU_VIRT_FLASH + 64K) -#if ENV_ROMSTAGE - ROMSTAGE(STAGES_START, 128K) -#endif + DRAM_START(QEMU_VIRT_DRAM) #if ENV_RAMSTAGE - REGION(opensbi, STAGES_START, 128K, 4K) + REGION(opensbi, QEMU_VIRT_DRAM, 128K, 4K) #endif - PRERAM_CBMEM_CONSOLE(STAGES_START + 128K, 8K) - RAMSTAGE(STAGES_START + 200K, 16M) - STACK(STAGES_START + 200K + 16M, 4K) +#if ENV_ROMSTAGE + ROMSTAGE(QEMU_VIRT_DRAM + 128K, 128K) +#endif + // TODO, drop the 15M hack + RAMSTAGE(QEMU_VIRT_DRAM + 256K, 15M) + PRERAM_CBMEM_CONSOLE(QEMU_VIRT_DRAM + 256K + 15M, 8K) + STACK(QEMU_VIRT_DRAM + 256K + 15M + 8K, 4K) } diff --git a/src/mainboard/emulation/qemu-riscv/rom_media.c b/src/mainboard/emulation/qemu-riscv/rom_media.c index 79e5ca8..7349ecb 100644 --- a/src/mainboard/emulation/qemu-riscv/rom_media.c +++ b/src/mainboard/emulation/qemu-riscv/rom_media.c @@ -15,11 +15,10 @@ */ #include <boot_device.h> #include <symbols.h> +#include <mainboard/addressmap.h> -/* This assumes that the CBFS resides at start of dram, which is true for the - * default configuration. */ static const struct mem_region_device boot_dev = - MEM_REGION_DEV_RO_INIT(_sram, CONFIG_ROM_SIZE); + MEM_REGION_DEV_RO_INIT(QEMU_VIRT_FLASH, CONFIG_ROM_SIZE); const struct region_device *boot_device_ro(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/36487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5dd47d55bbaf26bddfc8378e48fa247c2f4c1988 Gerrit-Change-Number: 36487 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: src/mb/intel/coffeelake_rvp: Add mainboard for CML-S RVP8
by Gaggery Tsai (Code Review) 07 Aug '23

07 Aug '23

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36685 ) Change subject: src/mb/intel/coffeelake_rvp: Add mainboard for CML-S RVP8 ...................................................................... src/mb/intel/coffeelake_rvp: Add mainboard for CML-S RVP8 This patches adds an initial commit for Intel CML-S RVP board support and rename the original CML-U RVP to RVPU to avoid confusing. It adds an additional GBE region in fmd file as well. TEST=build an image and boot to UEFI payload Change-Id: Idf723ada53dc441cb9fabc8efb1dcd3da8e0991c Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/coffeelake_rvp/Kconfig.name M src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c A src/mainboard/intel/coffeelake_rvp/variants/cml_s/devicetree.cb A src/mainboard/intel/coffeelake_rvp/variants/cml_s/include/variant/hda_verb.h 6 files changed, 398 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/36685/1 diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 13e55b3..13cba46 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -1,9 +1,9 @@ -if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COFFEELAKE_RVP8 || BOARD_INTEL_COMETLAKE_RVP +if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COFFEELAKE_RVP8 || BOARD_INTEL_COMETLAKE_RVPU || BOARD_INTEL_COMETLAKE_RVP8 config BOARD_SPECIFIC_OPTIONS def_bool y - select BOARD_ROMSIZE_KB_16384 if !BOARD_INTEL_COFFEELAKE_RVPU - select BOARD_ROMSIZE_KB_32768 if BOARD_INTEL_COFFEELAKE_RVPU + select BOARD_ROMSIZE_KB_16384 if !(BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_COMETLAKE_RVP8) + select BOARD_ROMSIZE_KB_32768 if BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_COMETLAKE_RVP8 select GENERIC_SPD_BIN select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES @@ -11,11 +11,11 @@ select MAINBOARD_HAS_CHROMEOS select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC - select SOC_INTEL_CANNONLAKE_PCH_H if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 + select SOC_INTEL_CANNONLAKE_PCH_H if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 || BOARD_INTEL_COMETLAKE_RVP8 select SOC_INTEL_COMMON_BLOCK_HDA_VERB if !BOARD_INTEL_COFFEELAKE_RVPU - select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COMETLAKE_RVP + select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COMETLAKE_RVPU select MAINBOARD_USES_IFD_EC_REGION - select MAINBOARD_USES_IFD_GBE_REGION if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 + select MAINBOARD_USES_IFD_GBE_REGION if BOARD_INTEL_COFFEELAKE_RVP11 config MAINBOARD_DIR string @@ -27,12 +27,13 @@ default "cfl_h" if BOARD_INTEL_COFFEELAKE_RVP11 default "whl_u" if BOARD_INTEL_WHISKEYLAKE_RVP default "cfl_s" if BOARD_INTEL_COFFEELAKE_RVP8 - default "cml_u" if BOARD_INTEL_COMETLAKE_RVP + default "cml_u" if BOARD_INTEL_COMETLAKE_RVPU + default "cml_s" if BOARD_INTEL_COMETLAKE_RVP8 config MAINBOARD_PART_NUMBER string default "whlrvp" if BOARD_INTEL_WHISKEYLAKE_RVP - default "cmlrvp" if BOARD_INTEL_COMETLAKE_RVP + default "cmlrvp" if BOARD_INTEL_COMETLAKE_RVPU || BOARD_INTEL_COMETLAKE_RVP8 default "cflrvp" config MAINBOARD_VENDOR @@ -42,7 +43,7 @@ config MAINBOARD_FAMILY string default "Intel_whlrvp" if BOARD_INTEL_WHISKEYLAKE_RVP - default "Intel_cmlrvp" if BOARD_INTEL_COMETLAKE_RVP + default "Intel_cmlrvp" if BOARD_INTEL_COMETLAKE_RVPU || BOARD_INTEL_COMETLAKE_RVP8 default "Intel_cflrvp" config CHROMEOS @@ -53,7 +54,7 @@ config MAX_CPUS int - default 12 if BOARD_INTEL_COFFEELAKE_RVP11 + default 12 if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COMETLAKE_RVP8 default 16 if BOARD_INTEL_COFFEELAKE_RVP8 default 8 diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig.name b/src/mainboard/intel/coffeelake_rvp/Kconfig.name index 35c0f0f..3e5bf19 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig.name +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig.name @@ -12,6 +12,10 @@ config BOARD_INTEL_COFFEELAKE_RVP8 bool "-> Coffeelake S U-DIMM DDR4 RVP8" select SOC_INTEL_COFFEELAKE -config BOARD_INTEL_COMETLAKE_RVP +config BOARD_INTEL_COMETLAKE_RVPU bool "-> Cometlake U DDR4 RVP" select SOC_INTEL_COMETLAKE +config BOARD_INTEL_COMETLAKE_RVP8 + bool "-> Cometlake S U-DIMM DDR4 RVP8" + select SOC_INTEL_COMETLAKE +~ diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd b/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd index 62e0f5d..521716a 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd +++ b/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd @@ -1,8 +1,9 @@ FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x1081000 { + SI_ALL@0x0 0x1083000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x80000 - SI_ME@0x81000 0x1000000 + SI_GBE@0x81000 0x2000 + SI_ME@0x83000 0x1000000 } SI_BIOS@0x1400000 0xC00000 { RW_SECTION_A@0x0 0x2d0000 { diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c index ec8f58b..0295d93 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Intel Corporation. + * Copyright 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -264,7 +264,7 @@ /* H21 : GPPC_H_21 */ /* H22 : GPPC_H_22 */ PAD_CFG_GPI(GPP_H22, NONE, DEEP), -#if CONFIG(BOARD_INTEL_WHISKEYLAKE_RVP) || CONFIG(BOARD_INTEL_COMETLAKE_RVP) +#if CONFIG(BOARD_INTEL_WHISKEYLAKE_RVP) || CONFIG(BOARD_INTEL_COMETLAKE_RVPU) PAD_CFG_GPO(GPP_H22, 1, PLTRST), #else PAD_CFG_GPI(GPP_H22, NONE, DEEP), @@ -466,8 +466,11 @@ /* F17 : USB2_OC_6 */ /* F18 : USB2_OC_7 */ /* F19 : EDP_VDDEN */ + PAD_CFG_NF(GPP_F19, NONE, PLTRST, NF1), /* F20 : EDP_BKLTEN */ + PAD_CFG_NF(GPP_F20, NONE, PLTRST, NF1), /* F21 : EDP_BKLTCTL */ + PAD_CFG_NF(GPP_F21, NONE, PLTRST, NF1), /* F22 : DDPF_C_TRLCLK */ /* F23 : DDPF_C_TRLDATA */ @@ -512,16 +515,27 @@ PAD_CFG_GPI_SCI_LOW(GPP_H23, NONE, PLTRST, EDGE_SINGLE), /* I0 : DDPB_HPD_0 */ + PAD_CFG_NF(GPP_I0, UP_20K, PLTRST, NF1), /* I1 : DDPC_HPD_1 */ + PAD_CFG_NF(GPP_I1, UP_20K, PLTRST, NF1), /* I2 : DPPD_HPD_2 */ + PAD_CFG_NF(GPP_I2, UP_20K, PLTRST, NF1), /* I3 : DPPE_HPD_3 */ + PAD_CFG_NF(GPP_I3, UP_20K, PLTRST, NF1), /* I4 : EDP_HPD */ + PAD_CFG_NF(GPP_I4, UP_20K, PLTRST, NF1), /* I5 : DDPB_C_TRLCLK */ + PAD_CFG_NF(GPP_I5, UP_20K, PLTRST, NF1), /* I6 : DDPB_C_TRLDATA */ + PAD_CFG_NF(GPP_I6, UP_20K, PLTRST, NF1), /* I7 : DDPC_C_TRLCLK */ + PAD_CFG_NF(GPP_I7, UP_20K, PLTRST, NF1), /* I8 : DDPC_C_TRLDATA */ + PAD_CFG_NF(GPP_I8, UP_20K, PLTRST, NF1), /* I9 : DDPD_C_TRLCLK */ + PAD_CFG_NF(GPP_I9, UP_20K, PLTRST, NF1), /* I10 : DDPD_C_TRLDATA */ + PAD_CFG_NF(GPP_I10, UP_20K, PLTRST, NF1), /* I11 : M2_SKT2_C_FG0 */ /* I12 : M2_SKT2_CFG1 */ /* I13 : M2_SKT2_C_FG2 */ diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_s/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_s/devicetree.cb new file mode 100644 index 0000000..7a93af0 --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_s/devicetree.cb @@ -0,0 +1,163 @@ +chip soc/intel/cannonlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "RMT" = "1" + register "ScsEmmcHs400Enabled" = "1" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC7)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC7)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[6]" = "USB2_PORT_TYPE_C(OC6)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC3)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC5)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC5)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[13]" = "USB2_PORT_EMPTY" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC4)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC7)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" + register "usb3_ports[8]" = "USB3_PORT_EMPTY" + register "usb3_ports[9]" = "USB3_PORT_EMPTY" + + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "0" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "1" + register "SataPortsEnable[7]" = "1" + + register "PchHdaDspEnable" = "0" + register "PchHdaAudioLinkHda" = "1" + + register "PcieRpEnable[0]" = "0" + register "PcieRpEnable[1]" = "0" + + # PCIe root port 3 for GBe LAN + register "PcieRpEnable[2]" = "1" + # RP 3 uses CLK SRC 8 + register "PcieClkSrcUsage[8]" = "2" + # ClkReq-to-ClkSrc mapping for CLK SRC 8 + register "PcieClkSrcClkReq[8]" = "8" + + # PCIe root port 4 for M.2 Wi-Fi + register "PcieRpEnable[3]" = "1" + register "PcieRpLtrEnable[3]" = "1" + # RP 4 uses CLK SRC 0 + register "PcieClkSrcUsage[0]" = "3" + # ClkReq-to-ClkSrc mapping for CLK SRC 0 + register "PcieClkSrcClkReq[0]" = "0" + + # PCIe root port 9 for X4 slot + register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[11]" = "1" + # RP 9 uses CLK SRC 4 + register "PcieClkSrcUsage[4]" = "8" + + # PCIe root port 13 for GBe LAN + register "PcieRpEnable[12]" = "1" + # RP 13 uses CLK SRC 1 + register "PcieClkSrcUsage[1]" = "12" + # ClkReq-to-ClkSrc mapping for CLK SRC 1 + register "PcieClkSrcClkReq[1]" = "1" + + # PCIe root port 17 for X4 M.2 SSD + register "PcieRpEnable[16]" = "1" + register "PcieRpEnable[17]" = "1" + register "PcieRpEnable[18]" = "1" + register "PcieRpEnable[19]" = "1" + # RP 17 uses CLK SRC 2 + register "PcieClkSrcUsage[2]" = "16" + # ClkReq-to-ClkSrc mapping for CLK SRC 1 + register "PcieClkSrcClkReq[2]" = "2" + + # PCIe root port 21 for X4 slot + register "PcieRpEnable[20]" = "1" + register "PcieRpEnable[21]" = "1" + register "PcieRpEnable[22]" = "1" + register "PcieRpEnable[23]" = "1" + # RP 21 uses CLK SRC 5 + register "PcieClkSrcUsage[5]" = "20" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # HECI + register "HeciEnabled" = "1" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + chip drivers/intel/wifi + register "wake" = "PME_B0_EN_BIT" + device pci 14.3 on end # CNVi wifi + end + device pci 14.5 on end # SDCard + device pci 15.0 on end # I2C 0 + device pci 15.1 on end # I2C #1 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 off end # I2C #4 + device pci 19.2 off end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 X4 SLOT 1 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1b.0 on end # PCI Express Port 17 M.2 SSD + device pci 1b.4 on end # PCI Express Port 21 X4 SLOT 2 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on end # LPC + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_s/include/variant/hda_verb.h b/src/mainboard/intel/coffeelake_rvp/variants/cml_s/include/variant/hda_verb.h new file mode 100644 index 0000000..f921f3f --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_s/include/variant/hda_verb.h @@ -0,0 +1,200 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Damien Zammit <damien(a)zamaudio.com> + * Copyright 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + + /* + * VerbTable: CFL Display Audio Codec + * Revision ID = 0xFF + * Codec Vendor: 0x8086280B + */ + + 0x8086280B, + 0xFFFFFFFF, + 0x00000005, + + /* + * Display Audio Verb Table + * For GEN9, the Vendor Node ID is 08h + * Port to be exposed to the inbox driver in the vanilla mode + * PORT C - BIT[7:6] = 01b + */ + 0x00878140, + 0x00878140, + 0x00878140, + 0x00878140, + /* Pin Widget 5 - PORT B - Configuration Default: 0x18560010 */ + 0x00571C10, + 0x00571D00, + 0x00571E56, + 0x00571F18, + /* Pin Widget 6 - PORT C - Configuration Default: 0x18560020 */ + 0x00671C20, + 0x00671D00, + 0x00671E56, + 0x00671F18, + /* Pin Widget 7 - PORT D - Configuration Default: 0x18560030 */ + 0x00771C30, + 0x00771D00, + 0x00771E56, + 0x00771F18, + /* Disable the third converter and third Pin (NID 08h) */ + 0x00878140, + 0x00878140, + 0x00878140, + 0x00878140, + + /* ALC700 */ + 0x10EC0700, + 0xFFFFFFFF, + 0x00000015, + + /* + * HDA Codec Subsystem ID Verb-table + * HDA Codec Subsystem ID : 0x10EC112C + */ + 0x0017202C, + 0x00172111, + 0x001722EC, + 0x00172310, + + /* + * Pin Widget Verb-table + * Widget node 0x01 + */ + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + /* Pin widget 0x12 - DMIC */ + 0x01271C00, + 0x01271D00, + 0x01271E00, + 0x01271F40, + /* Pin widget 0x13 - DMIC */ + 0x01371CF0, + 0x01371D11, + 0x01371E11, + 0x01371F41, + /* Pin widget 0x14 - FRONT (Port-D) */ + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + /* Pin widget 0x15 - I2S-OUT */ + 0x01571C10, + 0x01571D01, + 0x01571E17, + 0x01571F90, + /* Pin widget 0x16 - LINE3 (Port-B) */ + 0x01671C20, + 0x01671D10, + 0x01671E01, + 0x01671F01, + /* Pin widget 0x17 - I2S-OUT */ + 0x01771CF0, + 0x01771D11, + 0x01771E11, + 0x01771F41, + /* Pin widget 0x18 - I2S-IN */ + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + /* Pin widget 0x19 - MIC2 (Port-F) */ + 0x01971C30, + 0x01971D90, + 0x01971EA1, + 0x01971F02, + /* Pin widget 0x1A - LINE1 (Port-C) */ + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + /* Pin widget 0x1B - LINE2 (Port-E) */ + 0x01B71C40, + 0x01B71D90, + 0x01B71EA1, + 0x01B71F01, + /* Pin widget 0x1D - PC-BEEP */ + 0x01D71C69, + 0x01D71D84, + 0x01D71E45, + 0x01D71F40, + /* Pin widget 0x1E - S/PDIF-OUT */ + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + /* Pin widget 0x1F - S/PDIF-IN */ + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + /* Pin widget 0x21 - P-OUT (Port-I) */ + 0x02171C2F, + 0x02171D10, + 0x02171E21, + 0x02171F02, + /* Pin widget 0x29 - I2S-IN */ + 0x02971CF0, + 0x02971D11, + 0x02971E11, + 0x02971F41, + /* + * Widget node 0x20 : MIC2-Vrefo-R and MIC2-vrefo-L + * to independent control + */ + 0x02050045, + 0x02045089, + 0x0205004A, + 0x0204201B, + /* Widget node 0x20 - 1 */ + 0x05850000, + 0x05843888, + 0x0205006F, + 0x02042C0B, + /* + * Widget node 0x20 - 2 : Line2-JD gating MIC2-Vrefo-R, + * P-JD gating MIC2-vrefo-L + */ + 0x0205006B, + 0x02044260, + 0x05B50010, + 0x05B45C1D, + + /* Widget node 0X20 for ALC1305 */ + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040000, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + +}; + +const u32 pc_beep_verbs[] = { +}; + +AZALIA_ARRAY_SIZES; +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/36685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf723ada53dc441cb9fabc8efb1dcd3da8e0991c Gerrit-Change-Number: 36685 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-MessageType: newchange

9 44

Change in coreboot[master]: cpu/x86/smm: Remove usused Kconfig symbol
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36977 ) Change subject: cpu/x86/smm: Remove usused Kconfig symbol ...................................................................... cpu/x86/smm: Remove usused Kconfig symbol These platforms now use parallel mp. Change-Id: I73527a7feb6151d765295d6449262a2852b30177 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/Kconfig M src/cpu/x86/smm/smmhandler.S 2 files changed, 0 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/36977/1 diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 85ebd83..5004cfd 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -137,13 +137,6 @@ endif -config SMM_LAPIC_REMAP_MITIGATION - bool - default y if NORTHBRIDGE_INTEL_I945 - default y if NORTHBRIDGE_INTEL_GM45 - default y if NORTHBRIDGE_INTEL_NEHALEM - default n - config SERIALIZED_SMM_INITIALIZATION bool default n diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index a2be7f2..6e8941e 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -75,36 +75,6 @@ #endif .global smm_handler_start smm_handler_start: -#if CONFIG(SMM_LAPIC_REMAP_MITIGATION) - /* Check if the LAPIC register block overlaps with SMM. - * This block needs to work without data accesses because they - * may be routed into the LAPIC register block. - * Code accesses, on the other hand, are never routed to LAPIC, - * which is what makes this work in the first place. - */ - mov $LAPIC_BASE_MSR, %ecx - rdmsr - and $(~0xfff), %eax - sub $(SMM_START), %eax - cmp $(SMM_END - SMM_START), %eax - ja untampered_lapic -1: - /* emit "Crash" on serial */ - mov $(CONFIG_TTYS0_BASE), %dx - mov $'C', %al - out %al, (%dx) - mov $'r', %al - out %al, (%dx) - mov $'a', %al - out %al, (%dx) - mov $'s', %al - out %al, (%dx) - mov $'h', %al - out %al, (%dx) - /* now crash for real */ - ud2 -untampered_lapic: -#endif movw $(smm_gdtptr16 - smm_handler_start + SMM_HANDLER_OFFSET), %bx lgdtl %cs:(%bx) -- To view, visit https://review.coreboot.org/c/coreboot/+/36977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73527a7feb6151d765295d6449262a2852b30177 Gerrit-Change-Number: 36977 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/google: Fix Hatch baseboard/gpio.c default mux
by Edward O'Callaghan (Code Review) 07 Aug '23

07 Aug '23

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36988 ) Change subject: mainboard/google: Fix Hatch baseboard/gpio.c default mux ...................................................................... mainboard/google: Fix Hatch baseboard/gpio.c default mux The schematics seem to suggest F20,F21,F11,F22 are all NC. BUG=b:144809606 Change-Id: Ide74ab6361f48f0e9c967b9e4318537f605bee2d Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/36988/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 598600b..d8625b9 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -301,12 +301,12 @@ PAD_NC(GPP_F18, NONE), /* F19 : GPP_F19 ==> NC */ PAD_NC(GPP_F19, NONE), - /* F20 : PCH_MEM_STRAP0 */ - PAD_CFG_GPI(GPP_F20, NONE, PLTRST), - /* F21 : PCH_MEM_STRAP1 */ - PAD_CFG_GPI(GPP_F21, NONE, PLTRST), - /* F22 : PCH_MEM_STRAP3 */ - PAD_CFG_GPI(GPP_F22, NONE, PLTRST), + /* F20 : GPP_F20 ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : GPP_F21 ==> NC */ + PAD_NC(GPP_F21, NONE), + /* F22 : GPP_F22 ==> NC */ + PAD_NC(GPP_F22, NONE), /* F23 : GPP_F23 ==> NC */ PAD_NC(GPP_F23, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/36988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide74ab6361f48f0e9c967b9e4318537f605bee2d Gerrit-Change-Number: 36988 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: arch/riscv: Add error detection for supports_extension
by Xiang Wang (Code Review) 07 Aug '23

07 Aug '23

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37130 ) Change subject: arch/riscv: Add error detection for supports_extension ...................................................................... arch/riscv: Add error detection for supports_extension Change-Id: I5df3d82b9a9b4968beea6040b86628b58fd8a45d Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org> --- M src/arch/riscv/include/arch/cpu.h 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/37130/1 diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h index 72a8a69..dd70af7 100644 --- a/src/arch/riscv/include/arch/cpu.h +++ b/src/arch/riscv/include/arch/cpu.h @@ -49,7 +49,7 @@ * */ int soc_supports_extension(char ext); -static inline int supports_extension(char ext) +static inline int supports_extension_imp(char ext) { uintptr_t isa = read_csr(misa); if (isa) @@ -58,6 +58,13 @@ return soc_supports_extension(ext); } +#define supports_extension(c)\ +({\ + _Static_assert(((c >= 'A') && (c <= 'Z')),\ + "The parameter of supports_extension must be [A-Z]");\ + supports_extension_imp(c);\ +}) + /* If the SOC does not implement misa, the read misa will be zero. * Such SOC requires a non-standard mechanism to detect machine XLEN. * If the soc does not implement misa, implement this function. -- To view, visit https://review.coreboot.org/c/coreboot/+/37130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5df3d82b9a9b4968beea6040b86628b58fd8a45d Gerrit-Change-Number: 37130 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-MessageType: newchange

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