Change in coreboot[master]: soc/intel/baytrail: Use common sb code for SPI lockdown configuration
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36009 )
Change subject: soc/intel/baytrail: Use common sb code for SPI lockdown configuration ......................................................................
soc/intel/baytrail: Use common sb code for SPI lockdown configuration
This removes the weakly linked function to configure the SPI lockdown.
Change-Id: I10c00f6c8a0928210faa7c91a32a745d282088e9 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/google/rambi/w25q64.c M src/soc/intel/baytrail/include/soc/spi.h M src/soc/intel/baytrail/southcluster.c 3 files changed, 16 insertions(+), 61 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/36009/1
diff --git a/src/mainboard/google/rambi/w25q64.c b/src/mainboard/google/rambi/w25q64.c index a9ed8ac..114c8c7 100644 --- a/src/mainboard/google/rambi/w25q64.c +++ b/src/mainboard/google/rambi/w25q64.c @@ -17,52 +17,16 @@ #include <soc/spi.h>
/* - * SPI lockdown configuration W25Q64FW. + * SPI VSCC configuration W25Q64FW. */ -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ - -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ - -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ - -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ - -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ - -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ - -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ - -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ -#define SPI_OPTYPE_7 0x02 /* Read, address required */ - -#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) #define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB)
-static const struct spi_config spi_config = { - .preop = SPI_OPPREFIX, - .optype = SPI_OPTYPE, - .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, +static const struct vscc_config spi_config = { .lvscc = SPI_VSCC, .uvscc = SPI_VSCC, };
-int mainboard_get_spi_config(struct spi_config *cfg) +int mainboard_get_spi_vscc_config(struct vscc_config *cfg) { memcpy(cfg, &spi_config, sizeof(*cfg));
diff --git a/src/soc/intel/baytrail/include/soc/spi.h b/src/soc/intel/baytrail/include/soc/spi.h index 063dd7f..61e430b 100644 --- a/src/soc/intel/baytrail/include/soc/spi.h +++ b/src/soc/intel/baytrail/include/soc/spi.h @@ -54,17 +54,14 @@ # define BCR_WPD (0x1 << 0)
/* - * SPI lockdown configuration. + * SPI VSCC configuration. */ -struct spi_config { - uint16_t preop; - uint16_t optype; - uint32_t opmenu[2]; - uint32_t lvscc; - uint32_t uvscc; -}; + struct vscc_config { + uint32_t lvscc; + uint32_t uvscc; + };
/* Return 0 on success < 0 on failure. */ -int mainboard_get_spi_config(struct spi_config *cfg); +int mainboard_get_spi_vscc_config(struct vscc_config *cfg);
#endif /* _BAYTRAIL_SPI_H_ */ diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 139d2be..f5bbda6 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -42,6 +42,7 @@ #include <soc/spi.h> #include "chip.h" #include <arch/acpigen.h> +#include <southbridge/intel/common/spi.h>
static inline void add_mmio_resource(struct device *dev, int i, unsigned long addr, @@ -540,11 +541,6 @@ .device = LPC_DEVID, };
-int __weak mainboard_get_spi_config(struct spi_config *cfg) -{ - return -1; -} - static void finalize_chipset(void *unused) { u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); @@ -552,7 +548,7 @@ u32 *gen_pmcon2 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2); u32 *etr = (u32 *)(PMC_BASE_ADDRESS + ETR); u8 *spi = (u8 *)SPI_BASE_ADDRESS; - struct spi_config cfg; + struct vscc_config cfg;
/* Set the lock enable on the BIOS control register. */ write32(bcr, read32(bcr) | BCR_LE); @@ -566,14 +562,12 @@ /* Set the CF9 lock. */ write32(etr, read32(etr) | CF9LOCK);
- if (mainboard_get_spi_config(&cfg) < 0) { - printk(BIOS_DEBUG, "No SPI lockdown configuration.\n"); + spi_finalize_ops(); + write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN); + + if (mainboard_get_spi_vscc_config(&cfg) < 0) { + printk(BIOS_DEBUG, "No SPI VSCC configuration.\n"); } else { - write16(spi + PREOP, cfg.preop); - write16(spi + OPTYPE, cfg.optype); - write32(spi + OPMENU0, cfg.opmenu[0]); - write32(spi + OPMENU1, cfg.opmenu[1]); - write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN); write32(spi + UVSCC, cfg.uvscc); write32(spi + LVSCC, cfg.lvscc | VCL); }
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36009
to look at the new patch set (#9).
Change subject: soc/intel/baytrail: Use common sb code for SPI lockdown configuration ......................................................................
soc/intel/baytrail: Use common sb code for SPI lockdown configuration
This removes the weakly linked function to configure the SPI lockdown.
Change-Id: I10c00f6c8a0928210faa7c91a32a745d282088e9 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/google/rambi/w25q64.c M src/soc/intel/baytrail/include/soc/spi.h M src/soc/intel/baytrail/southcluster.c 3 files changed, 16 insertions(+), 65 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/36009/9
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36009 )
Change subject: soc/intel/baytrail: Use common sb code for SPI lockdown configuration ......................................................................
Patch Set 12: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/36009/12/src/soc/intel/baytrail/inc... File src/soc/intel/baytrail/include/soc/spi.h:
https://review.coreboot.org/c/coreboot/+/36009/12/src/soc/intel/baytrail/inc... PS12, Line 51: }; indentation?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36009 )
Change subject: soc/intel/baytrail: Use common sb code for SPI lockdown configuration ......................................................................
Patch Set 14: Code-Review+1
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36009 )
Change subject: soc/intel/baytrail: Use common sb code for SPI lockdown configuration ......................................................................
Patch Set 14: Code-Review+1
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/36009?usp=email )
Change subject: soc/intel/baytrail: Use common sb code for SPI lockdown configuration ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
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Angel Pons (Code Review) -
Arthur Heymans (Code Review)
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Frans Hendriks (Code Review)
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Martin L Roth (Code Review)
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Nico Huber (Code Review)