coreboot-gerrit August 2022

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Change in coreboot[master]: cpu/intel/haswell: add Crystal Well CPU IDs
by Iru Cai (vimacs) (Code Review) 11 Sep '22

11 Sep '22

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44066 to review the following change. Change subject: cpu/intel/haswell: add Crystal Well CPU IDs ...................................................................... cpu/intel/haswell: add Crystal Well CPU IDs Change-Id: Ife4ae71fd977d32d7b11ee7e2a1a7e2ec3eec52f Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M src/cpu/intel/haswell/haswell_init.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/44066/1 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index e621638..5f3debb 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -778,6 +778,8 @@ { X86_VENDOR_INTEL, 0x306c3 }, /* Intel Haswell C0 */ { X86_VENDOR_INTEL, 0x40650 }, /* Intel Haswell ULT B0 */ { X86_VENDOR_INTEL, 0x40651 }, /* Intel Haswell ULT B1 */ + { X86_VENDOR_INTEL, 0x40660 }, /* Intel Crystal Well C0 */ + { X86_VENDOR_INTEL, 0x40661 }, /* Intel Crystal Well C1 */ { 0, 0 }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/44066 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife4ae71fd977d32d7b11ee7e2a1a7e2ec3eec52f Gerrit-Change-Number: 44066 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/haswell: Add Broadwell CPUIDs and microcode
by Angel Pons (Code Review) 11 Sep '22

11 Sep '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46942 ) Change subject: cpu/intel/haswell: Add Broadwell CPUIDs and microcode ...................................................................... cpu/intel/haswell: Add Broadwell CPUIDs and microcode Broadwell can now use the Haswell CPU driver. Change-Id: I36138cab72b1e3ad0ff7f6434996f5ce00de9d0d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/haswell/haswell_init.c 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/46942/1 diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index b93b911..3c4db4f 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -23,3 +23,7 @@ cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3c-*) cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-45-*) + +ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) +cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin +endif diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 04f5802..577061c 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -728,6 +728,10 @@ { X86_VENDOR_INTEL, CPUID_HASWELL_ULT_C0 }, { X86_VENDOR_INTEL, CPUID_CRYSTALWELL_B0 }, { X86_VENDOR_INTEL, CPUID_CRYSTALWELL_C0 }, + { X86_VENDOR_INTEL, CPUID_BROADWELL_C0 }, + { X86_VENDOR_INTEL, CPUID_BROADWELL_ULT_C0 }, + { X86_VENDOR_INTEL, CPUID_BROADWELL_ULT_D0 }, + { X86_VENDOR_INTEL, CPUID_BROADWELL_ULT_E0 }, { 0, 0 }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/46942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36138cab72b1e3ad0ff7f6434996f5ce00de9d0d Gerrit-Change-Number: 46942 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: device: Introduce RESOURCE_ALLOCATION_TOP_DOWN
by Nico Huber (Code Review) 07 Sep '22

07 Sep '22

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41957 ) Change subject: device: Introduce RESOURCE_ALLOCATION_TOP_DOWN ...................................................................... device: Introduce RESOURCE_ALLOCATION_TOP_DOWN Add option to resource allocators v4 and v4.5 that restores the top-down allocation approach at the domain level. Change-Id: Iaf463d3e6b37d52e46761d8e210034fded58a8a4 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/device/Kconfig M src/device/resource_allocator_v4.5.c M src/device/resource_allocator_v4.c M src/include/memrange.h M src/lib/memrange.c 5 files changed, 37 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/41957/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index ee6fb21..35433b0 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -821,4 +821,8 @@ endchoice +config RESOURCE_ALLOCATION_TOP_DOWN + bool "Allocate resources from top down" + depends on RESOURCE_ALLOCATOR_V4 || RESOURCE_ALLOCATOR_V4_5 + endmenu diff --git a/src/device/resource_allocator_v4.5.c b/src/device/resource_allocator_v4.5.c index 6b9e712..4a03a23 100644 --- a/src/device/resource_allocator_v4.5.c +++ b/src/device/resource_allocator_v4.5.c @@ -403,7 +403,8 @@ if (!res->size) continue; - if (!memranges_steal(&ranges, res->limit, res->size, res->align, type, &base)) { + if (!memranges_steal(&ranges, res->limit, res->size, res->align, type, &base, + CONFIG(RESOURCE_ALLOCATION_TOP_DOWN))) { printk(BIOS_ERR, "ERROR: Resource didn't fit!!!\n"); print_failed_res(dev, res); continue; diff --git a/src/device/resource_allocator_v4.c b/src/device/resource_allocator_v4.c index 3a11032..4e967f2 100644 --- a/src/device/resource_allocator_v4.c +++ b/src/device/resource_allocator_v4.c @@ -365,6 +365,9 @@ static void allocate_child_resources(struct bus *bus, struct memranges *ranges, unsigned long type_mask, unsigned long type_match) { + const bool allocate_top_down = + bus->dev->path.type == DEVICE_PATH_DOMAIN && + CONFIG(RESOURCE_ALLOCATION_TOP_DOWN); struct resource *resource = NULL; const struct device *dev; @@ -373,8 +376,9 @@ if (!resource->size) continue; - if (memranges_steal(ranges, resource->limit, resource->size, resource->align, - type_match, &resource->base) == false) { + if (memranges_steal(ranges, resource->limit, resource->size, + resource->align, type_match, &resource->base, + allocate_top_down)) == false) { printk(BIOS_ERR, " ERROR: Resource didn't fit!!! "); printk(BIOS_DEBUG, " %s %02lx * size: 0x%llx limit: %llx %s\n", dev_path(dev), resource->index, diff --git a/src/include/memrange.h b/src/include/memrange.h index 2b8c00e..d50a9c8 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -161,15 +161,17 @@ const struct range_entry *r); /* Steals memory from the available list in given ranges as per the constraints: - * limit = Upper bound for the memory range to steal (Inclusive). - * size = Requested size for the stolen memory. - * align = Required alignment(log 2) for the starting address of the stolen memory. - * tag = Use a range that matches the given tag. + * limit = Upper bound for the memory range to steal (Inclusive). + * size = Requested size for the stolen memory. + * align = Required alignment(log 2) for the starting address of the stolen memory. + * tag = Use a range that matches the given tag. + * from_top = Steal the highest possible range. * * If the constraints can be satisfied, this function creates a hole in the memrange, * writes the base address of that hole to stolen_base and returns true. Otherwise it returns * false. */ bool memranges_steal(struct memranges *ranges, resource_t limit, resource_t size, - unsigned char align, unsigned long tag, resource_t *stolen_base); + unsigned char align, unsigned long tag, resource_t *stolen_base, + bool from_top); #endif /* MEMRANGE_H_ */ diff --git a/src/lib/memrange.c b/src/lib/memrange.c index 39f502c..2f6d55c 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -378,11 +378,11 @@ /* Find a range entry that satisfies the given constraints to fit a hole that matches the * required alignment, is big enough, does not exceed the limit and has a matching tag. */ -static const struct range_entry *memranges_find_entry(struct memranges *ranges, - resource_t limit, resource_t size, - unsigned char align, unsigned long tag) +static const struct range_entry * +memranges_find_entry(struct memranges *ranges, resource_t limit, resource_t size, + unsigned char align, unsigned long tag, bool last) { - const struct range_entry *r; + const struct range_entry *r, *last_entry = NULL; resource_t base, end; if (size == 0) @@ -407,25 +407,30 @@ if (end > limit) break; - return r; + if (!last) + return r; + + last_entry = r; } - return NULL; + return last_entry; } bool memranges_steal(struct memranges *ranges, resource_t limit, resource_t size, - unsigned char align, unsigned long tag, resource_t *stolen_base) + unsigned char align, unsigned long tag, resource_t *stolen_base, + bool from_top) { - resource_t base; - const struct range_entry *r = memranges_find_entry(ranges, limit, size, align, tag); + const struct range_entry *r; + r = memranges_find_entry(ranges, limit, size, align, tag, from_top); if (r == NULL) return false; - base = ALIGN_UP(r->begin, POWER_OF_2(align)); - - memranges_create_hole(ranges, base, size); - *stolen_base = base; + if (from_top) + *stolen_base = ALIGN_DOWN(range_entry_end(r) - size, POWER_OF_2(align)); + else + *stolen_base = ALIGN_UP(r->begin, POWER_OF_2(align)); + memranges_create_hole(ranges, *stolen_base, size); return true; } -- To view, visit https://review.coreboot.org/c/coreboot/+/41957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf463d3e6b37d52e46761d8e210034fded58a8a4 Gerrit-Change-Number: 41957 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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coreboot-gerrit August 2022