coreboot-gerrit July 2022

coreboot-gerrit@coreboot.org

673 discussions

Change in coreboot[master]: New PCI ID for Family 15h (Models 60h-6fh) I/O Memory Management Unit
by Name of user not set (Code Review) 07 Aug '23

07 Aug '23

Name of user not set #1002701 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37548 ) Change subject: New PCI ID for Family 15h (Models 60h-6fh) I/O Memory Management Unit ...................................................................... New PCI ID for Family 15h (Models 60h-6fh) I/O Memory Management Unit The 1022:1577 IOMMU device is found in the AMD Bettong board. Change-Id: I536ec4f24e210fa2e85e87eb4cbfde179f8c7f0f Signed-off-by: Jorge Fernandez <jorgefm(a)cirsa.com> --- M src/include/device/pci_ids.h M src/soc/amd/common/block/iommu/iommu.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/37548/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 6444bc1..1276994 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -303,6 +303,7 @@ #define PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB 0x15d0 #define PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_IOMMU 0x1419 #define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU 0x1423 +#define PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_IOMMU 0x1577 #define PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU 0x1577 #define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_IOMMU 0x1567 #define PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB_IOMMU 0x15d1 diff --git a/src/soc/amd/common/block/iommu/iommu.c b/src/soc/amd/common/block/iommu/iommu.c index 18c8e66..c8b1ff7 100644 --- a/src/soc/amd/common/block/iommu/iommu.c +++ b/src/soc/amd/common/block/iommu/iommu.c @@ -47,6 +47,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU, + PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_IOMMU, PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU, PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB_IOMMU, 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/37548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I536ec4f24e210fa2e85e87eb4cbfde179f8c7f0f Gerrit-Change-Number: 37548 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002701 Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/google/hatch/variant/kohaku: Drop early gpio MEM_STRAP conf
by Edward O'Callaghan (Code Review) 07 Aug '23

07 Aug '23

Hello Edward O'Callaghan, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37589 to review the following change. Change subject: mb/google/hatch/variant/kohaku: Drop early gpio MEM_STRAP conf ...................................................................... mb/google/hatch/variant/kohaku: Drop early gpio MEM_STRAP conf No need to configure the mem_strap in the early gpio block and again later. Fixes commit 5a0edcbde1537. BUG=b:144895517 BRANCH=hatch TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I963d0ade9941ebbb57856baecb8b126a51ed9ded Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/variants/kohaku/gpio.c 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/37589/1 diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 61d3375..4ebd258 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -119,14 +119,6 @@ PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), /* F2 : MEM_CH_SEL */ PAD_CFG_GPI(GPP_F2, NONE, PLTRST), - /* F11 : PCH_MEM_STRAP2 */ - PAD_CFG_GPI(GPP_F11, NONE, PLTRST), - /* F20 : PCH_MEM_STRAP0 */ - PAD_CFG_GPI(GPP_F20, NONE, PLTRST), - /* F21 : PCH_MEM_STRAP1 */ - PAD_CFG_GPI(GPP_F21, NONE, PLTRST), - /* F22 : PCH_MEM_STRAP3 */ - PAD_CFG_GPI(GPP_F22, NONE, PLTRST), }; const struct pad_config *variant_early_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/37589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I963d0ade9941ebbb57856baecb8b126a51ed9ded Gerrit-Change-Number: 37589 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)google.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mainboard/hatch: Move GPP_A11 config into variants from baseboard
by Edward O'Callaghan (Code Review) 07 Aug '23

07 Aug '23

Hello Edward O'Callaghan, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37590 to review the following change. Change subject: mainboard/hatch: Move GPP_A11 config into variants from baseboard ...................................................................... mainboard/hatch: Move GPP_A11 config into variants from baseboard Not all Hatch variants have a FP reader and so the baseboard should not assume one is connected. Instead the baseboard defines A11 as NC unless the variant defines it otherwise by override. Also, kindred has no FP so fix that while we are here. BUG=b:144809606 BRANCH=hatch TEST=none Change-Id: Ib4fa6ccfe746fe8e8b64b082c68d76cdc34cf8fb Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/variants/akemi/gpio.c M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/dratini/gpio.c M src/mainboard/google/hatch/variants/hatch/gpio.c M src/mainboard/google/hatch/variants/helios/gpio.c M src/mainboard/google/hatch/variants/jinlon/gpio.c M src/mainboard/google/hatch/variants/kohaku/gpio.c M src/mainboard/google/hatch/variants/stryke/gpio.c 8 files changed, 12 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/37590/1 diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c index 4be3c34..0be39b7 100644 --- a/src/mainboard/google/hatch/variants/akemi/gpio.c +++ b/src/mainboard/google/hatch/variants/akemi/gpio.c @@ -27,8 +27,6 @@ PAD_NC(GPP_A8, NONE), /* A10 : NC */ PAD_NC(GPP_A10, NONE), - /* A11 : NC */ - PAD_NC(GPP_A11, NONE), /* A12 : NC */ PAD_NC(GPP_A12, NONE), /* A18 : NC */ @@ -98,8 +96,6 @@ PAD_NC(GPP_A8, NONE), /* A10 : NC */ PAD_NC(GPP_A10, NONE), - /* A11 : NC */ - PAD_NC(GPP_A11, NONE), /* A12 : NC */ PAD_NC(GPP_A12, NONE), /* A18 : NC */ diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 029aba16..2bc843e 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -35,8 +35,8 @@ /* A9 : ESPI_CLK */ /* A10 : FPMCU_PCH_BOOT1 */ PAD_CFG_GPO(GPP_A10, 0, DEEP), - /* A11 : PCH_SPI_FPMCU_CS_L */ - PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), + /* A11 : GPP_A11 ==> NC */ + PAD_NC(GPP_A11, NONE), /* A12 : FPMCU_RST_ODL */ PAD_CFG_GPO(GPP_A12, 1, DEEP), /* A13 : SUSWARN_L */ diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c index 30d56d7..0b5d0de 100644 --- a/src/mainboard/google/hatch/variants/dratini/gpio.c +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -27,6 +27,8 @@ PAD_NC(GPP_A8, NONE), /* A10 : NC */ PAD_NC(GPP_A10, NONE), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), /* A18 : NC */ PAD_NC(GPP_A18, NONE), /* A19 : NC */ diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c index 56f587b..def6ff0 100644 --- a/src/mainboard/google/hatch/variants/hatch/gpio.c +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -19,6 +19,8 @@ #include <commonlib/helpers.h> static const struct pad_config gpio_table[] = { + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), /* C13 : EC_PCH_INT_L */ PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT)}; diff --git a/src/mainboard/google/hatch/variants/helios/gpio.c b/src/mainboard/google/hatch/variants/helios/gpio.c index 85eb3fc..89c6b41 100644 --- a/src/mainboard/google/hatch/variants/helios/gpio.c +++ b/src/mainboard/google/hatch/variants/helios/gpio.c @@ -23,6 +23,8 @@ PAD_NC(GPP_A0, NONE), /* A6 : SERIRQ ==> NC */ PAD_NC(GPP_A6, NONE), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), /* A18 : ISH_GP0 ==> NC */ PAD_NC(GPP_A18, NONE), /* A19 : ISH_GP1 ==> NC */ diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 7e475fa..bf94edb 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -27,6 +27,8 @@ PAD_NC(GPP_A8, NONE), /* A10 : NC */ PAD_NC(GPP_A10, NONE), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), /* C12 : FPMCU_PCH_BOOT1 */ PAD_CFG_GPO(GPP_C12, 0, DEEP), /* F1 : NC */ diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 4ebd258..49798c3 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -25,6 +25,8 @@ PAD_NC(GPP_A6, NONE), /* A10 : GPP_A10 ==> NC */ PAD_NC(GPP_A10, NONE), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), /* A16 : EMR_GARAGE_DET (notification) */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A16, NONE, PLTRST), /* A17 : PIRQA# ==> NC */ diff --git a/src/mainboard/google/hatch/variants/stryke/gpio.c b/src/mainboard/google/hatch/variants/stryke/gpio.c index 4d27554..814f2a6 100644 --- a/src/mainboard/google/hatch/variants/stryke/gpio.c +++ b/src/mainboard/google/hatch/variants/stryke/gpio.c @@ -27,8 +27,6 @@ PAD_NC(GPP_A8, NONE), /* A10 : NC */ PAD_NC(GPP_A10, NONE), - /* A11 : NC */ - PAD_NC(GPP_A11, NONE), /* A12 : NC */ PAD_NC(GPP_A12, NONE), /* A22 : NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4fa6ccfe746fe8e8b64b082c68d76cdc34cf8fb Gerrit-Change-Number: 37590 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)google.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/hatch/variant/hatch: Config MEM_STRAP GPIOs
by Edward O'Callaghan (Code Review) 07 Aug '23

07 Aug '23

Hello Edward O'Callaghan, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37591 to review the following change. Change subject: mb/google/hatch/variant/hatch: Config MEM_STRAP GPIOs ...................................................................... mb/google/hatch/variant/hatch: Config MEM_STRAP GPIOs Hatch always used the default MEM_STRAPs in baseboard. Adding explicit configuration for the Hatch variant in the event that MEM_STRAP is set differently in the baseboard gpio file. BUG=b:144895517 BRANCH=hatch TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I6f6cb0af2d159ba9532f413939b546526b64a935 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/variants/hatch/gpio.c 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/37591/1 diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c index 56f587b..9aac509 100644 --- a/src/mainboard/google/hatch/variants/hatch/gpio.c +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -20,7 +20,16 @@ static const struct pad_config gpio_table[] = { /* C13 : EC_PCH_INT_L */ - PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT)}; + PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT), + /* F11 : PCH_MEM_STRAP2 */ + PAD_CFG_GPI(GPP_F11, NONE, PLTRST), + /* F20 : PCH_MEM_STRAP0 */ + PAD_CFG_GPI(GPP_F20, NONE, PLTRST), + /* F21 : PCH_MEM_STRAP1 */ + PAD_CFG_GPI(GPP_F21, NONE, PLTRST), + /* F22 : PCH_MEM_STRAP3 */ + PAD_CFG_GPI(GPP_F22, NONE, PLTRST), +}; const struct pad_config *override_gpio_table(size_t *num) { -- To view, visit https://review.coreboot.org/c/coreboot/+/37591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f6cb0af2d159ba9532f413939b546526b64a935 Gerrit-Change-Number: 37591 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)google.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: drivers/intel/fsp2_0: honour FSP2_0_DISPLAY_LOGO Kconfig
by Aamir Bohra (Code Review) 07 Aug '23

07 Aug '23

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37675 ) Change subject: drivers/intel/fsp2_0: honour FSP2_0_DISPLAY_LOGO Kconfig ...................................................................... drivers/intel/fsp2_0: honour FSP2_0_DISPLAY_LOGO Kconfig The FSP logo support should only compile if board selects FSP2_0_DISPLAY_LOGO Change-Id: Id92cc733562468a42ceee720861f5a1a4bcae9c3 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/drivers/intel/fsp2_0/silicon_init.c 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/37675/1 diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index ebdbdbf..8cd63f2 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -57,13 +57,11 @@ /* Give SoC/mainboard a chance to populate entries */ platform_fsp_silicon_init_params_cb(upd); -#if (CONFIG(HAVE_FSP_GOP)) - if (CONFIG(FSP2_0_DISPLAY_LOGO)) { +#if (CONFIG(FSP2_0_DISPLAY_LOGO)) upd->FspsConfig.LogoSize = 1 * MiB; logo_entry = cbmem_entry_add(CBMEM_ID_FSP_LOGO, upd->FspsConfig.LogoSize); upd->FspsConfig.LogoPtr = (UINT32)cbmem_entry_start(logo_entry); load_logo(upd); - } #endif /* Call SiliconInit */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id92cc733562468a42ceee720861f5a1a4bcae9c3 Gerrit-Change-Number: 37675 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: mainboard/intel/common: Add config for intel common mainboard support
by Aamir Bohra (Code Review) 07 Aug '23

07 Aug '23

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37705 ) Change subject: mainboard/intel/common: Add config for intel common mainboard support ...................................................................... mainboard/intel/common: Add config for intel common mainboard support Add config to support intel mainboard common code. The intend is to create common placeholder for APIs common across the mainboard. Change-Id: Idc6f9bd298520f5e929534c64f1b038a4c9684a9 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- A src/mainboard/intel/common/Kconfig 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/37705/1 diff --git a/src/mainboard/intel/common/Kconfig b/src/mainboard/intel/common/Kconfig new file mode 100644 index 0000000..e96d943 --- /dev/null +++ b/src/mainboard/intel/common/Kconfig @@ -0,0 +1,5 @@ +config MAINBOARD_INTEL_COMMON + bool + help + common code for Intel Mainboards + -- To view, visit https://review.coreboot.org/c/coreboot/+/37705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc6f9bd298520f5e929534c64f1b038a4c9684a9 Gerrit-Change-Number: 37705 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

7 16

Change in coreboot[master]: mainboard/intel/common: Add some common board and memory APIs
by Aamir Bohra (Code Review) 07 Aug '23

07 Aug '23

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37707 ) Change subject: mainboard/intel/common: Add some common board and memory APIs ...................................................................... mainboard/intel/common: Add some common board and memory APIs Add support for below APIs in mainboard intel/common: 1. get_board_id: Returns board ID from EC. 2. get_spd_index: Returns SPD index from board ID. Change-Id: I40c9454b583d6bc0e3034f3400beb822124ba8f4 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- A src/mainboard/intel/common/Makefile.inc A src/mainboard/intel/common/board/Makefile.inc A src/mainboard/intel/common/board/board_id.c A src/mainboard/intel/common/include/intel_mb/board_id.h A src/mainboard/intel/common/include/intel_mb/spd.h A src/mainboard/intel/common/memory/Makefile.inc A src/mainboard/intel/common/memory/spd.c 7 files changed, 143 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/37707/1 diff --git a/src/mainboard/intel/common/Makefile.inc b/src/mainboard/intel/common/Makefile.inc new file mode 100644 index 0000000..54bba3f --- /dev/null +++ b/src/mainboard/intel/common/Makefile.inc @@ -0,0 +1,8 @@ +ifeq ($(CONFIG_MAINBOARD_INTEL_COMMON),y) + +subdirs-y += board/ +subdirs-y += memory/ + +CPPFLAGS_common += -I$(src)/mainboard/intel/common/include/ + +endif diff --git a/src/mainboard/intel/common/board/Makefile.inc b/src/mainboard/intel/common/board/Makefile.inc new file mode 100644 index 0000000..4781dfb --- /dev/null +++ b/src/mainboard/intel/common/board/Makefile.inc @@ -0,0 +1,3 @@ +romstage-y += board_id.c +ramstage-y += board_id.c + diff --git a/src/mainboard/intel/common/board/board_id.c b/src/mainboard/intel/common/board/board_id.c new file mode 100644 index 0000000..19897c2 --- /dev/null +++ b/src/mainboard/intel/common/board/board_id.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <ec/acpi/ec.h> +#include <ec/google/chromeec/ec.h> +#include <intel_mb/board_id.h> +#include <stdint.h> + +static int get_board_id_via_ext_ec(void) +{ + uint32_t id = BOARD_ID_INIT; + + if (google_chromeec_get_board_version(&id)) + id = BOARD_ID_UNKNOWN; + + return id; +} + +/* Get Board ID via EC I/O port write/read */ +int get_board_id(void) +{ + MAYBE_STATIC_NONZERO int id = -1; + + if (id < 0) { + if (CONFIG(EC_GOOGLE_CHROMEEC)) + id = get_board_id_via_ext_ec(); + else{ + uint8_t buffer[2]; + uint8_t index; + if (send_ec_command(EC_FAB_ID_CMD) == 0) { + for (index = 0; index < sizeof(buffer); index++) + buffer[index] = recv_ec_data(); + id = (buffer[0] << 8) | buffer[1]; + } + } + } + + return id; +} diff --git a/src/mainboard/intel/common/include/intel_mb/board_id.h b/src/mainboard/intel/common/include/intel_mb/board_id.h new file mode 100644 index 0000000..9aac527 --- /dev/null +++ b/src/mainboard/intel/common/include/intel_mb/board_id.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MAINBOARD_COMMON_BOARD_ID_H_ +#define _MAINBOARD_COMMON_BOARD_ID_H_ + +#include <stdint.h> + +/* Board/FAB ID Command */ +#define EC_FAB_ID_CMD 0x0D + +/* + * Returns board information (board id[15:8] and + * Fab info[7:0]) on success and < 0 on error + */ +int get_board_id(void); + +#endif /* _MAINBOARD_COMMON_BOARD_ID_H_ */ diff --git a/src/mainboard/intel/common/include/intel_mb/spd.h b/src/mainboard/intel/common/include/intel_mb/spd.h new file mode 100644 index 0000000..3f834b8 --- /dev/null +++ b/src/mainboard/intel/common/include/intel_mb/spd.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MAINBOARD_COMMON_SPD_H_ +#define _MAINBOARD_COMMON_SPD_H_ + +#include <stdint.h> + +/* Returns SPD index from board ID */ +uint8_t get_spd_index(void); + +#endif /* _MAINBOARD_COMMON_SPD_H_ */ diff --git a/src/mainboard/intel/common/memory/Makefile.inc b/src/mainboard/intel/common/memory/Makefile.inc new file mode 100644 index 0000000..c0e5f53 --- /dev/null +++ b/src/mainboard/intel/common/memory/Makefile.inc @@ -0,0 +1,2 @@ +romstage-y += spd.c + diff --git a/src/mainboard/intel/common/memory/spd.c b/src/mainboard/intel/common/memory/spd.c new file mode 100644 index 0000000..5da5bf4 --- /dev/null +++ b/src/mainboard/intel/common/memory/spd.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intel_mb/board_id.h> +#include <intel_mb/spd.h> +#include <stdint.h> + +uint8_t get_spd_index(void) +{ + return get_board_id() & 0x7; + +} -- To view, visit https://review.coreboot.org/c/coreboot/+/37707 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40c9454b583d6bc0e3034f3400beb822124ba8f4 Gerrit-Change-Number: 37707 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mb/intel/icelake_rvp: Use board ID and spd index from mainboard common
by Aamir Bohra (Code Review) 07 Aug '23

07 Aug '23

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37708 ) Change subject: mb/intel/icelake_rvp: Use board ID and spd index from mainboard common ...................................................................... mb/intel/icelake_rvp: Use board ID and spd index from mainboard common Change-Id: I5d1a8a6da855b7ec2906a135a60ca2902307fd4c Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/intel/icelake_rvp/Makefile.inc D src/mainboard/intel/icelake_rvp/board_id.c D src/mainboard/intel/icelake_rvp/board_id.h M src/mainboard/intel/icelake_rvp/romstage_fsp_params.c M src/mainboard/intel/icelake_rvp/spd/spd_util.c M src/soc/intel/icelake/Kconfig 6 files changed, 4 insertions(+), 91 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/37708/1 diff --git a/src/mainboard/intel/icelake_rvp/Makefile.inc b/src/mainboard/intel/icelake_rvp/Makefile.inc index 74d02cb..c9c817f 100644 --- a/src/mainboard/intel/icelake_rvp/Makefile.inc +++ b/src/mainboard/intel/icelake_rvp/Makefile.inc @@ -22,12 +22,10 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += romstage_fsp_params.c -romstage-y += board_id.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c ramstage-y += mainboard.c -ramstage-y += board_id.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/icelake_rvp/board_id.c b/src/mainboard/intel/icelake_rvp/board_id.c deleted file mode 100644 index c0def22..0000000 --- a/src/mainboard/intel/icelake_rvp/board_id.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include "board_id.h" -#include <boardid.h> -#include <ec/acpi/ec.h> -#include <stdint.h> -#include <ec/google/chromeec/ec.h> - -static int get_board_id_via_ext_ec(void) -{ - uint32_t id = BOARD_ID_INIT; - - if (google_chromeec_get_board_version(&id)) - id = BOARD_ID_UNKNOWN; - - return id; -} - -/* Get Board ID via EC I/O port write/read */ -int get_board_id(void) -{ - MAYBE_STATIC_NONZERO int id = -1; - - if (id < 0) { - if (CONFIG(EC_GOOGLE_CHROMEEC)) - id = get_board_id_via_ext_ec(); - else{ - uint8_t buffer[2]; - uint8_t index; - if (send_ec_command(EC_FAB_ID_CMD) == 0) { - for (index = 0; index < sizeof(buffer); index++) - buffer[index] = recv_ec_data(); - id = (buffer[0] << 8) | buffer[1]; - } - } - } - - return id; -} diff --git a/src/mainboard/intel/icelake_rvp/board_id.h b/src/mainboard/intel/icelake_rvp/board_id.h deleted file mode 100644 index 3ccfe37..0000000 --- a/src/mainboard/intel/icelake_rvp/board_id.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _MAINBOARD_BOARD_ID_H_ -#define _MAINBOARD_BOARD_ID_H_ - -/* Board/FAB ID Command */ -#define EC_FAB_ID_CMD 0x0D - -/* - * Returns board information (board id[15:8] and - * Fab info[7:0]) on success and < 0 on error - */ -int get_board_id(void); - -#endif /* _MAINBOARD_BOARD_ID_H_ */ diff --git a/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c b/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c index 5a4d681..5db6f18 100644 --- a/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c +++ b/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c @@ -15,15 +15,15 @@ #include <console/console.h> #include <fsp/api.h> +#include <intel_mb/spd.h> #include <soc/romstage.h> #include <spd_bin.h> -#include "board_id.h" #include "spd/spd.h" void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; - u8 spd_index = (get_board_id() & 0x1F) & 0x7; + u8 spd_index = get_spd_index(); printk(BIOS_DEBUG, "spd index is 0x%x\n", spd_index); if (spd_index > 0 && spd_index != 2) { diff --git a/src/mainboard/intel/icelake_rvp/spd/spd_util.c b/src/mainboard/intel/icelake_rvp/spd/spd_util.c index d7babbd..cae3974 100644 --- a/src/mainboard/intel/icelake_rvp/spd/spd_util.c +++ b/src/mainboard/intel/icelake_rvp/spd/spd_util.c @@ -15,10 +15,10 @@ #include <arch/cpu.h> #include <intelblocks/mp_init.h> +#include <intel_mb/spd.h> #include <stdint.h> #include <string.h> -#include "../board_id.h" #include "spd.h" enum icl_dimm_type { @@ -47,13 +47,6 @@ memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); } -static uint8_t get_spd_index(void) -{ - uint8_t spd_index = (get_board_id() & 0x1F) & 0x7; - - return spd_index; -} - void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr) { /* DQS CPU<>DRAM map Ch0 */ diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 7f1cd89..09b22d5 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -26,6 +26,7 @@ select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC + select MAINBOARD_INTEL_COMMON select MRC_SETTINGS_PROTECT select PARALLEL_MP select PARALLEL_MP_AP_WORK -- To view, visit https://review.coreboot.org/c/coreboot/+/37708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d1a8a6da855b7ec2906a135a60ca2902307fd4c Gerrit-Change-Number: 37708 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: Revert "Revert "mb/google/hatch: Enable PchPmSlpS0Vm075VSupport for h...
by Kane Chen (Code Review) 07 Aug '23

07 Aug '23

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37866 ) Change subject: Revert "Revert "mb/google/hatch: Enable PchPmSlpS0Vm075VSupport for hatch"" ...................................................................... Revert "Revert "mb/google/hatch: Enable PchPmSlpS0Vm075VSupport for hatch"" This reverts commit b1ea707bdaf064ae1d2427e5e3c20d2ab66bf93d. Change-Id: Id4cc0e1c176d39d7c85a5298093852df5fc229fc --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/37866/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 7382209..a2831e1 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -58,6 +58,8 @@ register "PmTimerDisabled" = "1" + register "PchPmSlpS0Vm075VSupport" = "1" + # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | -- To view, visit https://review.coreboot.org/c/coreboot/+/37866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4cc0e1c176d39d7c85a5298093852df5fc229fc Gerrit-Change-Number: 37866 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: [DO-NOT-SUBMIT]: treeya: override edid for old AUO panel
by Peichao Li (Code Review) 07 Aug '23

07 Aug '23

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38118 ) Change subject: [DO-NOT-SUBMIT]: treeya: override edid for old AUO panel ...................................................................... [DO-NOT-SUBMIT]: treeya: override edid for old AUO panel Test only BUG=NONE TEST=NONE Signed-off-by: Peichao.Wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: I29a699ebd6c1a5e5a8ff1d2aa0882330ac51972a --- M src/mainboard/google/kahlee/OemCustomize.c M src/mainboard/google/kahlee/mainboard.c 2 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/38118/1 diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index 8e5d8eb..39bd4b1 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -102,4 +102,6 @@ (params->LvdsPowerOnSeqBlonToVaryBl)*4); } params->EDPv1_4VSMode = EDP_VS_HIGH_VDIFF_MODE; + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_TREEYA)) + params->DisplayMiscControl.Value |= 0x1; // Enable Int15 callback in VBIOS } diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 0173064..4fb8083 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -32,6 +32,9 @@ #include <variant/ec.h> #include <variant/thermal.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <arch/interrupt.h> +#include <x86emu/x86emu.h> +#include <string.h> /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -83,6 +86,19 @@ [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; +#if IS_ENABLED(CONFIG_BOARD_GOOGLE_TREEYA) +const u8 target_edid_auo_b116xan06p1[128] = { + 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x06, 0xAF, 0x5C, 0x61, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x1B, 0x01, 0x04, 0x95, 0x1A, 0x0E, 0x78, 0x02, 0x99, 0x85, 0x95, 0x55, 0x56, 0x92, 0x28, + 0x22, 0x50, 0x54, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x66, 0x1C, 0x56, 0xA0, 0x50, 0x00, 0x19, 0x30, 0x30, 0x20, + 0x46, 0x00, 0x00, 0x90, 0x10, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x41, + 0x55, 0x4F, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xFE, + 0x00, 0x42, 0x31, 0x31, 0x36, 0x58, 0x41, 0x4E, 0x30, 0x36, 0x2E, 0x31, 0x20, 0x0A, 0x00, 0x06 +}; +#endif + /* * This table defines the index into the picr/intr_data tables for each * device. Any enabled device and slot that uses hardware interrupts should @@ -114,6 +130,31 @@ picr_data_ptr = mainboard_picr_data; } +#if IS_ENABLED(CONFIG_BOARD_GOOGLE_TREEYA) +static int int15_handler(void) +{ + int res = 0; + u8 *edidbuffer = (uint8_t*)(uint)((X86_ES <<4) + X86_DI); + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); + + switch(X86_EAX & 0xffff) { + case 0x4E08: + printk(BIOS_DEBUG, "VBIOS called\n"); + if ((X86_EBX & 0x00ff) == 0x001b) { + printk(BIOS_DEBUG, "pass edid for override\n"); + memcpy(edidbuffer, target_edid_auo_b116xan06p1 , sizeof(target_edid_auo_b116xan06p1)); + X86_CX = sizeof(target_edid_auo_b116xan06p1); + X86_EAX = 0x4E00; // Function supported and successful. + res = 1; + } + break; + + } + return res; +} +#endif + static void mainboard_init(void *chip_info) { const struct sci_source *gpes; @@ -129,6 +170,11 @@ gpios = variant_gpio_table(&num_gpios); program_gpios(gpios, num_gpios); + if( boardid == 4) { +#if IS_ENABLED(CONFIG_BOARD_GOOGLE_TREEYA) + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif + } /* * Some platforms use SCI not generated by a GPIO pin (event above 23). * For these boards, gpe_configure_sci() is still needed, but all GPIO -- To view, visit https://review.coreboot.org/c/coreboot/+/38118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29a699ebd6c1a5e5a8ff1d2aa0882330ac51972a Gerrit-Change-Number: 38118 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

4 15

← Newer
1
...
22
23
24
25
26
27
28
...
68
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2022