coreboot-gerrit July 2022

coreboot-gerrit@coreboot.org

673 discussions

Change in coreboot[master]: payloads/LinuxBoot: Fix initramfs Makefile rule
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38530 ) Change subject: payloads/LinuxBoot: Fix initramfs Makefile rule ...................................................................... payloads/LinuxBoot: Fix initramfs Makefile rule Pass $(top) to LinuxBoot Makefile and build u-root before trying to include it into uImage on aarch64. Change-Id: I91d037a24b2893455761912fc966aa02272ad070 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M payloads/external/LinuxBoot/Makefile M payloads/external/Makefile.inc 2 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/38530/1 diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile index 5840e8e..67bb730 100644 --- a/payloads/external/LinuxBoot/Makefile +++ b/payloads/external/LinuxBoot/Makefile @@ -62,7 +62,10 @@ fi endif -linuxboot: kernel initramfs_compressed +linuxboot: + # for AARCH64 uroot needs to be build first + $(MAKE) initramfs_compressed + $(MAKE) kernel clean: if [ -d "$(kernel_dir)" ]; then rm -rf $(kernel_dir); fi diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index b8af8c9..4388a9e 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -295,7 +295,8 @@ CONFIG_LINUXBOOT_UROOT_SHELL=$(CONFIG_LINUXBOOT_UROOT_SHELL) \ CONFIG_LINUXBOOT_UROOT_COMMANDS=$(CONFIG_LINUXBOOT_UROOT_COMMANDS) \ CONFIG_LINUXBOOT_UROOT_FILES=$(CONFIG_LINUXBOOT_UROOT_FILES) \ - CONFIG_LINUXBOOT_DTB_FILE=$(CONFIG_LINUXBOOT_DTB_FILE) + CONFIG_LINUXBOOT_DTB_FILE=$(CONFIG_LINUXBOOT_DTB_FILE) \ + top=$(top) payloads/external/LinuxBoot/linuxboot/bzImage: linuxboot payloads/external/LinuxBoot/linuxboot/uImage: linuxboot -- To view, visit https://review.coreboot.org/c/coreboot/+/38530 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91d037a24b2893455761912fc966aa02272ad070 Gerrit-Change-Number: 38530 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: payloads/external/linux: Attempt to autodetect correct toolchain
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38531 ) Change subject: payloads/external/linux: Attempt to autodetect correct toolchain ...................................................................... payloads/external/linux: Attempt to autodetect correct toolchain Change-Id: Ide7cd9ff838266823057d604addc8970939ccb86 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M payloads/external/LinuxBoot/targets/linux.mk 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/38531/1 diff --git a/payloads/external/LinuxBoot/targets/linux.mk b/payloads/external/LinuxBoot/targets/linux.mk index 8be0926..aa3f168 100644 --- a/payloads/external/LinuxBoot/targets/linux.mk +++ b/payloads/external/LinuxBoot/targets/linux.mk @@ -27,6 +27,18 @@ project_dir=linuxboot tarball_dir:=$(project_dir)/tarball decompress_flag=.done +ifeq ($(LINUXBOOT_CROSS_COMPILE),) +$(info env LINUXBOOT_CROSS_COMPILE not set, auto-detecting host toolchain...) +# Don't use gnu-gcc as ccache falsely provides this single binary +ifeq ($(CONFIG_LINUXBOOT_X86_64),y) +LINUXBOOT_CROSS_COMPILE=$(shell which x86_64-linux-gnu-ld | sed -e "s/linux-gnu-ld/linux-gnu-/g") +else ifeq ($(CONFIG_LINUXBOOT_X86),y) +LINUXBOOT_CROSS_COMPILE=$(shell which i386-linux-gnu-ld | sed -e "s/linux-gnu-ld/linux-gnu-/g") +else ifeq ($(CONFIG_LINUXBOOT_ARM64),y) +LINUXBOOT_CROSS_COMPILE=$(shell which aarch64-linux-gnu-ld | sed -e "s/linux-gnu-ld/linux-gnu-/g") +endif +$(info Using '$(LINUXBOOT_CROSS_COMPILE)' as toolchain) +endif OBJCOPY:=$(LINUXBOOT_CROSS_COMPILE)objcopy KERNEL_MAKE_FLAGS = \ -- To view, visit https://review.coreboot.org/c/coreboot/+/38531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide7cd9ff838266823057d604addc8970939ccb86 Gerrit-Change-Number: 38531 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: sc7180: QSIP SPI NOR addressing mode
by mturney mturney (Code Review) 07 Aug '23

07 Aug '23

Hello Sajida Bhanu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38542 to review the following change. Change subject: sc7180: QSIP SPI NOR addressing mode ...................................................................... sc7180: QSIP SPI NOR addressing mode Putting SPI NOR 3 byte addressing mode as it is not supporting 4 byte addressing mode. Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Signed-off-by: Veerabhadrarao Badiganti <vbadigan(a)codeaurora.org> Signed-off-by: Shaik Sajida Bhanu <sbhanu(a)codeaurora.org> --- M src/drivers/spi/spi_flash.c M src/drivers/spi/winbond.c 2 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/38542/1 diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 90dd587..85cc160 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -459,6 +459,7 @@ { struct spi_slave spi; int ret = -1; + u8 reg8; if (spi_setup_slave(bus, cs, &spi)) { printk(BIOS_WARNING, "SF: Failed to set up slave\n"); @@ -491,6 +492,21 @@ " CONFIG_ROM_SIZE 0x%x!!\n", flash->size, CONFIG_ROM_SIZE); } + + /*Check addressing mode*/ + spi_flash_cmd(&flash->spi, 0x15, &reg8, sizeof(reg8)); + + if (reg8 & 0x1 ) { + printk(BIOS_WARNING, "4 byte adressing mode set:%02x\n. Falling back to 3 byte addressing mode\n", reg8); + } + + spi_flash_cmd(&flash->spi, 0xe9, NULL, 0); + spi_flash_cmd(&flash->spi, 0x15, &reg8, sizeof(reg8)); + if (reg8 & 0x1 ) { + printk(BIOS_WARNING, "4 byte adressing mode set:%02x\n. Exiting 4 byte mode not working . Looping here\n ", reg8); + while(1); + } + return 0; } diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index e85f59d..c4dc3d4 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -174,6 +174,14 @@ .bp_bits = 3, }, { + .id = 0x6019, + .name = "W25Q64DW", + .nr_sectors_shift = 11, + .fast_read_dual_output_support = 1, + .protection_granularity_shift = 17, + .bp_bits = 3, + }, + { .id = 0x4018, .name = "W25Q128_V", .nr_sectors_shift = 12, -- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-MessageType: newchange

8 29

Change in coreboot[master]: drivers/intel/gma/edid: Use unsigned type for count variable
by Paul Menzel (Code Review) 07 Aug '23

07 Aug '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38645 ) Change subject: drivers/intel/gma/edid: Use unsigned type for count variable ...................................................................... drivers/intel/gma/edid: Use unsigned type for count variable No real difference in the assembly though. @@ -799,8 +799,8 @@ .string "i" .byte 0x1 .byte 0x44 - .byte 0x6 - .long 0x4d + .byte 0xf + .long 0x60 .long .LLST25 .long .LVUS25 .uleb128 0xe Change-Id: I340a2752f955e5e4d2198a81408b3663b1488b80 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/drivers/intel/gma/edid.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/38645/1 diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 4d4aec3..7e6c840 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -65,7 +65,7 @@ void intel_gmbus_read_edid(u8 *mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size) { - int i; + unsigned int i; slave &= 0x7f; edid_size &= 0x1fc; -- To view, visit https://review.coreboot.org/c/coreboot/+/38645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I340a2752f955e5e4d2198a81408b3663b1488b80 Gerrit-Change-Number: 38645 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: drivers/intel/gma/edid: Measure execution time of EDID read function
by Paul Menzel (Code Review) 07 Aug '23

07 Aug '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38646 ) Change subject: drivers/intel/gma/edid: Measure execution time of EDID read function ...................................................................... drivers/intel/gma/edid: Measure execution time of EDID read function Getting more data, it might turn out, that storing the EDID data in CBFS might save some time. Change-Id: I4c3672ef85bfc2d206620e689626573e04a0f63b Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/drivers/intel/gma/edid.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/38646/1 diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 7e6c840..6885f98 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -15,6 +15,7 @@ #include <device/mmio.h> #include <console/console.h> #include <delay.h> +#include <timer.h> #include "i915_reg.h" #include "edid.h" @@ -66,10 +67,12 @@ void intel_gmbus_read_edid(u8 *mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size) { unsigned int i; + struct stopwatch sw; slave &= 0x7f; edid_size &= 0x1fc; + stopwatch_init(&sw); wait_rdy(mmio); /* 100 KHz, hold 0ns, */ write32(GMBUS0_ADDR, bus); @@ -107,4 +110,6 @@ if ((i & 0xf) == 0xf) printk (BIOS_SPEW, "\n"); } + printk(BIOS_DEBUG, "%s finished in %lu msecs\n", __func__, + stopwatch_duration_msecs(&sw)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/38646 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c3672ef85bfc2d206620e689626573e04a0f63b Gerrit-Change-Number: 38646 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: drivers/intel/gma/edid: Use byte swap function
by Paul Menzel (Code Review) 07 Aug '23

07 Aug '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38647 ) Change subject: drivers/intel/gma/edid: Use byte swap function ...................................................................... drivers/intel/gma/edid: Use byte swap function Instead of open coding the byte swapping (endianess), use the built-in. The compiler can use the instruction `bswap` now. As EDID data is not big, the difference in execution time won’t be measurable. With gcc (Debian 9.2.1-25) 9.2.1 20200123: .LBE128: .LBE127: - .loc 1 94 3 is_stmt 1 discriminator 3 view .LVU157 - addl $4, %ebp - .loc 1 94 15 is_stmt 0 discriminator 3 view .LVU158 - movb %al, -4(%ebp) - .loc 1 95 3 is_stmt 1 discriminator 3 view .LVU159 - .loc 1 96 28 is_stmt 0 discriminator 3 view .LVU160 - movl %eax, %edx - .loc 1 95 19 discriminator 3 view .LVU161 - movb %ah, -3(%ebp) - .loc 1 96 3 is_stmt 1 discriminator 3 view .LVU162 - .loc 1 96 28 is_stmt 0 discriminator 3 view .LVU163 - shrl $16, %edx - .loc 1 96 19 discriminator 3 view .LVU164 - movb %dl, -2(%ebp) - .loc 1 97 3 is_stmt 1 discriminator 3 view .LVU165 - .loc 1 97 35 is_stmt 0 discriminator 3 view .LVU166 - shrl $24, %eax + .loc 1 96 3 is_stmt 1 discriminator 3 view .LVU159 + .loc 1 96 15 is_stmt 0 discriminator 3 view .LVU160 + movl 76(%esp), %edx + .loc 1 96 17 discriminator 3 view .LVU161 + bswap %eax Change-Id: I818318361a83b2b3f0c6d8637dd3b6917590c836 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/drivers/intel/gma/edid.c 1 file changed, 3 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38647/1 diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 6885f98..5f1cfe8 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -15,6 +15,7 @@ #include <device/mmio.h> #include <console/console.h> #include <delay.h> +#include <swab.h> #include <timer.h> #include "i915_reg.h" @@ -91,10 +92,8 @@ u32 reg32; wait_rdy(mmio); reg32 = read32(GMBUS3_ADDR); - edid[4 * i] = reg32 & 0xff; - edid[4 * i + 1] = (reg32 >> 8) & 0xff; - edid[4 * i + 2] = (reg32 >> 16) & 0xff; - edid[4 * i + 3] = (reg32 >> 24) & 0xff; + /* Writes 4 * i to (4 * i) + 3 */ + edid[4 * i] = swab32(reg32); } wait_rdy(mmio); write32(GMBUS1_ADDR, GMBUS_SW_RDY -- To view, visit https://review.coreboot.org/c/coreboot/+/38647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I818318361a83b2b3f0c6d8637dd3b6917590c836 Gerrit-Change-Number: 38647 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: Documentation: Add MacBook internal flashing tutorial
by Evgeny Zinoviev (Code Review) 07 Aug '23

07 Aug '23

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38770 ) Change subject: Documentation: Add MacBook internal flashing tutorial ...................................................................... Documentation: Add MacBook internal flashing tutorial Change-Id: I2650d5d60db7a29a1567e44e89b785def9342df2 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M Documentation/flash_tutorial/int_flashrom.md A Documentation/flash_tutorial/int_macbook.md 2 files changed, 294 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/38770/1 diff --git a/Documentation/flash_tutorial/int_flashrom.md b/Documentation/flash_tutorial/int_flashrom.md index 28b534b..0ca59af 100644 --- a/Documentation/flash_tutorial/int_flashrom.md +++ b/Documentation/flash_tutorial/int_flashrom.md @@ -16,4 +16,9 @@ flashrom -p internal -w coreboot.rom ``` +## Vendor-specific + +- [Lenovo ThinkPad xx30 series](../lenovo/ivb_internal_flashing) +- [Apple MacBook](int_macbook.md) - 2011-2012 models + [flashrom's wiki]: https://www.flashrom.org/Flashrom diff --git a/Documentation/flash_tutorial/int_macbook.md b/Documentation/flash_tutorial/int_macbook.md new file mode 100644 index 0000000..b0638ca --- /dev/null +++ b/Documentation/flash_tutorial/int_macbook.md @@ -0,0 +1,289 @@ +# Apple MacBook internal flashing + +This page describes a method of flashing coreboot on 2011-2012 models of +Apple MacBooks. Whether it can be used on other generations of MacBooks +is unknown. + +This is a very delicate prodecure. Be very careful, check everything +twice, especially the numbers. A single mistake may brick your machine +and you'll have to flash the backup externally. Given this fact, you +should have an external means of flashing, just in case. + +It was tested and confirmed to work on following models: +- MacBook Air 5,2 +- MacBook Pro 8,1 +- MacBook Pro 10,1 + +MacBook Air 4,2 should work too, but it's not tested. + +## Introduction + +Apple's "Think Different" slogan fits perfectly with their approach to +firmware security. Besides the fact that they do not use SMM_BWP to +protect SPI flash from being writable from userspace, they do not even +protect Flash Descriptor (`fd`) and Management Engine (`me`) regions. + +The Intel Flash Descriptor is a data structure of fixed size (4KB) +stored on the flash chip (resides in `0x0000-0x0fff`), that contains +various information such as space allocated for each region on the +flash, access permissions, some chipset configuration and more. In +particular, it contains access permissions for `fd` and `me` regions. +Normally they should be read-only in production, but Apple, for whatever +reasons, keeps them read-write. + +Instead, they decided to use SPI Protected Range Registers (PR0-PR4) to +set protection over `fd`, but here they failed again. Due to a bug in +their firmware, `0x0000-0x0fff` is not write-protected after cold boot +and becomes read-only only after resuming from S3. You can dump PRx +protections by running `flashrom -p internal`. + +This is what you should see after a cold boot (if so, then you can use +this guide): +``` +PR0: Warning: 0x00190000-0x0066ffff is read-only. +PR1: Warning: 0x00692000-0x01ffffff is read-only. +``` + +And this is after resuming from S3: +``` +PR0: Warning: 0x00000000-0x00000fff is read-only. +PR1: Warning: 0x00190000-0x0066ffff is read-only. +PR2: Warning: 0x00692000-0x01ffffff is read-only. +``` + +So, after cold boot flash descriptor is not protected neither by PRx +registers nor by access permissions bits on the flash descriptor itself. +Under certain circumstances, **writable flash descriptor allows to flash +whole SPI flash** by using a couple of tricks. + +The idea is that we can shrink ME firmware with me_cleaner, flash small +coreboot image on the freed space and move reset vector there. Then +power off, boot coreboot and flash full image, as there will be no more +PRx set. + +## Stage 1. Flashing temporary BIOS + +#### Preparations + +Dump your ROM: +``` +flashrom -p internal -r orig.bin +``` + +Please save this backup to an external drive. You may need it in case of +failure. + +Extract flash layout: +``` +ifdtool -f orig_layout.txt orig.bin +cat orig_layout.txt +``` + +You should see something like or exactly this: +``` +00000000:00000fff fd +00190000:007fffff bios +00001000:0018ffff me +``` +If you compare these regions with what's protected by PR0 and PR1, +you'll notice that `fd` and `me` regions are fully writable and only +`bios` is protected. Writable ME region gives us around 1.5 MB which we +can use for our goals. + +Extract flash regions from the dump into separate files: +``` +ifdtool -x orig.bin +``` + +You can see that 3 new files were created: +``` +ls flash* +flashregion_0_flashdescriptor.bin flashregion_1_bios.bin flashregion_2_intel_me.bin +``` + +The ME firmware is ~1.5 MB in size, but we can truncate it with +me_cleaner: +``` +me_cleaner.py -t -r -O flashregion_2_intel_me_truncated.bin flashregion_2_intel_me.bin +``` + +The truncated firmware should be around 90K: +``` +stat --printf=%s flashregion_2_intel_me_truncated.bin +94208 +``` + +Rename the original `flashregion_2_intel_me.bin` file to not mix them up +in future: +``` +mv flashregion_2_intel_me.bin flashregion_2_intel_me_orig.bin +``` + +Now we need to write a new flash layout. 128K is more than enough for +the "neutered" ME firmware. We can use the rest for new `bios` region, +but 892K is enough: + +``` +00000000:00000fff fd +00001000:00020fff me +00021000:000fffff bios +00100000:007fffff pd +``` + +Note that we must allocate the remaining `0x100000-0x7fffff` for +something to be able to address and flash it in future. Let's just mark +it as `pd` (which stands for "Platform Data") for now. + +Save the new layout to a file `new_layout.txt` and update regions in the +dump: +``` +ifdtool -n new_layout.txt orig.bin +``` + +The updated image will be saved to `orig.bin.new`. Move it to a +separate directory for convenience: +``` +mkdir patched && cd $_ +mv ../orig.bin.new . +``` + +Extract flash regions again, now from the updated image: +``` +fdtool -x orig.bin.new +``` + +By now we have new `flashregion_0_flashdescriptor.bin` file with our +custom layout. Let's also move the patched ME here: +``` +rm flashregion_2_intel_me.bin +mv ../flashregion_2_intel_me_truncated.bin . +``` + +So far, so good. At this point our preparations for the first stage are +finished and we're ready to configure coreboot. + +#### Configuring and flashing coreboot + +Run `make menuconfig` and configure as shown below. Note that you need +to change **ROM chip size**, **CBFS size** and specify paths to modified +`flashregion_0_flashdescriptor.bin` and +`flashregion_2_intel_me_truncated.bin`. + +``` +Mainboard ---> + Mainboard vendor (Apple) + Mainboard model () # Set according to your model + ROM chip size (1024 KB (1 MB)) + (0xd0000) Size of CBFS filesystem in ROM + +Chipset ---> + [*] Add Intel descriptor.bin file + (/path/to/patched/flashregion_0_flashdescriptor.bin) Path and filename of the descriptor.bin file + [*] Add Intel ME/TXE firmware + (/path/to/patched/flashregion_2_intel_me_truncated.bin) Path to management engine firmware + [ ] Verify the integrity of the supplied ME/TXE firmware + [ ] Strip down the Intel ME/TXE firmware + Protect flash regions (Unlock flash regions) +``` + +Then you need to decide which payload to use. For now, it's recommended +to use GRUB2. Be sure to include a good config for it that can load variety +of setups. SeaBIOS works too, but currently needs a patch for internal +MacBook's keyboard to work. + +When configuration is done, run `make` to build coreboot. In the end you +should have 1024 KB coreboot ROM at `build/coreboot.rom`. Flashrom won't +accept it, because it's size must match the chip, so we have to make it +8 MB. Just add 7 MB of zeroes: +``` +dd if=/dev/zero of=7M.bin bs=1024 count=7168 +``` +``` +cat build/coreboot.rom 7M.bin > coreboot8.rom +``` + +Now cross your fingers and flash the new **`fd`** (`0x0000-0x0fff`), +**`me`** (`0x1000-0x20fff`) and **`bios`** (`0x21000-0xfffff`) regions +using the layout file: +``` +flashrom -p internal -w coreboot8.rom -l new_layout.txt -i fd -N +flashrom -p internal -w coreboot8.rom -l new_layout.txt -i me -N +flashrom -p internal -w coreboot8.rom -l new_layout.txt -i bios -N +``` + +The first stage is completed. Power off the machine now. Reboot won't +work: new flash descriptor becomes active on cold boot. + +On the next boot, if you're lucky and didn't do any mistake, coreboot +will be loaded from the new `bios` region, and Apple's EFI, that still +resides in `0x190000-0x7fffff`, will be ignored. + +## Stage 2. Flashing full ROM + +Now we can flash whole 8 MB chip, because no PRx are set anymore. Let's +relayout the chip again. + +If you want to continue using truncated ME: +``` +00000000:00000fff fd +00001000:00020fff me +00021000:007fffff bios +``` + +If you want to flash full ME firmware back: +``` +00000000:00000fff fd +00001000:0018ffff me +00190000:007fffff bios +``` + +Save it to `final_layout.txt` and create new flash descriptor again. +``` +mkdir patched2 && cd $_ +cp ../orig.bin . +ifdtool -n final_layout.txt orig.bin +ifdtool -x orig.bin.new +``` + +Go back to coreboot directory and run `make menuconfing`. + +In the **Mainboard** section change **ROM chip size** back to 8 MB and +set **Size of CBFS** according to your needs: now you have plenty of +space. `0x500000` or so should work just fine. + +In the **Chipset** section, update paths to the flash descriptor and ME +firmware files. If you decided to stick to truncated ME, use +`flashregion_2_intel_me_truncated.bin`, otherwise use +`flashregion_2_intel_me_orig.bin`. + +``` +Mainboard ---> + ROM chip size (8192 KB (8 MB)) + (0x500000) Size of CBFS filesystem in ROM + +Chipset ---> + [*] Add Intel descriptor.bin file + + # Use the latest flashdescriptor from the patched2 directory + (/path/to/patched2/flashregion_0_flashdescriptor.bin) Path and filename of the descriptor.bin file + + [*] Add Intel ME/TXE firmware + (/path/to/patched/flashregion_2_intel_me_truncated.bin) Path to management engine firmware + [ ] Verify the integrity of the supplied ME/TXE firmware + [ ] Strip down the Intel ME/TXE firmware +``` + +Save the config and `make` it again. Then flash `fd` and `bios` +according to the `final_layout.txt`: +``` +flashrom -p internal -w build/coreboot.rom -l final_layout.txt -i fd -N +flashrom -p internal -w build/coreboot.rom -l final_layout.txt -i bios -N +``` + +If you changed ME firmware back to original, flash it as well: +``` +flashrom -p internal -w build/coreboot.rom -l final_layout.txt -i me -N +``` + +Stage 2 is completed. Power off (reboot won't work again). On the next +boot, you will have completely corebooted MacBook. -- To view, visit https://review.coreboot.org/c/coreboot/+/38770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2650d5d60db7a29a1567e44e89b785def9342df2 Gerrit-Change-Number: 38770 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: vboot/Kconfig: Handle VBNV RTC offset in code
by Nico Huber (Code Review) 07 Aug '23

07 Aug '23

Hello Julius Werner, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38918 to review the following change. Change subject: vboot/Kconfig: Handle VBNV RTC offset in code ...................................................................... vboot/Kconfig: Handle VBNV RTC offset in code This way, programmers and reviewers don't have to make the calculation over and over in their heads. Change-Id: I928457febd399526fa77108d12b804ca7e53f80b Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/lib/coreboot_table.c M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/google/kahlee/Kconfig M src/mainboard/hp/z220_sff_workstation/Kconfig M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/t410/Kconfig M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/x200/Kconfig M src/mainboard/lenovo/x201/Kconfig M src/mainboard/lenovo/x220/Kconfig M src/mainboard/supermicro/x11-lga1151-series/Kconfig M src/security/vboot/Kconfig M src/security/vboot/vbnv_cmos.c M src/vendorcode/google/chromeos/acpi/chromeos.asl 17 files changed, 19 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/38918/1 diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index e42cb3b..33ce503 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -212,7 +212,7 @@ vbnv = (struct lb_range *)lb_new_record(header); vbnv->tag = LB_TAG_VBNV; vbnv->size = sizeof(*vbnv); - vbnv->range_start = CONFIG_VBOOT_VBNV_OFFSET + 14; + vbnv->range_start = CONFIG_VBOOT_VBNV_OFFSET; vbnv->range_size = VBOOT_VBNV_BLOCK_SIZE; #endif } diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 3c27b1e..fde47c2 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -38,7 +38,7 @@ config VBOOT_VBNV_OFFSET hex - default 0x2c + default 0x3a config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index ee430d0..a0a7175 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -37,7 +37,7 @@ config VBOOT_VBNV_OFFSET hex - default 0x2c + default 0x3a config MAINBOARD_DIR string diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 7d98d89..c538e12 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -107,7 +107,7 @@ config VBOOT_VBNV_OFFSET hex - default 0x2A + default 0x38 config CHROMEOS select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE diff --git a/src/mainboard/hp/z220_sff_workstation/Kconfig b/src/mainboard/hp/z220_sff_workstation/Kconfig index dc288d6..b07601a 100644 --- a/src/mainboard/hp/z220_sff_workstation/Kconfig +++ b/src/mainboard/hp/z220_sff_workstation/Kconfig @@ -28,7 +28,7 @@ config VBOOT_VBNV_OFFSET hex - default 0x2a + default 0x38 config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index deb6c8e..0cd4e5c 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -39,7 +39,7 @@ config VBOOT_VBNV_OFFSET hex - default 0x82 + default 0x90 config FMDFILE string diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig index 5d60565..744c62d 100644 --- a/src/mainboard/lenovo/t410/Kconfig +++ b/src/mainboard/lenovo/t410/Kconfig @@ -37,7 +37,7 @@ config VBOOT_VBNV_OFFSET hex - default 0x2a + default 0x38 config FMDFILE string diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index d26ad17..342cb35 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -41,7 +41,7 @@ config VBOOT_VBNV_OFFSET hex - default 0x2a + default 0x38 config FMDFILE string diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index 89f84fc..3cf721a 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -40,7 +40,7 @@ config VBOOT_VBNV_OFFSET hex - default 0x2a + default 0x38 config FMDFILE string diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 6d31be2..304ff84 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -40,7 +40,7 @@ config VBOOT_VBNV_OFFSET hex - default 0x2a + default 0x38 config VARIANT_DIR string diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index 432c805..0d1b3f5 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -36,7 +36,7 @@ config VBOOT_VBNV_OFFSET hex - default 0x82 + default 0x90 config FMDFILE string diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index a94d24e..9feb8da 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -36,7 +36,7 @@ config VBOOT_VBNV_OFFSET hex - default 0x2a + default 0x38 config FMDFILE string diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index b20255e..4e93da7 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -39,7 +39,7 @@ config VBOOT_VBNV_OFFSET hex - default 0x2a + default 0x38 config MAINBOARD_DIR string diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index e0f468c..674426d 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -56,7 +56,7 @@ config VBOOT_VBNV_OFFSET hex - default 0x2a + default 0x38 config FMDFILE string diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index ea70e65..c534d7f 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -73,11 +73,11 @@ config VBOOT_VBNV_OFFSET hex - default 0x26 + default 0x34 depends on VBOOT_VBNV_CMOS help CMOS offset for VbNv data. This value must match cmos.layout - in the mainboard directory, minus 14 bytes for the RTC. + in the mainboard directory. config VBOOT_VBNV_CMOS_BACKUP_TO_FLASH bool diff --git a/src/security/vboot/vbnv_cmos.c b/src/security/vboot/vbnv_cmos.c index 7758ef6..5cb1e96 100644 --- a/src/security/vboot/vbnv_cmos.c +++ b/src/security/vboot/vbnv_cmos.c @@ -62,7 +62,7 @@ int i; for (i = 0; i < VBOOT_VBNV_BLOCK_SIZE; i++) - vbnv_copy[i] = cmos_read(CONFIG_VBOOT_VBNV_OFFSET + 14 + i); + vbnv_copy[i] = cmos_read(CONFIG_VBOOT_VBNV_OFFSET + i); /* Verify contents before attempting a restore from backup storage. */ if (verify_vbnv(vbnv_copy)) @@ -76,7 +76,7 @@ int i; for (i = 0; i < VBOOT_VBNV_BLOCK_SIZE; i++) - cmos_write(vbnv_copy[i], CONFIG_VBOOT_VBNV_OFFSET + 14 + i); + cmos_write(vbnv_copy[i], CONFIG_VBOOT_VBNV_OFFSET + i); } void vbnv_init_cmos(uint8_t *vbnv_copy) diff --git a/src/vendorcode/google/chromeos/acpi/chromeos.asl b/src/vendorcode/google/chromeos/acpi/chromeos.asl index 4852600..29c04ef 100644 --- a/src/vendorcode/google/chromeos/acpi/chromeos.asl +++ b/src/vendorcode/google/chromeos/acpi/chromeos.asl @@ -76,7 +76,7 @@ Name(VNBV, Package() { // See src/vendorcode/google/chromeos/Kconfig // for the definition of these: - CONFIG_VBOOT_VBNV_OFFSET, + CONFIG_VBOOT_VBNV_OFFSET - 14, VBOOT_VBNV_BLOCK_SIZE }) Return(VNBV) -- To view, visit https://review.coreboot.org/c/coreboot/+/38918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I928457febd399526fa77108d12b804ca7e53f80b Gerrit-Change-Number: 38918 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: [WIP]coreboot_tables: Support multiple framebuffers
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39005 ) Change subject: [WIP]coreboot_tables: Support multiple framebuffers ...................................................................... [WIP]coreboot_tables: Support multiple framebuffers Advertise each framebuffer in a seperate CB table and get rid of fill_lb_framebuffer. Change-Id: I31c3da71ca0b96fb25219d6125c5f89d12157f74 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/include/boot/coreboot_tables.h M src/lib/coreboot_table.c M src/lib/edid_fill_fb.c 3 files changed, 23 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/39005/1 diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 5bebd4a..3887a29 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -18,14 +18,11 @@ void uart_fill_lb(void *data); void lb_add_serial(struct lb_serial *serial, void *data); void lb_add_console(uint16_t consoletype, void *data); +void lb_framebuffer(struct lb_header *header); /* Define this in mainboard.c to add board-specific table entries. */ void lb_board(struct lb_header *header); -/* Define this function to fill in the frame buffer returning 0 on success and - < 0 on error. */ -int fill_lb_framebuffer(struct lb_framebuffer *framebuffer); - /* Allow arch to add records. */ void lb_arch_add_records(struct lb_header *header); diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index e42cb3b..3f9b2dc 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -133,28 +133,6 @@ console->type = consoletype; } -static void lb_framebuffer(struct lb_header *header) -{ - struct lb_framebuffer *framebuffer; - struct lb_framebuffer fb = {0}; - - if (!CONFIG(LINEAR_FRAMEBUFFER) || fill_lb_framebuffer(&fb)) - return; - - framebuffer = (struct lb_framebuffer *)lb_new_record(header); - memcpy(framebuffer, &fb, sizeof(*framebuffer)); - framebuffer->tag = LB_TAG_FRAMEBUFFER; - framebuffer->size = sizeof(*framebuffer); - - if (CONFIG(BOOTSPLASH)) { - uint8_t *fb_ptr = (uint8_t *)(uintptr_t)framebuffer->physical_address; - unsigned int width = framebuffer->x_resolution; - unsigned int height = framebuffer->y_resolution; - unsigned int depth = framebuffer->bits_per_pixel; - set_bootsplash(fb_ptr, width, height, depth); - } -} - void lb_add_gpios(struct lb_gpios *gpios, const struct lb_gpio *gpio_table, size_t count) { @@ -531,8 +509,10 @@ /* Record our various random string information */ lb_strings(head); lb_record_version_timestamp(head); + /* Record our framebuffer */ - lb_framebuffer(head); + if (CONFIG(LINEAR_FRAMEBUFFER)) + lb_framebuffer(head); #if CONFIG(CHROMEOS) /* Record our GPIO settings (ChromeOS specific) */ diff --git a/src/lib/edid_fill_fb.c b/src/lib/edid_fill_fb.c index 3abcdd0..1928335 100644 --- a/src/lib/edid_fill_fb.c +++ b/src/lib/edid_fill_fb.c @@ -36,6 +36,8 @@ /* * Allocate a new framebuffer info struct on heap. + * The caller must not free the returned pointer. + * * Returns NULL on error. */ struct edid_fb_info *fb_new_framebuffer_info(void) @@ -147,13 +149,25 @@ return info; } -int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) +void lb_framebuffer(struct lb_header *header) { + struct lb_framebuffer *framebuffer; + for (struct edid_fb_info *i = list; i != NULL; i = i->next) { - if (i->valid) { - *framebuffer = i->edid_fb; - return 0; + if (!i->valid) + continue; + + framebuffer = (struct lb_framebuffer *)lb_new_record(header); + memcpy(framebuffer, &i->edid_fb, sizeof(*framebuffer)); + framebuffer->tag = LB_TAG_FRAMEBUFFER; + framebuffer->size = sizeof(*framebuffer); + + if (CONFIG(BOOTSPLASH)) { + uint8_t *fb_ptr = (uint8_t *)(uintptr_t)framebuffer->physical_address; + unsigned int width = framebuffer->x_resolution; + unsigned int height = framebuffer->y_resolution; + unsigned int depth = framebuffer->bits_per_pixel; + set_bootsplash(fb_ptr, width, height, depth); } } - return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31c3da71ca0b96fb25219d6125c5f89d12157f74 Gerrit-Change-Number: 39005 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 15

Change in coreboot[master]: drivers/analogix: fixup the video banking area timing to meet chip
by jitao shi (Code Review) 07 Aug '23

07 Aug '23

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39026 ) Change subject: drivers/analogix: fixup the video banking area timing to meet chip ...................................................................... drivers/analogix: fixup the video banking area timing to meet chip Fixup HFP/HBP/HSYNC meet the chip (must larger than 8 and even number) BUG=b:149051882 BRANCH=kukui TEST=None Change-Id: I3715fa854649f20fbef4e0bdfce59ebfa1f5f2b5 Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> --- M src/drivers/analogix/anx7625/anx7625.c 1 file changed, 118 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/39026/1 diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index d2d09d8..10aa8b5 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -827,6 +827,119 @@ dt->vactive, dt->vsync_len, dt->vfront_porch, dt->vback_porch); } +static void anx7625_modify_edid(struct edid *edid, + struct display_timing *dt) +{ + u32 hsync, hfp, hbp, hactive, hblanking, htotal, vtotal; + u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj; + u32 vref, adj_clock; + + hactive = dt->hactive; + hfp = dt->hfront_porch; + hbp = dt->hback_porch; + hsync = dt->hsync_len; + hblanking = hfp + hbp + hsync; + htotal = hactive + hfp + hbp + hsync; + vtotal = dt->vactive + dt->vsync_len + + dt->vfront_porch + dt->vback_porch; + + ANXINFO("before mode fixup\n"); + ANXINFO("hsync(%d),hfp(%d),hbp(%d),clock(%d)\n", + hsync, + hfp, + hbp, + dt->pixelclock); + + adj_hfp = hfp; + adj_hsync = hsync; + adj_hbp = hbp; + adj_hblanking = hblanking; + + /* plus 1 if hfp is odd */ + if (hfp & 0x1) { + adj_hfp = hfp + 1; + adj_hblanking += 1; + } + + /* minus 1 if hbp is odd */ + if (hbp & 0x1) { + adj_hbp = hbp - 1; + adj_hblanking -= 1; + } + + /* plus 1 if hsync is odd */ + if (hsync & 0x1) { + if (adj_hblanking < hblanking) + adj_hsync = hsync + 1; + else + adj_hsync = hsync - 1; + } + + /* + * once illegal timing detected, use default HFP, HSYNC, HBP + */ + if ((hblanking < HBLANKING_MIN) || (hfp < HP_MIN && hbp < HP_MIN)) + { + adj_hsync = SYNC_LEN_DEF; + adj_hfp = HFP_HBP_DEF; + adj_hbp = HFP_HBP_DEF; + vref = dt->pixelclock * 1000 / (htotal * vtotal); + if (hblanking < HBLANKING_MIN) { + delta_adj = HBLANKING_MIN - hblanking; + adj_clock = vref * delta_adj * vtotal; + dt->pixelclock += DIV_ROUND_UP(adj_clock, 1000); + } else { + delta_adj = hblanking - HBLANKING_MIN; + adj_clock = vref * delta_adj * vtotal; + dt->pixelclock -= DIV_ROUND_UP(adj_clock, 1000); + } + + ANXINFO("warn: illegal hblanking timing, use default.\n"); + ANXINFO("warn: hfp(%d),hbp(%d),hsync(%d).\n", hfp, hbp, hsync); + } else if (adj_hfp < HP_MIN) { + /* adjust hfp if hfp less than HP_MIN */ + delta_adj = HP_MIN - adj_hfp; + adj_hfp = HP_MIN; + + /* + * balance total HBlanking pixel, if HBP hasn't enough space, + * adjust HSYNC length, otherwize adjust HBP + */ + if ((adj_hbp - delta_adj) < HP_MIN) + /* hbp not enough space */ + adj_hsync -= delta_adj; + else + adj_hbp -= delta_adj; + } else if (adj_hbp < HP_MIN) { + delta_adj = HP_MIN - adj_hbp; + adj_hbp = HP_MIN; + + /* + * balance total HBlanking pixel, if HBP hasn't enough space, + * adjust HSYNC length, otherwize adjust HBP + */ + if ((adj_hfp - delta_adj) < HP_MIN) + /* hbp not enough space */ + adj_hsync -= delta_adj; + else + adj_hfp -= delta_adj; + } + + ANXINFO("after mode fixup\n"); + ANXINFO("hsync(%d),hfp(%d),hbp(%d),clock(%d)\n", + adj_hsync, + adj_hfp, + adj_hbp, + dt->pixelclock); + + /* reconstructure EDID */ + edid->mode.hspw = adj_hsync; + edid->mode.hso = adj_hfp + edid->mode.hborder; + edid->mode.hbl = adj_hbp + edid->mode.hso + + edid->mode.hspw + edid->mode.hborder; + edid->mode.pixel_clock = dt->pixelclock; +} + int anx7625_dp_start(uint8_t bus, const struct edid *edid) { int ret; @@ -847,6 +960,7 @@ { int block_num; int ret; + struct display_timing dtiming; u8 edid[FOUR_BLOCK_SIZE]; block_num = sp_tx_edid_read(bus, edid, FOUR_BLOCK_SIZE); @@ -861,6 +975,10 @@ return -1; } + anx7625_parse_edid(out, &dtiming); + + anx7625_modify_edid(out, &dtiming); + return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3715fa854649f20fbef4e0bdfce59ebfa1f5f2b5 Gerrit-Change-Number: 39026 Gerrit-PatchSet: 1 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-MessageType: newchange

5 6

← Newer
1
...
23
24
25
26
27
28
29
...
68
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2022