coreboot-gerrit June 2022

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Change in coreboot[master]: cpu/amd: Add common helpers for TSEG and SMM
by Kyösti Mälkki (Code Review) 02 Jun '22

02 Jun '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Arthur Heymans, Fred Reitberger, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64866 ) Change subject: cpu/amd: Add common helpers for TSEG and SMM ...................................................................... Patch Set 6: (1 comment) File src/cpu/amd/smm/smm_helper.c: PS5: Since cpu,nb,sb/amd/agesa,pi already calls a lot of soc/amd/common, maybe keep SMM helpers there. I don't think there is much soc/amd calling to cpu/amd. -- To view, visit https://review.coreboot.org/c/coreboot/+/64866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73174766980e0405e7b8efd4f059bb400c0c0a25 Gerrit-Change-Number: 64866 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 02 Jun 2022 12:26:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/meteorlake: Refactor bootblock SoC programming code
by Tarun Tuli (Code Review) 02 Jun '22

02 Jun '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Kapil Porwal, Angel Pons, Eric Lai. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64793 ) Change subject: soc/intel/meteorlake: Refactor bootblock SoC programming code ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8485b195f77225d8870589ff2e4d3dbdc8931f0a Gerrit-Change-Number: 64793 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 02 Jun 2022 12:26:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [NEEDSTEST]cpu/amd/family15: Use parallel_mp
by Arthur Heymans (Code Review) 02 Jun '22

02 Jun '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64892 ) Change subject: [NEEDSTEST]cpu/amd/family15: Use parallel_mp ...................................................................... [NEEDSTEST]cpu/amd/family15: Use parallel_mp This now computes an MTRR solution based on coreboots allocation and always uses that solution over the one set by AGESA. Syncing MSR is now done in sipi_vector.S. This also implement SMM in ASEG in the helper functions as some AGESA targets have an SMI handler. Change-Id: I33a5f93e3c2777fffb47400dfab9eedd774d3b2b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/agesa/family15tn/model_15_init.c M src/cpu/amd/smm/smm_helper.c M src/include/cpu/amd/msr.h M src/northbridge/amd/agesa/family15tn/Kconfig M src/northbridge/amd/agesa/family15tn/northbridge.c 5 files changed, 57 insertions(+), 164 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/64892/1 diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index a557407..a5cc5ef 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -18,42 +18,11 @@ printk(BIOS_DEBUG, "Model 15 Init.\n"); msr_t msr; - int msrno; unsigned int cpu_idx; #if CONFIG(LOGICAL_CPUS) u32 siblings; #endif - /* - * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set - * by coreboot. - */ - disable_cache(); - /* Enable access to AMD RdDram and WrDram extension bits */ - msr = rdmsr(SYSCFG_MSR); - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; - wrmsr(SYSCFG_MSR, msr); - - // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs - msr.lo = msr.hi = 0; - wrmsr(MTRR_FIX_16K_A0000, msr); - msr.lo = msr.hi = 0x1e1e1e1e; - wrmsr(MTRR_FIX_64K_00000, msr); - wrmsr(MTRR_FIX_16K_80000, msr); - for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++) - wrmsr(msrno, msr); - - msr = rdmsr(SYSCFG_MSR); - msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - msr.lo |= SYSCFG_MSR_MtrrFixDramEn; - wrmsr(SYSCFG_MSR, msr); - - if (acpi_is_wakeup_s3()) - restore_mtrr(); - - x86_mtrr_check(); - enable_cache(); /* zero the machine check error status registers */ mca_clear_status(); @@ -93,8 +62,9 @@ wrmsr(SMM_MASK_MSR, msr); } - /* Write protect SMM space with SMMLOCK. */ - lock_smm(); + /* Write protect SMM space with SMMLOCK. Done by SMM setup if used. */ + if (!CONFIG(HAVE_SMI_HANDLER)) + lock_smm(); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/amd/smm/smm_helper.c b/src/cpu/amd/smm/smm_helper.c index 9dc8725..34035a6 100644 --- a/src/cpu/amd/smm/smm_helper.c +++ b/src/cpu/amd/smm/smm_helper.c @@ -63,6 +63,14 @@ wrmsr(SMM_MASK_MSR, mask); } +static void aseg_valid(void) +{ + msr_t mask = rdmsr(SMM_MASK_MSR); + mask.lo |= SMM_ASEG_VALID; + + wrmsr(SMM_MASK_MSR, mask); +} + void lock_smm(void) { msr_t hwcr = rdmsr(HWCR_MSR); @@ -96,10 +104,8 @@ return 1 + (cpuid_ecx(0x80000008) & 0xff); } -static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) +static enum cb_err check_tseg(void) { - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - uintptr_t tseg_base; size_t tseg_size; @@ -107,21 +113,36 @@ if (!IS_ALIGNED(tseg_base, tseg_size)) { printk(BIOS_ERR, "TSEG base not aligned to TSEG size\n"); - return; + return CB_ERR; } if (tseg_size < (1 << 17)) { printk(BIOS_ERR, "TSEG size too small\n"); - return; + return CB_ERR; + } + return CB_SUCCESS; +} + +static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) +{ + printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); + + if (CONFIG(SMM_TSEG)) { + if (check_tseg() != CB_SUCCESS) + return; + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + } else { /* SMM_ASEG */ + *perm_smbase = 0xa0000; + *perm_smsize = 0x10000; } - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); } static void smm_relocation_trigger(void) { - setup_tseg(); + if (CONFIG(SMM_TSEG)) + setup_tseg(); uintptr_t smbase = smm_get_cpu_smbase(cpu_index()); msr_t msr = { @@ -130,7 +151,11 @@ }; wrmsr(SMM_BASE_MSR, msr); - tseg_valid(); + if (CONFIG(SMM_TSEG)) + tseg_valid(); + else + aseg_valid(); + lock_smm(); } diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index 37372d1..df88208 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -59,6 +59,7 @@ #define SMM_BASE_MSR 0xC0010111 #define SMM_ADDR_MSR 0xC0010112 #define SMM_MASK_MSR 0xC0010113 +#define SMM_ASEG_VALID (1 << 0) #define SMM_TSEG_VALID (1 << 1) #define SMM_TSEG_WB (6 << 12) diff --git a/src/northbridge/amd/agesa/family15tn/Kconfig b/src/northbridge/amd/agesa/family15tn/Kconfig index 5bb7cca..606ba42 100644 --- a/src/northbridge/amd/agesa/family15tn/Kconfig +++ b/src/northbridge/amd/agesa/family15tn/Kconfig @@ -2,7 +2,6 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY15_TN bool - select LEGACY_SMP_INIT select RESOURCE_ALLOCATOR_V3 if NORTHBRIDGE_AMD_AGESA_FAMILY15_TN diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 046f875..77cf6dc 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -12,7 +12,7 @@ #include <lib.h> #include <cpu/cpu.h> #include <AGESA.h> -#include <cpu/x86/lapic.h> +#include <cpu/x86/mp.h> #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <Porting.h> @@ -577,8 +577,17 @@ .enable_dev = 0, }; +static void sysconf_init(struct device *dev); + static void domain_read_resources(struct device *dev) { + struct device *dev_mc = pcidev_on_root(DEV_CDB, 0); + if (!dev_mc) { + printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB); + die(""); + } + sysconf_init(dev_mc); + unsigned int reg; /* Find the already assigned resource pairs */ @@ -767,132 +776,21 @@ node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void cpu_bus_scan(struct device *dev) +void mp_init_cpus(struct bus *cpu_bus) { - struct bus *cpu_bus; - struct device *dev_mc; - int i,j; - int coreid_bits; - int core_max = 0; - unsigned int ApicIdCoreIdSize; - unsigned int core_nums; - int siblings = 0; - unsigned int family; - - dev_mc = pcidev_on_root(DEV_CDB, 0); - if (!dev_mc) { - printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB); - die(""); - } - sysconf_init(dev_mc); - - /* Get Max Number of cores(MNC) */ - coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12; - core_max = 1 << (coreid_bits & 0x000F); //mnc - - ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); - if (ApicIdCoreIdSize) { - core_nums = (1 << ApicIdCoreIdSize) - 1; - } else { - core_nums = 3; //quad core - } - - /* Find which cpus are present */ - cpu_bus = dev->link_list; - for (i = 0; i < node_nums; i++) { - struct device *cdb_dev; - unsigned int devn; - struct bus *pbus; - - devn = DEV_CDB + i; - pbus = dev_mc->bus; - - /* Find the cpu's pci device */ - cdb_dev = pcidev_on_root(devn, 0); - if (!cdb_dev) { - /* If I am probing things in a weird order - * ensure all of the cpu's pci devices are found. - */ - int fn; - for (fn = 0; fn <= 5; fn++) { //FBDIMM? - cdb_dev = pci_probe_dev(NULL, pbus, - PCI_DEVFN(devn, fn)); - } - cdb_dev = pcidev_on_root(devn, 0); - } else { - /* Ok, We need to set the links for that device. - * otherwise the device under it will not be scanned - */ - add_more_links(cdb_dev, 4); - } - - family = cpuid_eax(1); - family = (family >> 20) & 0xFF; - if (family == 1) { //f10 - u32 dword; - cdb_dev = pcidev_on_root(devn, 3); - dword = pci_read_config32(cdb_dev, 0xe8); - siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12); - } else if (family == 6) {//f15 - cdb_dev = pcidev_on_root(devn, 5); - if (cdb_dev && cdb_dev->enabled) { - siblings = pci_read_config32(cdb_dev, 0x84); - siblings &= 0xFF; - } - } else { - siblings = 0; //default one core - } - int enable_node = cdb_dev && cdb_dev->enabled; - printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", - dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); - - for (j = 0; j <= siblings; j++) { - extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; - u32 modules = TopologyConfiguration.PlatformNumberOfModules; - u32 lapicid_start = 0; - - /* - * APIC ID calucation is tightly coupled with AGESA v5 code. - * This calculation MUST match the assignment calculation done - * in LocalApicInitializationAtEarly() function. - * And reference GetLocalApicIdForCore() - * - * Apply APIC enumeration rules - * For systems with >= 16 APICs, put the IO-APICs at 0..n and - * put the local-APICs at m..z - * - * This is needed because many IO-APIC devices only have 4 bits - * for their APIC id and therefore must reside at 0..15 - */ - - u8 plat_num_io_apics = 3; /* FIXME */ - - if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { - lapicid_start = (plat_num_io_apics - 1) / core_max; - lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); - } - u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); - printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", - i, j, apic_id); - - struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); - if (cpu) - amd_cpu_topology(cpu, i, j); - } //j - } -} - -static void cpu_bus_init(struct device *dev) -{ - initialize_cpus(dev->link_list); + extern const struct mp_ops amd_mp_ops; + extern const struct mp_ops amd_mp_ops_with_smm; + /* TODO: Handle mp_init_with_smm failure? */ + if (CONFIG(HAVE_SMI_HANDLER)) + mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm); + else + mp_init_with_smm(cpu_bus, &amd_mp_ops); } static struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, - .init = cpu_bus_init, - .scan_bus = cpu_bus_scan, + .init = mp_cpu_bus_init, }; static void root_complex_enable_dev(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/64892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33a5f93e3c2777fffb47400dfab9eedd774d3b2b Gerrit-Change-Number: 64892 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/amd/pi00730F01: Use common code for mp_init
by Arthur Heymans (Code Review) 02 Jun '22

02 Jun '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64891 ) Change subject: cpu/amd/pi00730F01: Use common code for mp_init ...................................................................... cpu/amd/pi00730F01: Use common code for mp_init Change-Id: Ia9f0eb3df8fd2dfe395f616da981cc3a0cd3b29d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/smm/smm_helper.c M src/northbridge/amd/pi/00730F01/northbridge.c 2 files changed, 7 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/64891/1 diff --git a/src/cpu/amd/smm/smm_helper.c b/src/cpu/amd/smm/smm_helper.c index d032db5..515302c 100644 --- a/src/cpu/amd/smm/smm_helper.c +++ b/src/cpu/amd/smm/smm_helper.c @@ -128,3 +128,8 @@ .per_cpu_smm_trigger = smm_relocation_trigger, .post_mp_init = global_smi_enable, }; + +const struct mp_ops amd_mp_ops = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_cpu_count, +}; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 52364a2..0a53e04 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -867,28 +867,11 @@ .acpi_name = domain_acpi_name, }; -static void pre_mp_init(void) -{ - x86_setup_mtrrs_with_detect(); - x86_mtrr_check(); -} - -static int get_cpu_count(void) -{ - uint8_t siblings = cpuid_ecx(0x80000008) & 0xff; - - return siblings + 1; -} - -static const struct mp_ops mp_ops = { - .pre_mp_init = pre_mp_init, - .get_cpu_count = get_cpu_count, -}; - void mp_init_cpus(struct bus *cpu_bus) { + extern const struct mp_ops amd_mp_ops; /* TODO: Handle mp_init_with_smm failure? */ - mp_init_with_smm(cpu_bus, &mp_ops); + mp_init_with_smm(cpu_bus, &amd_mp_ops); /* The flash is now no longer cacheable. Reset to WP for performance. */ mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE, -- To view, visit https://review.coreboot.org/c/coreboot/+/64891 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9f0eb3df8fd2dfe395f616da981cc3a0cd3b29d Gerrit-Change-Number: 64891 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: [NEEDSTEST]cpu/amd/family16: Use parallel mp init
by Arthur Heymans (Code Review) 02 Jun '22

02 Jun '22

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64496 to look at the new patch set (#2). Change subject: [NEEDSTEST]cpu/amd/family16: Use parallel mp init ...................................................................... [NEEDSTEST]cpu/amd/family16: Use parallel mp init This now computes an MTRR solution based on coreboots allocation and always uses that solution over the one set by AGESA. Syncing MSR is now done in sipi_vector.S. Change-Id: If3326c5fbd278f8f974d5408e16440e3b56b1b44 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/agesa/family16kb/model_16_init.c M src/northbridge/amd/agesa/family16kb/Kconfig M src/northbridge/amd/agesa/family16kb/northbridge.c 3 files changed, 30 insertions(+), 168 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/64496/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3326c5fbd278f8f974d5408e16440e3b56b1b44 Gerrit-Change-Number: 64496 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [NEEDSTEST]cpu/amd/family14: Use parallel mp init
by Arthur Heymans (Code Review) 02 Jun '22

02 Jun '22

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64495 to look at the new patch set (#2). Change subject: [NEEDSTEST]cpu/amd/family14: Use parallel mp init ...................................................................... [NEEDSTEST]cpu/amd/family14: Use parallel mp init This now computes an MTRR solution based on coreboots allocation and always uses that solution over the one set by AGESA. Syncing MSR is now done in sipi_vector.S. Change-Id: I73a866462b0cb6fcaeb0a47eef7a1b16747240fb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/agesa/family14/model_14_init.c M src/cpu/amd/smm/smm_helper.c M src/northbridge/amd/agesa/family14/Kconfig M src/northbridge/amd/agesa/family14/northbridge.c 4 files changed, 37 insertions(+), 80 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/64495/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73a866462b0cb6fcaeb0a47eef7a1b16747240fb Gerrit-Change-Number: 64495 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/amd/smm: Move MP & SMM init in a common place
by Arthur Heymans (Code Review) 02 Jun '22

02 Jun '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. Hello Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64870 to look at the new patch set (#6). Change subject: cpu/amd/smm: Move MP & SMM init in a common place ...................................................................... cpu/amd/smm: Move MP & SMM init in a common place Change-Id: I7c457ab69581f8c29f2d79c054ca3bc7e58a896e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/smm/smm_helper.c M src/include/cpu/amd/smm.h M src/soc/amd/cezanne/cpu.c M src/soc/amd/common/block/cpu/smm/Makefile.inc D src/soc/amd/common/block/cpu/smm/smm_relocate.c M src/soc/amd/common/block/include/amdblocks/smm.h M src/soc/amd/picasso/cpu.c M src/soc/amd/sabrina/cpu.c M src/soc/amd/stoneyridge/cpu.c 9 files changed, 71 insertions(+), 189 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/64870/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/64870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c457ab69581f8c29f2d79c054ca3bc7e58a896e Gerrit-Change-Number: 64870 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/amd: Add common helpers for TSEG and SMM
by Arthur Heymans (Code Review) 02 Jun '22

02 Jun '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. Hello Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64866 to look at the new patch set (#6). Change subject: cpu/amd: Add common helpers for TSEG and SMM ...................................................................... cpu/amd: Add common helpers for TSEG and SMM Change-Id: I73174766980e0405e7b8efd4f059bb400c0c0a25 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/Kconfig M src/cpu/amd/Makefile.inc M src/cpu/amd/agesa/Kconfig M src/cpu/amd/agesa/family14/model_14_init.c M src/cpu/amd/agesa/family15tn/model_15_init.c M src/cpu/amd/agesa/family16kb/model_16_init.c M src/cpu/amd/pi/00730F01/model_16_init.c M src/cpu/amd/pi/Kconfig M src/cpu/amd/smm/Makefile.inc A src/cpu/amd/smm/smm_helper.c A src/include/cpu/amd/smm.h M src/soc/amd/common/block/cpu/Kconfig M src/soc/amd/common/block/cpu/noncar/memmap.c M src/soc/amd/common/block/cpu/smm/Makefile.inc M src/soc/amd/common/block/cpu/smm/finalize.c D src/soc/amd/common/block/cpu/smm/smm_helper.c M src/soc/amd/common/block/cpu/smm/smm_relocate.c M src/soc/amd/common/block/include/amdblocks/smm.h M src/soc/amd/stoneyridge/memmap.c 19 files changed, 129 insertions(+), 91 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/64866/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/64866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73174766980e0405e7b8efd4f059bb400c0c0a25 Gerrit-Change-Number: 64866 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: tree-wide: Translate KiB variants of memory allocators
by build bot (Jenkins) (Code Review) 02 Jun '22

02 Jun '22

Attention is currently required from: Arthur Heymans, Hung-Te Lin, Jeff Daly, Raul Rangel, Philipp Hug, Mariusz Szafrański, Julius Werner, Angel Pons, Andrey Petrov, Patrick Rudolph, Xi Chen, Jason Glenesk, Damien Zammit, Marshall Dawson, Christian Walter, Tim Wawrzynczak, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Fred Reitberger, ron minnich, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55937 ) Change subject: tree-wide: Translate KiB variants of memory allocators ...................................................................... Patch Set 4: (8 comments) File src/soc/intel/common/block/systemagent/systemagent.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150544): https://review.coreboot.org/c/coreboot/+/55937/comment/f80aa8fa_0bdd492e PS4, Line 272: CONFIG_EXT_BIOS_WIN_SIZE); code indent should use tabs where possible File src/soc/qualcomm/sc7180/soc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150544): https://review.coreboot.org/c/coreboot/+/55937/comment/ef73c37e_a9833652 PS4, Line 17: REGION_SIZE(dram_aop)); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150544): https://review.coreboot.org/c/coreboot/+/55937/comment/e6687514_b2959f67 PS4, Line 19: REGION_SIZE(dram_soc)); code indent should use tabs where possible File src/soc/qualcomm/sc7280/soc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150544): https://review.coreboot.org/c/coreboot/+/55937/comment/c476e20c_ddc48429 PS4, Line 17: REGION_SIZE(dram_soc)); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150544): https://review.coreboot.org/c/coreboot/+/55937/comment/5b126aa3_8128ba6b PS4, Line 19: REGION_SIZE(dram_wlan)); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150544): https://review.coreboot.org/c/coreboot/+/55937/comment/cdf124fe_1c7d98d3 PS4, Line 21: REGION_SIZE(dram_wpss)); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150544): https://review.coreboot.org/c/coreboot/+/55937/comment/610a4146_c50c7710 PS4, Line 23: REGION_SIZE(dram_aop)); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150544): https://review.coreboot.org/c/coreboot/+/55937/comment/6636229c_9475c46c PS4, Line 25: REGION_SIZE(dram_cpucp)); code indent should use tabs where possible -- To view, visit https://review.coreboot.org/c/coreboot/+/55937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I903c0183e7fc6b14aeb00325cd10cd48682c2e85 Gerrit-Change-Number: 55937 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Damien Zammit Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 02 Jun 2022 12:20:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: device/resource: Drop KiB variants of allocators
by Kyösti Mälkki (Code Review) 02 Jun '22

02 Jun '22

Attention is currently required from: Jeff Daly, Damien Zammit, Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Angel Pons. Hello build bot (Jenkins), Jeff Daly, Damien Zammit, Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64754 to look at the new patch set (#8). Change subject: device/resource: Drop KiB variants of allocators ...................................................................... device/resource: Drop KiB variants of allocators Change-Id: Idcaf9ee26a6324c825b8493f31166658fae95ad4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/include/device/device.h 1 file changed, 0 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/64754/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/64754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcaf9ee26a6324c825b8493f31166658fae95ad4 Gerrit-Change-Number: 64754 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Damien Zammit Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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