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Hello Sam McNally, build bot (Jenkins), Reka Norman, Kangheui Won, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63366
to look at the new patch set (#11).
Change subject: mb/google/brya/var/nereid: Configure descriptor for either Type-C or HDMI
......................................................................
mb/google/brya/var/nereid: Configure descriptor for either Type-C or HDMI
Some bytes in the descriptor need to be set differently for Type-C and
HDMI. To allow using a single firmware variant for both cases, update
the descriptor at runtime based on fw_config. This is a temporary
workaround while we find a better solution.
The byte values were determined by changing the following CSE strap and
comparing the generated descriptors:
Type-C: TypeCPort2Config = "No Thunderbolt"
HDMI: TypeCPort2Config = "DP Fixed Connection"
The default value before updating the descriptor is Type-C, but this was
chosen arbitrarily.
BUG=b:226848617
TEST=Type-C and HDMI both work on nereid with fw_config set correctly.
Change-Id: I2cc230e3bd35816c81989ae7e01df5d2c152062e
Signed-off-by: Reka Norman <rekanorman(a)google.com>
---
M src/mainboard/google/brya/Kconfig.name
M src/mainboard/google/brya/bootblock.c
M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/brya/variants/nereid/Makefile.inc
M src/mainboard/google/brya/variants/nereid/variant.c
5 files changed, 41 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/63366/11
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Change subject: link Agesa into bootblock
......................................................................
Patch Set 13:
(1 comment)
File src/drivers/amd/agesa/bootblock.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145617):
https://review.coreboot.org/c/coreboot/+/55070/comment/1b3bc726_692ad721
PS13, Line 47: void (*ap_romstage_entry)(void) = get_ap_entry_ptr();
function definition argument 'void' should also have an identifier name
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Change subject: Allow to build romstage sources inside the bootblock
......................................................................
Patch Set 14:
(1 comment)
File src/include/rules.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145616):
https://review.coreboot.org/c/coreboot/+/55068/comment/e799534e_0f3e6e37
PS14, Line 313: #define ENV_FIRST_CBMEM_STAGE (CONFIG(SEPARATE_ROMSTAGE) ? ENV_ROMSTAGE : ENV_BOOTBLOCK)
line over 96 characters
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Change subject: Kconfig: Set better defaults for building romstage
......................................................................
Patch Set 6: Verified-1
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Change subject: link Agesa into bootblock
......................................................................
Patch Set 12:
(1 comment)
File src/drivers/amd/agesa/bootblock.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145611):
https://review.coreboot.org/c/coreboot/+/55070/comment/6f19fef4_54bda6c8
PS12, Line 47: void (*ap_romstage_entry)(void) = get_ap_entry_ptr();
function definition argument 'void' should also have an identifier name
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Change subject: Allow to build romstage sources inside the bootblock
......................................................................
Patch Set 13:
(1 comment)
File src/include/rules.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145610):
https://review.coreboot.org/c/coreboot/+/55068/comment/c31fd1e3_796685fe
PS13, Line 313: #define ENV_FIRST_CBMEM_STAGE (CONFIG(SEPARATE_ROMSTAGE) ? ENV_ROMSTAGE : ENV_BOOTBLOCK)
line over 96 characters
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Change subject: link Agesa into bootblock
......................................................................
Patch Set 11:
(1 comment)
File src/drivers/amd/agesa/bootblock.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145603):
https://review.coreboot.org/c/coreboot/+/55070/comment/50a3fcf0_5ed523f2
PS11, Line 47: void (*ap_romstage_entry)(void) = get_ap_entry_ptr();
function definition argument 'void' should also have an identifier name
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Change subject: Allow to build romstage sources inside the bootblock
......................................................................
Patch Set 12:
(1 comment)
File src/include/rules.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145602):
https://review.coreboot.org/c/coreboot/+/55068/comment/2dcf85a6_2596e6c8
PS12, Line 313: #define ENV_FIRST_CBMEM_STAGE (CONFIG(SEPARATE_ROMSTAGE) ? ENV_ROMSTAGE : ENV_BOOTBLOCK)
line over 96 characters
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Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63403 )
Change subject: util/intelp2m: Add support for Alder Lake H macro generation
......................................................................
Patch Set 1:
(12 comments)
Patchset:
PS1:
Thank you for this work!
File util/intelp2m/description.md:
https://review.coreboot.org/c/coreboot/+/63403/comment/9619df3d_c17756e1
PS1, Line 39: CPU
PCH
https://review.coreboot.org/c/coreboot/+/63403/comment/573fbd6e_c00cff8d
PS1, Line 39: AlderLake-H
Please, could you clarify how the pads in the H variant differ from other platforms of the Alder Lake family?
File util/intelp2m/main.go:
https://review.coreboot.org/c/coreboot/+/63403/comment/1aa94a60_422cd1ff
PS1, Line 72: CPU
PCH
File util/intelp2m/platforms/adl_h/macro.go:
PS1:
It seems to me that this platform is more like Cannon Lake than Sunrise PCH.
In that case, then I suggest defining this interface to use the functions for the Canon Lake platform - * Steps 1, 2, 3 *.
Please repeat the TEST after the changes and compare with the previous result.
Currently, this solution is used against code duplication.
I plan to start working on a global code update in a few months and maybe rework it.
https://review.coreboot.org/c/coreboot/+/63403/comment/16447c96_29d42892
PS1, Line 1: adl_h
For golang, it is preferable not to use the underscore in the package name.
Use "adlh" here and in the package file path too.
https://review.coreboot.org/c/coreboot/+/63403/comment/c742a4bc_7c9daeb6
PS1, Line 22:
step 1: Let's add functions to the interface that have a common code with Cannon Lake.
https://review.coreboot.org/c/coreboot/+/63403/comment/f24b2e69_9c409a91
PS1, Line 23: type InheritanceMacro interface {
: GpoMacroAdd()
: NativeFunctionMacroAdd()
: NoConnMacroAdd()
: }
type InheritanceMacro interface {
GpoMacroAdd()
NativeFunctionMacroAdd()
NoConnMacroAdd()
Pull()
GpiMacroAdd()
}
(step 1)
https://review.coreboot.org/c/coreboot/+/63403/comment/3c6ef90a_5e0c8f8a
PS1, Line 67: func (PlatformSpecific) Pull() {
func (platform PlatformSpecific) Pull() {
platform.InheritanceMacro.Pull()
}
(step 2)
https://review.coreboot.org/c/coreboot/+/63403/comment/822f6e5a_d286f1a8
PS1, Line 106: // Generate macro to cause NMI when configured in GPIO input mode
: func nmiRoute() bool {
: macro := common.GetMacro()
: if macro.Register(PAD_CFG_DW0).GetGPIOInputRouteNMI() == 0 {
: return false
: }
: // PAD_CFG_GPI_NMI(GPIO_24, UP_20K, DEEP, LEVEL, INVERT),
: macro.Add("_NMI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),")
: return true
: }
:
: // Generate macro to cause SCI when configured in GPIO input mode
: func sciRoute() bool {
: macro := common.GetMacro()
: dw0 := macro.Register(PAD_CFG_DW0)
: if dw0.GetGPIOInputRouteSCI() == 0 {
: return false
: }
: // PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv)
: macro.Add("_SCI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),")
: return true
: }
:
: // Generate macro to cause SMI when configured in GPIO input mode
: func smiRoute() bool {
: macro := common.GetMacro()
: dw0 := macro.Register(PAD_CFG_DW0)
: if dw0.GetGPIOInputRouteSMI() == 0 {
: return false
: }
: // PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv)
: macro.Add("_SMI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),")
: return true
: }
remove
https://review.coreboot.org/c/coreboot/+/63403/comment/07f5a594_f6ac2c84
PS1, Line 142: func (PlatformSpecific) GpiMacroAdd() {
func (platform PlatformSpecific) GpiMacroAdd() {
platform.InheritanceMacro.GpiMacroAdd()
}
(step 2)
https://review.coreboot.org/c/coreboot/+/63403/comment/1c143f74_e1127f90
PS1, Line 204: snr.PlatformSpecific{}
cnl.PlatformSpecific{}
(step 3)
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