coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/brask/variants/moli: add delay time to rtd3-cold
by Tim Wawrzynczak (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: YH Lin, Paul Menzel, Zhuohao Lee, Raihow Shi, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63544 ) Change subject: mb/google/brask/variants/moli: add delay time to rtd3-cold ...................................................................... Patch Set 6: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63544/comment/47fdcb5a_5f39774b PS1, Line 9: which will turn : off the eMMC controller (a true D3cold state) during the RTD3 sequence. > The reason is both primus and moli use BH799BB, so I follow this CL: https://review.coreboot. […] The reason is that the rise and fall times of each signal may differ by board, and so those board-specific delays must be taken into account when power sequencing. -- To view, visit https://review.coreboot.org/c/coreboot/+/63544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idecb1c89655c9b8b720c3c65efc77e06e6a8b300 Gerrit-Change-Number: 63544 Gerrit-PatchSet: 6 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 12 Apr 2022 19:04:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: set RFI Spread Spectrum to 6%
by Tim Wawrzynczak (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Robert Chen. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63440 ) Change subject: mb/google/brya/var/vell: set RFI Spread Spectrum to 6% ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cdca8f51ad18f4ab03e4e6c744b60da68263ce2 Gerrit-Change-Number: 63440 Gerrit-PatchSet: 6 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 19:02:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/{sa, adl}: Add `finalize` operation for systemagent
by Tim Wawrzynczak (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Subrata Banik, Nick Vaccaro, Angel Pons, Arthur Heymans, Lean Sheng Tan, Eric Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63518 ) Change subject: soc/intel/common/{sa, adl}: Add `finalize` operation for systemagent ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/systemagent/systemagent.c: https://review.coreboot.org/c/coreboot/+/63518/comment/82e9922e_ce137fd5 PS2, Line 337: skip = CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE), is it harmful to attempt to lock the PAM registers twice? i.e., does this need to be skipped only if the Kconfig is true or can we always send it? i.e., sa_final() would just be set to e.g. ``` static void systemagent_final(struct device *dev) { sa_lock_pam(); } ``` also are there more steps to come here later? -- To view, visit https://review.coreboot.org/c/coreboot/+/63518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd464d2507393ed0c746eb1fbd10e36092ed5599 Gerrit-Change-Number: 63518 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 19:02:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/xhci: Add function to reset the XHCI controller
by Tim Wawrzynczak (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Sridhar Siricilla, Nick Vaccaro, Eric Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63551 ) Change subject: soc/intel/cmn/xhci: Add function to reset the XHCI controller ...................................................................... Patch Set 3: Code-Review+2 (1 comment) File src/soc/intel/common/block/xhci/xhci.c: https://review.coreboot.org/c/coreboot/+/63551/comment/68af327e_2c060175 PS3, Line 15: : #define XHCI_USBCMD 0x80 : #define USBCMD_HCRST (1 << 1) nit: align right side with tabs -- To view, visit https://review.coreboot.org/c/coreboot/+/63551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0dc0a64044f291893931726d26c08c8b964a3cc Gerrit-Change-Number: 63551 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 19:00:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Reset XHCI controller while preparing for S5
by Tim Wawrzynczak (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Sridhar Siricilla, Nick Vaccaro, Eric Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63552 ) Change subject: mb/google/brya: Reset XHCI controller while preparing for S5 ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/smihandler.c: https://review.coreboot.org/c/coreboot/+/63552/comment/3bfa76fc_5a9f7700 PS3, Line 16: ACPI_S5 did this also end up applying to S3? -- To view, visit https://review.coreboot.org/c/coreboot/+/63552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf06a64f055a0cee3659b410652082f31e18e149 Gerrit-Change-Number: 63552 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 19:00:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Disable PCH USB2 phy power gating for felwinter
by Tim Wawrzynczak (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Paul Menzel, Sridhar Siricilla, Angel Pons. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63294 ) Change subject: mb/google/brya: Disable PCH USB2 phy power gating for felwinter ...................................................................... Patch Set 9: Code-Review-1 (1 comment) Patchset: PS9: I don't know that we want this patch in yet given the power costs and lack of testing -- To view, visit https://review.coreboot.org/c/coreboot/+/63294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25033ea218fa3154eb99af6be43c4198f4db3bcb Gerrit-Change-Number: 63294 Gerrit-PatchSet: 9 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 18:57:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: apple/macbook21: configure the clockgen and add C3 CPU state
by Ferass EL HAFIDI (Code Review) 12 Apr '22

12 Apr '22

Ferass EL HAFIDI has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63587 ) Change subject: apple/macbook21: configure the clockgen and add C3 CPU state ...................................................................... apple/macbook21: configure the clockgen and add C3 CPU state To add the C3 CPU state, the clockgen has to be reconfigured. The values are taken from the vendor firmware with i2cdump. Change-Id: Ib97f95599fbdf66aa55e936bdcb9cc0cd69b3824 Signed-off-by: Ferass 'Vitali64' EL HAFIDI <vitali64pmemail(a)protonmail.com> --- M src/mainboard/apple/macbook21/Kconfig M src/mainboard/apple/macbook21/cstates.c M src/mainboard/apple/macbook21/devicetree.cb 3 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/63587/1 diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig index 5f5ffde..27377b7 100644 --- a/src/mainboard/apple/macbook21/Kconfig +++ b/src/mainboard/apple/macbook21/Kconfig @@ -16,6 +16,7 @@ select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select I945_LVDS + select DRIVERS_I2C_CK505 config MAINBOARD_DIR default "apple/macbook21" diff --git a/src/mainboard/apple/macbook21/cstates.c b/src/mainboard/apple/macbook21/cstates.c index 13d06f0..076a096 100644 --- a/src/mainboard/apple/macbook21/cstates.c +++ b/src/mainboard/apple/macbook21/cstates.c @@ -29,6 +29,18 @@ .addrh = 0, } }, + { + .ctype = 3, + .latency = 1, + .power = 250, + .resource = { + .space_id = ACPI_ADDRESS_SPACE_FIXED, + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, + .access_size = ACPI_ACCESS_SIZE_UNDEFINED, + .addrl = 0x20, + .addrh = 0, + } }; int get_cst_entries(const acpi_cstate_t **entries) diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index bcce778..1626808 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -104,6 +104,11 @@ end device pci 1f.3 on # SMBUS subsystemid 0x8086 0x7270 + chip drivers/i2c/ck505 + register "mask" = "{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }" + register "regs" = "{ 0x77, 0x77, 0x2d, 0x00, 0x21, 0x10, 0x3b, 0x06, 0x07, 0x0f, 0xf0, 0x01, 0x1e, 0x7f, 0x80, 0x80, 0x10, 0x08, 0x04, 0x01 }" + device i2c 69 on end + end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/63587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib97f95599fbdf66aa55e936bdcb9cc0cd69b3824 Gerrit-Change-Number: 63587 Gerrit-PatchSet: 1 Gerrit-Owner: Ferass EL HAFIDI <vitali64pmemail(a)protonmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/amd/common: Move RAM calcualtion to common code
by Kyösti Mälkki (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Nico Huber, Michał Żygowski, Michał Kopeć, Paul Menzel, Arthur Heymans. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61682 ) Change subject: nb/amd/common: Move RAM calcualtion to common code ...................................................................... Patch Set 6: (7 comments) File src/northbridge/amd/agesa/family14/northbridge.c: https://review.coreboot.org/c/coreboot/+/61682/comment/88cbdc6c_4631b3c6 PS6, Line 27: static unsigned int fx_devs = 0; These arrays reduce to single struct device *, therefore any loops with FX_DEVS or fx_devs or nodeid != 0 just makes the source unreadable. https://review.coreboot.org/c/coreboot/+/61682/comment/ba22e738_308d94f1 PS6, Line 77: __f4_dev[i] = get_node_pci(i, 4); So.. FX_DEVS==1. https://review.coreboot.org/c/coreboot/+/61682/comment/7d57961e_eb7f094f PS6, Line 79: fx_devs = i + 1; It's safe to assume the conditional does not fail, thus fx_devs==1 in this file. https://review.coreboot.org/c/coreboot/+/61682/comment/f9ed9ba3_210f0b50 PS6, Line 100: dev = __f1_dev[i]; dev = pcidev_on_root(DEV_CDB, 1) ? File src/northbridge/amd/agesa/family15tn/northbridge.c: https://review.coreboot.org/c/coreboot/+/61682/comment/a68b9ced_a4b990db PS6, Line 25: #define MAX_NODE_NUMS MAX_NODES In reality 1 src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.h: #define MAX_NODES_SUPPORTED_TN 1 File src/northbridge/amd/agesa/family16kb/northbridge.c: https://review.coreboot.org/c/coreboot/+/61682/comment/42e03bcb_dcb52c1e PS6, Line 25: #define MAX_NODE_NUMS MAX_NODES In reality 1 src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.h: #define MAX_NODES_SUPPORTED_KB 1 File src/northbridge/amd/pi/00730F01/northbridge.c: https://review.coreboot.org/c/coreboot/+/61682/comment/8344f1c0_2d3ba7c1 PS6, Line 28: #define MAX_NODE_NUMS MAX_NODES src/vendorcode/amd/pi/00730F01/Include/Topology.h:#define MAX_NODES 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d222f6cbd26fe78d968d2883984f25e8b62ab5c Gerrit-Change-Number: 61682 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 12 Apr 2022 18:28:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mb/google,intel: Split chromeos.c files
by Julius Werner (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Tim Wawrzynczak, Nick Vaccaro, Kyösti Mälkki, Fred Reitberger, Felix Held. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59011 ) Change subject: [WIP] mb/google,intel: Split chromeos.c files ...................................................................... Patch Set 9: (1 comment) Patchset: PS9: Do we have to split all these files up? I feel like GPIO setup and filling out the GPIO table belongs logically together (and it's nice to be able to see on one screen whether each GPIO in the table also gets initialized and vice versa). lb_gpios() in coreboot_table.c is already guarded by CHROMEOS, so it wouldn't hurt to compile these for all configs. I'm okay with renaming these and making them non-CHROMEOS-specific if that's useful (although I'm not sure the name `bootmode` really fits for everything there... maybe just `gpios.c` or `board.c`? We often call the header that defines GPIO constants `board.h`, after all...), but I'd prefer them to stay all in one file. -- To view, visit https://review.coreboot.org/c/coreboot/+/59011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71a02c5fa1b256316b86b673660bf22dfd284f7f Gerrit-Change-Number: 59011 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 12 Apr 2022 18:01:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/lint/checkpatch.pl: Update lines related to tabsize
by Elyes Haouas (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Martin Roth. Hello build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63438 to look at the new patch set (#6). Change subject: util/lint/checkpatch.pl: Update lines related to tabsize ...................................................................... util/lint/checkpatch.pl: Update lines related to tabsize Update to v5.18-2 version. Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I6651a3f8e79beca2e1235fe8de3217875f81ba2b --- M util/lint/checkpatch.pl 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/63438/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/63438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6651a3f8e79beca2e1235fe8de3217875f81ba2b Gerrit-Change-Number: 63438 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2022