coreboot-gerrit April 2022

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Change in coreboot[master]: mb/google/nipperkin: Disable PSPP for WLAN
by Raul Rangel (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Rob Barnes, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63593 ) Change subject: mb/google/nipperkin: Disable PSPP for WLAN ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/mainboard/google/guybrush/variants/nipperkin/variant.c: https://review.coreboot.org/c/coreboot/+/63593/comment/170de5aa_2919abf3 PS1, Line 16: Disable Can you add a b/ explaining why? -- To view, visit https://review.coreboot.org/c/coreboot/+/63593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38f05b92ace4aba61163194a6a638915882b8871 Gerrit-Change-Number: 63593 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 20:39:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/nipperkin: Disable PSPP for WLAN
by Felix Held (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Raul Rangel, Rob Barnes, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63593 ) Change subject: mb/google/nipperkin: Disable PSPP for WLAN ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/mainboard/google/guybrush/variants/nipperkin/variant.c: https://review.coreboot.org/c/coreboot/+/63593/comment/ad0a12ce_35a8f70b PS1, Line 17: memset(dxio_descriptors[WLAN].port_params, 0, should this only be done for board_version >= 3 or for all board revisions? i'd also use a loop instead of a memset, but either works and i don't have a too strong preference here -- To view, visit https://review.coreboot.org/c/coreboot/+/63593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38f05b92ace4aba61163194a6a638915882b8871 Gerrit-Change-Number: 63593 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 20:38:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: checkpatch.conf: Disable gerrit change ID for coreboot
by Subrata Banik (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Martin Roth, Paul Menzel. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63030 ) Change subject: checkpatch.conf: Disable gerrit change ID for coreboot ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f6efb5559027ed9497ee85497bb4b4e786f9901 Gerrit-Change-Number: 63030 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 12 Apr 2022 20:31:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: add WWAN power sequence setting for vell
by Felix Held (Code Review) 12 Apr '22

12 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61847 ) Change subject: mb/google/brya/var/vell: add WWAN power sequence setting for vell ...................................................................... mb/google/brya/var/vell: add WWAN power sequence setting for vell Add WWAN power sequence setting to meet spec BUG=b:220084872 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: If6d3f965b8f6b6753446f55a8bd47d3b0c1ae7be Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61847 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/vell/gpio.c M src/mainboard/google/brya/variants/vell/overridetree.cb 2 files changed, 16 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/vell/gpio.c b/src/mainboard/google/brya/variants/vell/gpio.c index e9600da..57f8564 100644 --- a/src/mainboard/google/brya/variants/vell/gpio.c +++ b/src/mainboard/google/brya/variants/vell/gpio.c @@ -39,11 +39,17 @@ PAD_CFG_NF_LOCK(GPP_E12, NONE, NF3, LOCK_CONFIG), /* E13 : THC0_SPI1_IO2 ==> UWB_GSPI0_DO */ PAD_CFG_NF_LOCK(GPP_E13, NONE, NF3, LOCK_CONFIG), + /* E16 : RSVD_TP ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_E16, 1, DEEP), /* E22 : DDPA_CTRLCLK ==> WWAN_CONFIG0 */ PAD_CFG_GPI(GPP_E22, NONE, DEEP), /* E23 : DDPA_CTRLDATA ==> USB_C3_OC_ODL */ PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), - + /* + * E0 : SATAXPCIE0 ==> WWAN_PERST_L + * Drive high here, so that PERST_L is sequenced after RST_L + */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), /* F19 : NC */ PAD_NC(GPP_F19, NONE), @@ -94,6 +100,8 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* B4 : PROC_GP3 ==> SSD_PERST_L */ @@ -117,7 +125,8 @@ PAD_CFG_GPO(GPP_D3, 1, DEEP), /* D11 : ISH_SPI_MISO ==> USB_C0_LSX_SOC_TX */ PAD_CFG_NF(GPP_D11, NONE, DEEP, NF4), - + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */ + PAD_CFG_GPO(GPP_E0, 0, DEEP), /* E3 : PROC_GP0 ==> MEM_STRAP_0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* E5 : SATA_DEVSLP1 ==> MEM_CH_SEL */ @@ -131,6 +140,8 @@ PAD_CFG_GPO(GPP_E16, 0, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ @@ -162,6 +173,8 @@ static const struct pad_config romstage_gpio_table[] = { /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ + PAD_CFG_GPO(GPP_F21, 1, DEEP), }; const struct pad_config *variant_romstage_gpio_table(size_t *num) diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index b12a00d..fd5f27a 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -196,7 +196,7 @@ register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)" register "add_acpi_dma_property" = "true" use rp6_rtd3 as rtd3dev - device generic 0 on end + device generic 0 alias rp6_wwan on end end end device ref pcie_rp8 off end -- To view, visit https://review.coreboot.org/c/coreboot/+/61847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6d3f965b8f6b6753446f55a8bd47d3b0c1ae7be Gerrit-Change-Number: 61847 Gerrit-PatchSet: 27 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: arch/x86/postcar_loader.c: Provide a NOOP weak postcar_fill_frame
by Arthur Heymans (Code Review) 12 Apr '22

12 Apr '22

1 0

Change in coreboot[master]: arch/x86/postcar_loader.c: Add common code for CBMEM and TSEG
by Arthur Heymans (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Jeff Daly, Mariusz Szafrański, Jonathan Zhang, Angel Pons, Anjaneya "Reddy" Chagam, Damien Zammit, Lee Leahy, Marshall Dawson, Johnny Lin, Christian Walter, Suresh Bellampalli, Vanessa Eusebio, Tim Chu, Felix Held. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63594 ) Change subject: arch/x86/postcar_loader.c: Add common code for CBMEM and TSEG ...................................................................... arch/x86/postcar_loader.c: Add common code for CBMEM and TSEG Move the boilerplate code to set up MTRR for cbmem and TSEG into a common location. The empty function calls will be cleaned up in a follow up. Change-Id: I86c76c69fdb6a7930c2ba7dcd21fd9d368c680e0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/postcar_loader.c M src/drivers/intel/fsp1_1/car.c M src/mainboard/emulation/qemu-i440fx/memmap.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/ironlake/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/common/block/systemagent/memmap.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/xeon_sp/memmap.c 17 files changed, 36 insertions(+), 161 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/63594/1 diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 810be93..0545210 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -10,6 +10,7 @@ #include <reset.h> #include <rmodule.h> #include <stage_cache.h> +#include <stdint.h> #include <timestamp.h> #include <security/vboot/vboot_common.h> @@ -48,11 +49,45 @@ postcar_frame_add_mtrr(pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, type); } +static void postcar_frame_add_cbmem_cache(struct postcar_frame *pcf) +{ + uintptr_t cbmem_base; + size_t cbmem_size; + + /* Try account for the CBMEM region currently used and for future use */ + cbmem_get_region((void **)&cbmem_base, &cbmem_size); + + if (cbmem_base <= 4 * MiB) + return; + cbmem_base -= 4 * MiB; + cbmem_size += 4 * MiB; + /* Align to make sure we don't use too many MTRR's */ + cbmem_base = ALIGN_DOWN(cbmem_base, 4 * MiB); + cbmem_size = ALIGN_UP(cbmem_size, 4 * MiB); + + postcar_frame_add_mtrr(pcf, cbmem_base, cbmem_size, MTRR_TYPE_WRBACK); +} + +static void postcar_frame_add_external_stage_cache(struct postcar_frame *pcf) +{ + if (CONFIG(TSEG_STAGE_CACHE)) + return; + uintptr_t stage_cache_base; + size_t stage_cache_size; + stage_cache_external_region((void **)&stage_cache_base, &stage_cache_size); + if (stage_cache_size != 0) + postcar_frame_add_mtrr(pcf, stage_cache_base, stage_cache_size, MTRR_TYPE_WRBACK); +} + static void postcar_frame_common_mtrrs(struct postcar_frame *pcf) { if (pcf->skip_common_mtrr) return; + postcar_frame_add_cbmem_cache(pcf); + + postcar_frame_add_external_stage_cache(pcf); + /* Cache the ROM as WP just below 4GiB. */ postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT); } diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 5d41a01..65cf3d4 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -12,14 +12,6 @@ void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB - * above top of the ram. This satisfies MTRR alignment requirement - * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); - } /* This is the romstage entry called from cpu/intel/car/romstage.c */ diff --git a/src/mainboard/emulation/qemu-i440fx/memmap.c b/src/mainboard/emulation/qemu-i440fx/memmap.c index 75ab352..5a2aa6b 100644 --- a/src/mainboard/emulation/qemu-i440fx/memmap.c +++ b/src/mainboard/emulation/qemu-i440fx/memmap.c @@ -62,4 +62,5 @@ /* Nothing to do, MTRRs are no-op on QEMU. */ void fill_postcar_frame(struct postcar_frame *pcf) { + pcf->skip_common_mtrr = 1; } diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index 28edb38..2e98cf0 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -118,15 +118,4 @@ void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - - /* Cache 8 MiB region below the top of RAM and 2 MiB above top of - * RAM to cover both cbmem as the TSEG region. - */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, - MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), - northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); - } diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index c19cfec..84fe86f 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -69,12 +69,4 @@ void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB - * above top of the ram. This satisfies MTRR alignment requirement - * with different TSEG size configurations. - */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8 * MiB); - postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); } diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c index b6d9526..321421c 100644 --- a/src/northbridge/intel/i440bx/memmap.c +++ b/src/northbridge/intel/i440bx/memmap.c @@ -53,11 +53,4 @@ void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - - /* Cache CBMEM region as WB. */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, - MTRR_TYPE_WRBACK); - } diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 1dea21c..556b9a7 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -83,13 +83,4 @@ void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - - /* Cache 8 MiB region below the top of RAM and 2 MiB above top of - * RAM to cover both cbmem as the TSEG region. - */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), - northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); } diff --git a/src/northbridge/intel/ironlake/memmap.c b/src/northbridge/intel/ironlake/memmap.c index 78fbae8..de34a38 100644 --- a/src/northbridge/intel/ironlake/memmap.c +++ b/src/northbridge/intel/ironlake/memmap.c @@ -35,13 +35,4 @@ void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB - * above top of the ram. This satisfies MTRR alignment requirement - * with different TSEG size configurations. - */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); } diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index c02cf35..fa1c873 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -87,14 +87,4 @@ void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - - /* - * Cache 8 MiB region below the top of RAM and 2 MiB above top of RAM to cover both - * CBMEM and the TSEG region. - */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), northbridge_get_tseg_size(), - MTRR_TYPE_WRBACK); } diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index f667544..0df49ed 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -67,22 +67,4 @@ void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram = (uintptr_t)cbmem_top(); - - /* - * Cache 8MiB below the top of ram. On sandybridge systems the top of - * RAM under 4GiB is the start of the TSEG region. It is required to - * be 8MiB aligned. Set this area as cacheable so it can be used later - * for ramstage before setting up the entire RAM as cacheable. - */ - postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK); - - /* - * Cache 8MiB at the top of ram. Top of RAM on sandybridge systems - * is where the TSEG region resides. However, it is not restricted - * to SMM mode until SMM has been relocated. By setting the region - * to cacheable it provides faster access when relocating the SMM - * handler as well as using the TSEG region for other purposes. - */ - postcar_frame_add_mtrr(pcf, top_of_ram, 8 * MiB, MTRR_TYPE_WRBACK); } diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index dced902..f942c09 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -85,14 +85,4 @@ void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - - /* Cache 8 MiB region below the top of RAM and 2 MiB above top of - * RAM to cover both cbmem as the TSEG region. - */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, - MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), - northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); } diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index b7731b0..f78d2f0 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -125,11 +125,6 @@ void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); - - /* Cache the TSEG region */ - postcar_enable_tseg_cache(pcf); } void SetMemParams(AMD_POST_PARAMS *PostParams) diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index aa8e890..5987e0b 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -29,13 +29,4 @@ void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB - * above top of the ram. This satisfies MTRR alignment requirement - * with different TSEG size configurations. - */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, - MTRR_TYPE_WRBACK); } diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index b467dc0..f0d7b76 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -47,13 +47,4 @@ void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB - * above top of the ram. This satisfies MTRR alignment requirement - * with different TSEG size configurations. - */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, - MTRR_TYPE_WRBACK); } diff --git a/src/soc/intel/common/block/systemagent/memmap.c b/src/soc/intel/common/block/systemagent/memmap.c index a67d050..0988f14 100644 --- a/src/soc/intel/common/block/systemagent/memmap.c +++ b/src/soc/intel/common/block/systemagent/memmap.c @@ -68,22 +68,6 @@ void fill_postcar_frame(struct postcar_frame *pcf) { - /* FSP does not seem to bother w.r.t. alignment when asked to place cbmem_top() */ - uintptr_t top_of_ram = ALIGN_UP((uintptr_t)cbmem_top(), 8 * MiB); - - /* - * We need to make sure ramstage will be run cached. At this - * point exact location of ramstage in cbmem is not known. - * Instruct postcar to cache 16 megs below cbmem top which is - * a safe bet to cover ramstage. - */ - printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - - postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); - - /* Cache the TSEG region */ - postcar_enable_tseg_cache(pcf); - /* Cache the extended BIOS region if it is supported */ fast_spi_cache_ext_bios_postcar(pcf); } diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index f607d0f..c417ee1 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -41,17 +41,4 @@ void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - - /* - * We need to make sure ramstage will be run cached. At this point exact - * location of ramstage in cbmem is not known. Instruct postcar to cache - * 16 megs under cbmem top which is a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, - MTRR_TYPE_WRBACK); - - /* Cache the TSEG region */ - postcar_enable_tseg_cache(pcf); } diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c index b640c2d..2586e7e 100644 --- a/src/soc/intel/xeon_sp/memmap.c +++ b/src/soc/intel/xeon_sp/memmap.c @@ -29,25 +29,6 @@ void fill_postcar_frame(struct postcar_frame *pcf) { - const uintptr_t top_of_ram = (uintptr_t)cbmem_top(); - uintptr_t cbmem_base; - size_t cbmem_size; - - /* Try account for the CBMEM region currently used and for future use */ - cbmem_get_region((void **)&cbmem_base, &cbmem_size); - printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - printk(BIOS_DEBUG, "cbmem base_ptr: 0x%lx, size: 0x%zx\n", cbmem_base, cbmem_size); - /* Assume 4MiB will be enough for future cbmem objects (FSP-S, ramstage, ...) */ - cbmem_base -= 4 * MiB; - cbmem_base = ALIGN_DOWN(cbmem_base, 4 * MiB); - - /* Align the top to make sure we don't use too many MTRR's */ - cbmem_size = ALIGN_UP(top_of_ram - cbmem_base, 4 * MiB); - - postcar_frame_add_mtrr(pcf, cbmem_base, cbmem_size, MTRR_TYPE_WRBACK); - /* Cache the TSEG region */ - if (CONFIG(TSEG_STAGE_CACHE)) - postcar_enable_tseg_cache(pcf); } #if !defined(__SIMPLE_DEVICE__) -- To view, visit https://review.coreboot.org/c/coreboot/+/63594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86c76c69fdb6a7930c2ba7dcd21fd9d368c680e0 Gerrit-Change-Number: 63594 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Damien Zammit Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]arch/x86: Tear down CAR in ramstage
by Arthur Heymans (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Arthur Heymans, Raul Rangel, Jonathan Zhang, Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Christian Walter, Morgan Jang, Fred Reitberger, Tim Chu, Felix Held. Hello build bot (Jenkins), Raul Rangel, Jonathan Zhang, Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Christian Walter, Morgan Jang, Tim Chu, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54301 to look at the new patch set (#14). Change subject: [WIP]arch/x86: Tear down CAR in ramstage ...................................................................... [WIP]arch/x86: Tear down CAR in ramstage Postcar is a 'full' stage to just run a few instructions to disable CAR and setup MTRR for ramstage. This takes up a lot of place in ROM. This functionality can be moved into ramstage. Notes: Typically no caching is set up around cbmem so the LZMA compressed ramstage is being decompressed in uncached memory, which is likely to be slow. Change-Id: I02e5017ab2b6a6fd30b37edad19165c2531c8fd1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/Kconfig M src/arch/x86/c_start.S M src/arch/x86/exit_car.S A src/arch/x86/exit_car.inc M src/arch/x86/postcar_loader.c M src/cpu/x86/mtrr/Makefile.inc M src/lib/program.ld M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-i440fx/Makefile.inc M src/soc/amd/common/block/cpu/car/Makefile.inc M src/soc/intel/common/block/cpu/Makefile.inc M src/soc/intel/xeon_sp/Kconfig 12 files changed, 56 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/54301/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/54301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02e5017ab2b6a6fd30b37edad19165c2531c8fd1 Gerrit-Change-Number: 54301 Gerrit-PatchSet: 14 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86/postcar: Set up postcar MTRR in C code
by Arthur Heymans (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Subrata Banik, Marshall Dawson, Kyösti Mälkki, Aaron Durbin, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Subrata Banik, Marshall Dawson, Kyösti Mälkki, Aaron Durbin, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54299 to look at the new patch set (#12). Change subject: arch/x86/postcar: Set up postcar MTRR in C code ...................................................................... arch/x86/postcar: Set up postcar MTRR in C code Setting up postcar MTRRs is done when invd is already called so there is no reason to do this in assembly anymore. TESTED on Qemu that MTRRs are properly set. Change-Id: I5ec10e84118197a04de0a5194336ef8bb049bba4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/exit_car.S M src/arch/x86/include/arch/romstage.h M src/arch/x86/postcar.c M src/arch/x86/postcar_loader.c M src/cpu/x86/mtrr/Makefile.inc M src/cpu/x86/mtrr/earlymtrr.c M src/drivers/amd/agesa/mtrr_fixme.c M src/drivers/amd/agesa/romstage.c M src/include/cpu/x86/mtrr.h M src/soc/amd/common/block/cpu/noncar/early_cache.c M src/soc/amd/stoneyridge/romstage.c 11 files changed, 87 insertions(+), 220 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/54299/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/54299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ec10e84118197a04de0a5194336ef8bb049bba4 Gerrit-Change-Number: 54299 Gerrit-PatchSet: 12 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: migrate GPMR driver
by Wonkyu Kim (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Subrata Banik, Ravishankar Sarawadi, Angel Pons, Nick Vaccaro, Tim Wawrzynczak. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63471 ) Change subject: soc/intel/common: migrate GPMR driver ...................................................................... Patch Set 10: (1 comment) File src/soc/intel/common/block/gpmr/gpmr.c: https://review.coreboot.org/c/coreboot/+/63471/comment/163c77ca_d1e5c49e PS9, Line 20: void gpmr_or32(uint16_t offset, uint32_t ordata) : { : return pcr_or32(PID_DMI, offset, ordata); : } > I would have harness GPMR driver with new APIs and marking APIs from static to non-static before sta […] I also tried to split GPMR API patch and other files which use GPMR APIs but The other file changes are dependencies fast_spi.c : updated api name enable_gpmr lpc_lib.c : SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR So, only files which does not have dependencies are tco.c and lockdown.c So, even we splite patch, we need to add fast_spi.c and lpc_lib.c togeter in first patch(GPMR api patch) and other files(tco.c and lockdown.c). So, I made one patch. WDYT? -- To view, visit https://review.coreboot.org/c/coreboot/+/63471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00ac667e8d3f2ccefd8d51a8150a989fc8e5c7e2 Gerrit-Change-Number: 63471 Gerrit-PatchSet: 10 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 20:19:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/nipperkin: Disable PSPP for WLAN
by Rob Barnes (Code Review) 12 Apr '22

12 Apr '22

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63593 ) Change subject: mb/google/nipperkin: Disable PSPP for WLAN ...................................................................... mb/google/nipperkin: Disable PSPP for WLAN Disable PSPP parameters for WLAN card on Nipperkin. This feature is causing S0ix resume hangs. BUG=b:227296841,b:228830362 BRANCH=guybrush TEST=Suspend stress test passes on Nipperkin Signed-off-by: Rob Barnes <robbarnes(a)google.com> Change-Id: I38f05b92ace4aba61163194a6a638915882b8871 --- M src/mainboard/google/guybrush/variants/nipperkin/variant.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/63593/1 diff --git a/src/mainboard/google/guybrush/variants/nipperkin/variant.c b/src/mainboard/google/guybrush/variants/nipperkin/variant.c index 204ec61..b10aadf 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/variant.c +++ b/src/mainboard/google/guybrush/variants/nipperkin/variant.c @@ -4,6 +4,7 @@ #include <boardid.h> #include <device/device.h> #include <soc/gpio.h> +#include <string.h> void variant_update_dxio_descriptors(fsp_dxio_descriptor *dxio_descriptors) { @@ -12,6 +13,9 @@ if (board_version >= 3) { dxio_descriptors[WLAN].link_aspm_L1_1 = true; dxio_descriptors[WLAN].link_aspm_L1_2 = true; + /* Disable PSPP */ + memset(dxio_descriptors[WLAN].port_params, 0, + sizeof(dxio_descriptors[WLAN].port_params)); } else { dxio_descriptors[WLAN].link_aspm_L1_1 = false; dxio_descriptors[WLAN].link_aspm_L1_2 = false; -- To view, visit https://review.coreboot.org/c/coreboot/+/63593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38f05b92ace4aba61163194a6a638915882b8871 Gerrit-Change-Number: 63593 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

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