coreboot-gerrit April 2022

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Change in coreboot[master]: soc/intel/cmn/xhci: Add function to reset the XHCI controller
by Tim Wawrzynczak (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Sridhar Siricilla, Nick Vaccaro, Eric Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63551 ) Change subject: soc/intel/cmn/xhci: Add function to reset the XHCI controller ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0dc0a64044f291893931726d26c08c8b964a3cc Gerrit-Change-Number: 63551 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 19:20:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/*/Kconfig: Remove SOC_AMD_COMMON_BLOCK_UCODE_SIZE
by Fred Reitberger (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63590 ) Change subject: soc/amd/*/Kconfig: Remove SOC_AMD_COMMON_BLOCK_UCODE_SIZE ...................................................................... soc/amd/*/Kconfig: Remove SOC_AMD_COMMON_BLOCK_UCODE_SIZE Remove unused UCODE_SIZE config options. The size of a microcode binary is determined by its header, so this option is not needed anymore. Change-Id: I7e94580ea038f1b6f866f08798e1edd8597ba5c9 Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/block/cpu/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/sabrina/Kconfig 4 files changed, 0 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/63590/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 8522d3f..58d034c 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -82,9 +82,6 @@ config ARCH_ALL_STAGES_X86 default n -config SOC_AMD_COMMON_BLOCK_UCODE_SIZE - default 5568 - config CHIPSET_DEVICETREE string default "soc/amd/cezanne/chipset.cb" diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index 7f50965..8d46f27 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -72,9 +72,3 @@ select SUPPORT_CPU_UCODE_IN_CBFS help Builds in support for loading uCode. - -config SOC_AMD_COMMON_BLOCK_UCODE_SIZE - int - depends on SOC_AMD_COMMON_BLOCK_UCODE - help - Defines the size of the uCode binary in bytes. diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index b005f9b..760cce5 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -79,9 +79,6 @@ config ARCH_ALL_STAGES_X86 default n -config SOC_AMD_COMMON_BLOCK_UCODE_SIZE - default 3200 - config CHIPSET_DEVICETREE string default "soc/amd/picasso/chipset.cb" diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index 6924ce4..20493bc 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -86,9 +86,6 @@ config ARCH_ALL_STAGES_X86 default n -config SOC_AMD_COMMON_BLOCK_UCODE_SIZE - default 3200 - config CHIPSET_DEVICETREE string default "soc/amd/sabrina/chipset.cb" -- To view, visit https://review.coreboot.org/c/coreboot/+/63590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e94580ea038f1b6f866f08798e1edd8597ba5c9 Gerrit-Change-Number: 63590 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/update_microcode: Make ucode update more generic
by Fred Reitberger (Code Review) 12 Apr '22

12 Apr '22

Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63589 ) Change subject: soc/amd/common/block/update_microcode: Make ucode update more generic ...................................................................... soc/amd/common/block/update_microcode: Make ucode update more generic Use microcode block headers to determine its size. This enables the use case where different sized microcode blocks can be packaged together in a single cbfs entry. Change-Id: I84a2480cf8274d53ffdab7864135c1bf001241e6 Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/common/block/cpu/update_microcode.c 1 file changed, 27 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/63589/1 diff --git a/src/soc/amd/common/block/cpu/update_microcode.c b/src/soc/amd/common/block/cpu/update_microcode.c index 33b244d..c1d4138 100644 --- a/src/soc/amd/common/block/cpu/update_microcode.c +++ b/src/soc/amd/common/block/cpu/update_microcode.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/cpu.h> -#include <stdint.h> +#include <types.h> #include <cpu/amd/microcode.h> #include <commonlib/helpers.h> #include <console/console.h> @@ -12,13 +12,13 @@ #define CPU_MICROCODE_BLOB_NAME "cpu_microcode_blob.bin" -_Static_assert(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE_SIZE > 0, - "SOC_AMD_COMMON_BLOCK_UCODE_SIZE is not set"); +#define CEZANNE_PROC_REV_ID 0xA500 -#define MPB_MAX_SIZE CONFIG_SOC_AMD_COMMON_BLOCK_UCODE_SIZE -#define MPB_DATA_OFFSET 32 +#define UCODE_SIZE_3200 3200 +#define UCODE_SIZE_5568 5568 +#define MPB_MAX_SIZE UCODE_SIZE_5568 /* this needs to be the largest UCODE size*/ -struct microcode { +struct microcode_hdr { uint32_t date_code; uint32_t patch_id; @@ -34,12 +34,24 @@ uint8_t chipset2_rev_id; uint8_t reserved2[4]; +} __packed; - uint8_t m_patch_data[MPB_MAX_SIZE-MPB_DATA_OFFSET]; +struct microcode { + struct microcode_hdr hdr; + uint8_t m_patch_data[MPB_MAX_SIZE-sizeof(struct microcode_hdr)]; } __packed; _Static_assert(sizeof(struct microcode) == MPB_MAX_SIZE, "microcode size is invalid"); +static size_t get_ucode_size_for_proc_rev_id(uint16_t processor_rev_id) +{ + // currently, only cezanne has a different ucode size + if (processor_rev_id == CEZANNE_PROC_REV_ID) + return UCODE_SIZE_5568; + + return UCODE_SIZE_3200; +} + static void apply_microcode_patch(const struct microcode *m) { uint32_t new_patch_id; @@ -51,12 +63,12 @@ wrmsr(MSR_PATCH_LOADER, msr); printk(BIOS_DEBUG, "microcode: patch id to apply = 0x%08x\n", - m->patch_id); + m->hdr.patch_id); msr = rdmsr(IA32_BIOS_SIGN_ID); new_patch_id = msr.lo; - if (new_patch_id == m->patch_id) + if (new_patch_id == m->hdr.patch_id) printk(BIOS_INFO, "microcode: being updated to patch id = 0x%08x succeeded\n", new_patch_id); else @@ -75,10 +87,14 @@ { uint16_t equivalent_processor_rev_id = get_equivalent_processor_rev_id(); const struct microcode *m; + uintptr_t addr = (uintptr_t)ucode; + const struct microcode *end = (const struct microcode *)((uintptr_t)ucode + ucode_len); - for (m = ucode; m < ucode + ucode_len / MPB_MAX_SIZE; m++) { - if (m->processor_rev_id == equivalent_processor_rev_id) + for (m = ucode; m < end; ) { + if (m->hdr.processor_rev_id == equivalent_processor_rev_id) return m; + addr += get_ucode_size_for_proc_rev_id(m->hdr.processor_rev_id); + m = (const struct microcode*)addr; } printk(BIOS_WARNING, "Failed to find microcode for processor rev: %hx.\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/63589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84a2480cf8274d53ffdab7864135c1bf001241e6 Gerrit-Change-Number: 63589 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/{sa, adl}: Add `finalize` operation for systemagent
by Subrata Banik (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Angel Pons, Arthur Heymans, Lean Sheng Tan, Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63518 ) Change subject: soc/intel/common/{sa, adl}: Add `finalize` operation for systemagent ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/systemagent/systemagent.c: https://review.coreboot.org/c/coreboot/+/63518/comment/c0b1755f_ac8ad4fa PS2, Line 337: skip = CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE), > is it harmful to attempt to lock the PAM registers twice? the attribute says RW/L so, next write won't have any impact. > i.e., does this need to be skipped only if the Kconfig is true or can we always send it? i.e., sa_final() would just be set to e.g. Incase FSP writes it then next write from coreboot doesn't have any value hence, thought of avoiding it. > > ``` > static void systemagent_final(struct device *dev) > { > sa_lock_pam(); > } > ``` > > also are there more steps to come here later? yes, you got me right, I'm planning to implement Intel FAS security register recommendation here for SA/MCH. similarly each common code block to implement CPU, PCH, SPI etc. recommendation so that way, we have good confidence about meeting Intel guideline for each program and if we need SoC override, we can also design accordingly. -- To view, visit https://review.coreboot.org/c/coreboot/+/63518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd464d2507393ed0c746eb1fbd10e36092ed5599 Gerrit-Change-Number: 63518 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 19:16:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/xhci: Add function to reset the XHCI controller
by Subrata Banik (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Sridhar Siricilla, Nick Vaccaro, Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63551 ) Change subject: soc/intel/cmn/xhci: Add function to reset the XHCI controller ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/xhci/xhci.c: https://review.coreboot.org/c/coreboot/+/63551/comment/79a5eab4_ea8953ea PS3, Line 15: : #define XHCI_USBCMD 0x80 : #define USBCMD_HCRST (1 << 1) > nit: align right side with tabs Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0dc0a64044f291893931726d26c08c8b964a3cc Gerrit-Change-Number: 63551 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 19:12:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Reset XHCI controller while preparing for S5
by Subrata Banik (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Sridhar Siricilla, Nick Vaccaro, Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63552 ) Change subject: mb/google/brya: Reset XHCI controller while preparing for S5 ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/smihandler.c: https://review.coreboot.org/c/coreboot/+/63552/comment/755b56f6_7c4d4cd6 PS3, Line 16: ACPI_S5 > did this also end up applying to S3? S3 is non-por for Chrome/Brya I believe, so we might don't need to bother adding xhci reset in S3 flow and there can be downside of XHCI controller getting reset during S3 entry as below: - suppose user is coping a file from USB to HDD or vice verse - expectation is upon S3 resume, the file transfer will continue from where it paused. but with XHCI controller is getting reset, the user previous state won't be preserved. -- To view, visit https://review.coreboot.org/c/coreboot/+/63552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf06a64f055a0cee3659b410652082f31e18e149 Gerrit-Change-Number: 63552 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 19:11:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in libgfxinit[master]: README: Fix hyphenations in markdown
by Jack Rosenthal (Code Review) 12 Apr '22

12 Apr '22

Jack Rosenthal has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/63588 ) Change subject: README: Fix hyphenations in markdown ...................................................................... README: Fix hyphenations in markdown These hyphenations do not show properly once the Markdown is rendered in (for example) Gitiles. Change-Id: Ie44b3d4c14215be6cc50692f0063139066751cbf --- M README.md 1 file changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/88/63588/1 diff --git a/README.md b/README.md index 5c54f0a..95ec37e 100644 --- a/README.md +++ b/README.md @@ -8,9 +8,9 @@ It can query and set up most kinds of displays based on their EDID information. You can, however, also specify particular mode lines. -*libgfxinit* is written in SPARK, an Ada subset with formal verifica- -tion aspects. Absence of runtime errors can be proved automatically -with SPARK GPL 2016. +*libgfxinit* is written in SPARK, an Ada subset with formal +verification aspects. Absence of runtime errors can be proved +automatically with SPARK GPL 2016. Building on Linux @@ -25,9 +25,9 @@ Grab the Sources ---------------- -You'll need *libhwbase* and *libgfxinit*. Best is to clone the reposi- -tories into a common parent directory (this way *libgfxinit* will know -where to find *libhwbase*). +You'll need *libhwbase* and *libgfxinit*. Best is to clone the +repositories into a common parent directory (this way *libgfxinit* +will know where to find *libhwbase*). $ mkdir gfxfun && cd gfxfun $ git clone https://review.coreboot.org/p/libhwbase.git @@ -61,8 +61,8 @@ Build libgfxinit/`gfx_test` --------------------------- -*libgfxinit* is configured and installed in the same manner as de- -scribed above. You will have to select a configuration matching your +*libgfxinit* is configured and installed in the same manner as +described above. You will have to select a configuration matching your hardware. The makefile knows an additional target `gfx_test` to build a small @@ -78,10 +78,10 @@ =========================== `gfx_test` sets up its own framebuffer in the *stolen memory*. It -backs any current framebuffer mapping and contents up first and re- -stores it before exiting. This works somehow even while the *i915* -driver is running. A wrapper script `gfxtest/gfx_test.sh` is pro- -vided to help with the setup. It switches to a text console first +backs any current framebuffer mapping and contents up first and +restores it before exiting. This works somehow even while the *i915* +driver is running. A wrapper script `gfxtest/gfx_test.sh` is +provided to help with the setup. It switches to a text console first and tries to unload the *i915* driver. But ignores failures to do so (it won't work if you still have any application running that uses the gfx driver, e.g. an X server). -- To view, visit https://review.coreboot.org/c/libgfxinit/+/63588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Ie44b3d4c14215be6cc50692f0063139066751cbf Gerrit-Change-Number: 63588 Gerrit-PatchSet: 1 Gerrit-Owner: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [HACK] Add an option to use ADL-S IOT FSP
by Tim Wawrzynczak (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Michał Żygowski. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63578 ) Change subject: [HACK] Add an option to use ADL-S IOT FSP ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > Question is if we can have a hack like this in the repo temporarily? Everything boils down to missin […] Can you get a commitment from them to update their FSP package? We were able to get that for the client FSP. -- To view, visit https://review.coreboot.org/c/coreboot/+/63578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97198b1faa3e3c57f4950b0d69df1e6c43d289c3 Gerrit-Change-Number: 63578 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 19:06:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask/variants/moli: update type-c setting in overridetree ...
by Tim Wawrzynczak (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: YH Lin, Zhuohao Lee, Raihow Shi, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63570 ) Change subject: mb/google/brask/variants/moli: update type-c setting in overridetree for moli ...................................................................... Patch Set 5: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63570/comment/9b1a9ab8_a990019e PS5, Line 7: for moli `for moli` is redundant, the summary already says `moli` earlier -- To view, visit https://review.coreboot.org/c/coreboot/+/63570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfd7b761496a110f34838abb0fd408b37d390ba2 Gerrit-Change-Number: 63570 Gerrit-PatchSet: 5 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 12 Apr 2022 19:05:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask/variants/moli: add delay time to rtd3-cold
by Tim Wawrzynczak (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: YH Lin, Paul Menzel, Zhuohao Lee, Raihow Shi, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63544 ) Change subject: mb/google/brask/variants/moli: add delay time to rtd3-cold ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63544/comment/383d4dbe_ba8ce8c5 PS6, Line 12: We checked power on sequence requires enable pin prior to reset pin, : so added delay to meet the sequence. : Based on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2. nit: remove line break between lines 11 and 12 OR add another line break between them (new paragraph) -- To view, visit https://review.coreboot.org/c/coreboot/+/63544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idecb1c89655c9b8b720c3c65efc77e06e6a8b300 Gerrit-Change-Number: 63544 Gerrit-PatchSet: 6 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 12 Apr 2022 19:04:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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