coreboot-gerrit April 2022

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Change in coreboot[master]: mb/google/nipperkin: Disable PSPP for WLAN
by Rob Barnes (Code Review) 12 Apr '22

12 Apr '22

Rob Barnes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/63592 ) Change subject: mb/google/nipperkin: Disable PSPP for WLAN ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/63592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19d3a11c251f8dc9ecca6a087adeef28dcda7ec0 Gerrit-Change-Number: 63592 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/nipperkin: Disable PSPP for WLAN
by Rob Barnes (Code Review) 12 Apr '22

12 Apr '22

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63592 ) Change subject: mb/google/nipperkin: Disable PSPP for WLAN ...................................................................... mb/google/nipperkin: Disable PSPP for WLAN Disable PSPP parameters for WLAN card on Nipperkin. This feature is causing S0ix resume hangs. BUG=b:227296841,b:228830362 BRANCH=guybrush TEST=Suspend stress test passes on Nipperkin Change-Id: I19d3a11c251f8dc9ecca6a087adeef28dcda7ec0 Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M 3rdparty/amd_blobs M 3rdparty/blobs M 3rdparty/intel-microcode M 3rdparty/libgfxinit M 3rdparty/libhwbase M src/mainboard/google/guybrush/variants/nipperkin/variant.c 6 files changed, 9 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/63592/1 diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index a069321..c3aa07a 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit a0693217d2fea9f3c05f6d96008c1ad301ed69e6 +Subproject commit c3aa07acc64a95c46d17799f4062f98acf40989d diff --git a/3rdparty/blobs b/3rdparty/blobs index 8c580e5..2c67522 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 8c580e55da92252fa665b5038b87100d0e076d23 +Subproject commit 2c67522aae7132c337d994e0ed48ba6d182df08a diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 115c3e4..ee319ae 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 115c3e4cdad6a9d84bf06e066162c5c546a9d2c3 +Subproject commit ee319ae7bc59e88b60142f40a9ec1b46656de4db diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index 1b04c51..f64ccae 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit 1b04c517b377468b3b470d38607fb539187391dd +Subproject commit f64ccae3ba02210a6f4309264d8e5b8e1af636a8 diff --git a/3rdparty/libhwbase b/3rdparty/libhwbase index fc2102f..9946827 160000 --- a/3rdparty/libhwbase +++ b/3rdparty/libhwbase @@ -1 +1 @@ -Subproject commit fc2102f560f25e0f2e5be91ec36646dcb69e6e1b +Subproject commit 9946827bbae199477cfcb68dcc5ed257aaa9ba7d diff --git a/src/mainboard/google/guybrush/variants/nipperkin/variant.c b/src/mainboard/google/guybrush/variants/nipperkin/variant.c index 204ec61..b10aadf 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/variant.c +++ b/src/mainboard/google/guybrush/variants/nipperkin/variant.c @@ -4,6 +4,7 @@ #include <boardid.h> #include <device/device.h> #include <soc/gpio.h> +#include <string.h> void variant_update_dxio_descriptors(fsp_dxio_descriptor *dxio_descriptors) { @@ -12,6 +13,9 @@ if (board_version >= 3) { dxio_descriptors[WLAN].link_aspm_L1_1 = true; dxio_descriptors[WLAN].link_aspm_L1_2 = true; + /* Disable PSPP */ + memset(dxio_descriptors[WLAN].port_params, 0, + sizeof(dxio_descriptors[WLAN].port_params)); } else { dxio_descriptors[WLAN].link_aspm_L1_1 = false; dxio_descriptors[WLAN].link_aspm_L1_2 = false; -- To view, visit https://review.coreboot.org/c/coreboot/+/63592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19d3a11c251f8dc9ecca6a087adeef28dcda7ec0 Gerrit-Change-Number: 63592 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/update_microcode: Make ucode update more generic
by Raul Rangel (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Fred Reitberger, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63589 ) Change subject: soc/amd/common/block/update_microcode: Make ucode update more generic ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/cpu/update_microcode.c: https://review.coreboot.org/c/coreboot/+/63589/comment/3f6ce4ae_1d19106a PS1, Line 49: CEZANNE_PROC_REV_ID I'm not a fan of having SoC specific code in common/. What's wrong with keeping CONFIG_SOC_AMD_COMMON_BLOCK_UCODE_SIZE? It's a config parameter for common code. -- To view, visit https://review.coreboot.org/c/coreboot/+/63589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84a2480cf8274d53ffdab7864135c1bf001241e6 Gerrit-Change-Number: 63589 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 12 Apr 2022 20:04:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot tables: Add PCIe info to coreboot table
by Julius Werner (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Arthur Heymans, Yu-Ping Wu, Jianjun Wang. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 ) Change subject: coreboot tables: Add PCIe info to coreboot table ...................................................................... Patch Set 13: (2 comments) File src/commonlib/include/commonlib/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/63251/comment/f7c8d184_37b624bf PS12, Line 151: lb_uint64_t ctrl_base; /* Base address of PCIe controller */ : lb_uint64_t config_base; /* Base address of Config space */ : uint32_t config_size; : lb_uint64_t atu_base; > Did you means to sort them by the variable type or length? He means move atu_base further up so that config_size is at the end. I don't think that's necessarily that important/useful though, since coreboot table entries themselves are only guaranteed to be 4-byte aligned. so even if the 8-byte values are aligned correctly inside the struct, there's about a 50/50 chance that the whole struct is misaligned and then they're all misaligned anyway. File src/lib/coreboot_table.c: https://review.coreboot.org/c/coreboot/+/63251/comment/76ed9180_b39035f9 PS11, Line 36: CB_ERR > I don't understand your point. […] Yeah, sounds like a good idea to me. -- To view, visit https://review.coreboot.org/c/coreboot/+/63251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Gerrit-Change-Number: 63251 Gerrit-PatchSet: 13 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 20:01:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: comment

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Change in libgfxinit[master]: README: Fix hyphenations in markdown
by Angel Pons (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Nico Huber, Jack Rosenthal. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/63588 ) Change subject: README: Fix hyphenations in markdown ...................................................................... Patch Set 1: Verified+1 Code-Review+1 -- To view, visit https://review.coreboot.org/c/libgfxinit/+/63588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Ie44b3d4c14215be6cc50692f0063139066751cbf Gerrit-Change-Number: 63588 Gerrit-PatchSet: 1 Gerrit-Owner: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-Comment-Date: Tue, 12 Apr 2022 19:59:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/postcar: Set up postcar MTRR in C code
by Arthur Heymans (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Subrata Banik, Marshall Dawson, Kyösti Mälkki, Aaron Durbin, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54299 ) Change subject: arch/x86/postcar: Set up postcar MTRR in C code ...................................................................... Patch Set 11: (3 comments) File src/arch/x86/postcar.c: https://review.coreboot.org/c/coreboot/+/54299/comment/a3d2e434_78f7d4ee PS11, Line 3: #include <cpu/x86/msr.h> > u can put this in order, rest looks good. Done File src/cpu/x86/mtrr/earlymtrr.c: https://review.coreboot.org/c/coreboot/+/54299/comment/83453310_ada2cb15 PS11, Line 126: for (int i = 0; i < ctx->max_var_mtrrs; i++) { : wrmsr(MTRR_PHYS_BASE(i), zero); : wrmsr(MTRR_PHYS_MASK(i), zero); : } > can't u use clear_all_var_mtrr() here ? Done https://review.coreboot.org/c/coreboot/+/54299/comment/b6eebce7_22e0ca31 PS11, Line 131: wrmsr(MTRR_PHYS_BASE(i), ctx->mtrr[i].base); : wrmsr(MTRR_PHYS_MASK(i), ctx->mtrr[i].mask); > set_var_mtrr() may be ? That would be an option but then I have to rewrite the postcar setup to use size instead of mask. Also romstage already made sure that base and mask are correct so there is no need for the checking in set_var_mtrr. I'd think this is ok. -- To view, visit https://review.coreboot.org/c/coreboot/+/54299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ec10e84118197a04de0a5194336ef8bb049bba4 Gerrit-Change-Number: 54299 Gerrit-PatchSet: 11 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 12 Apr 2022 19:56:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mb/google,intel: Split chromeos.c files
by Kyösti Mälkki (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Tim Wawrzynczak, Nick Vaccaro, Julius Werner, Fred Reitberger, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59011 ) Change subject: [WIP] mb/google,intel: Split chromeos.c files ...................................................................... Patch Set 9: (1 comment) Patchset: PS9: > Do we have to split all these files up? I feel like GPIO setup and filling out the GPIO table belong […] At the moment reply on patchset 6 unresolved comment would be most valuable. This is more or less direct continuation on the previous works strictly restricting <vendorcode/google/chromeos.h> to where it is really needed, late ramstage. And making sure features on VBOOT or TPM do not accidentally be implemented under CONFIG(CHROMEOS). I think I'll be able to present this better later. -- To view, visit https://review.coreboot.org/c/coreboot/+/59011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71a02c5fa1b256316b86b673660bf22dfd284f7f Gerrit-Change-Number: 59011 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 12 Apr 2022 19:54:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot_tables: Replace 'struct lb_uint64' with lb_uint64_t
by Julius Werner (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Hung-Te Lin, Jakub Czapiga, Arthur Heymans, Jianjun Wang. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63494 ) Change subject: coreboot_tables: Replace 'struct lb_uint64' with lb_uint64_t ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Sorry, forgot that earlier... but we should do the same thing on the libpayload side as well. (The struct cb_uint64 in libpayload should technically be compatible to the lb_uint64_t in coreboot on little-endian systems, but it's still not exactly clean to just rely on that.) In fact, since we now have commonlib/bsd accessible in libpayload, this would probably be a good opportunity to just combine the two separate definitions of these tables into one now. -- To view, visit https://review.coreboot.org/c/coreboot/+/63494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6b037e4403a8000625f4a5fb8d20311fe76200a Gerrit-Change-Number: 63494 Gerrit-PatchSet: 5 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 19:47:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Add an option to LZ4 compress postcar
by Arthur Heymans (Code Review) 12 Apr '22

12 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63591 ) Change subject: arch/x86: Add an option to LZ4 compress postcar ...................................................................... arch/x86: Add an option to LZ4 compress postcar The reason for selecting LZ4 over LZMA is that LZ4 has a very low stack requirement in comparison with LZMA which is a better idea for when operating in CAR. Other compression methods might be added later if platforms have enough stack in CAR for it. The LZ4 decompressor was already linked in romstage. Change-Id: Ic64ba097bfe2f983a219479f78b50264d7a2e380 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig M src/arch/x86/Makefile.inc 2 files changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/63591/1 diff --git a/src/Kconfig b/src/Kconfig index d57ce90..55db936 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -159,6 +159,16 @@ help Compress ramstage to save memory in the flash image. +config COMPRESS_POSTCAR + bool "Compress postcar with LZ4" + depends on POSTCAR_STAGE + # Default value set at the end of the file + help + Compress postcar with LZ4 to save flash space and speed up boot, + since the time for reading the image from SPI (and in the vboot + case verifying it) is usually much greater than the time spent + decompressing. + config COMPRESS_PRERAM_STAGES bool "Compress romstage and verstage with LZ4" depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE) @@ -1343,6 +1353,9 @@ config COMPRESS_RAMSTAGE default y if !UNCOMPRESSED_RAMSTAGE +config COMPRESS_POSTCAR + default y if X86_CACHED_CBMEM_INIT + config COMPRESS_PRERAM_STAGES depends on !ARCH_X86 default y diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 458bcc6..9709449 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -213,11 +213,16 @@ $(objcbfs)/postcar.elf: $(objcbfs)/postcar.debug.rmod cp $< $@ +CBFS_POSTCAR_COMPRESS_FLAG := none +ifeq ($(CONFIG_COMPRESS_POSTCAR),y) +CBFS_POSTCAR_COMPRESS_FLAG := lz4 +endif + # Add postcar to CBFS cbfs-files-$(CONFIG_POSTCAR_STAGE) += $(CONFIG_CBFS_PREFIX)/postcar $(CONFIG_CBFS_PREFIX)/postcar-file := $(objcbfs)/postcar.elf $(CONFIG_CBFS_PREFIX)/postcar-type := stage -$(CONFIG_CBFS_PREFIX)/postcar-compression := none +$(CONFIG_CBFS_PREFIX)/postcar-compression := $(CBFS_POSTCAR_COMPRESS_FLAG) ############################################################################### # ramstage -- To view, visit https://review.coreboot.org/c/coreboot/+/63591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic64ba097bfe2f983a219479f78b50264d7a2e380 Gerrit-Change-Number: 63591 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]soc/intel/xeon_sp: Cache cbmem and compress postcar
by Arthur Heymans (Code Review) 12 Apr '22

12 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48120 ) Change subject: [WIP]soc/intel/xeon_sp: Cache cbmem and compress postcar ...................................................................... [WIP]soc/intel/xeon_sp: Cache cbmem and compress postcar Tested on ocp/deltalake. Change-Id: Ibd38670a7486363795fe502c3abee79c39036cf8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp2_0/memory_init.c M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/Makefile.inc 3 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/48120/1 diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 27e34fe..f330462 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -18,6 +18,7 @@ #include <string.h> #include <symbols.h> #include <timestamp.h> +#include <cpu/x86/mtrr.h> #include <security/vboot/vboot_common.h> #include <security/tpm/tspi.h> #include <vb2_api.h> @@ -76,6 +77,8 @@ (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY)) die("Failed to accommodate FSP reserved memory request!\n"); + setup_romstage_wb_cbmem_cache(128 * MiB); + save_memory_training_data(s3wake, fsp_version); /* Create romstage handof information */ diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 2028a5e..894dac1 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -66,6 +66,8 @@ select HAVE_SMI_HANDLER select X86_SMM_LOADER_VERSION2 select REG_SCRIPT + select X86_CLFLUSH_CAR + select ROMSTAGE_CBMEM_CACHED config MAINBOARD_USES_FSP2_0 bool diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index cfda7d5..a3ee5af 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -8,6 +8,7 @@ bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c memmap.c romstage-y += ../../../cpu/intel/car/romstage.c +subdirs-y += ../../../cpu/x86/cache ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c ramstage.c chip_common.c ramstage-y += memmap.c pch.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c -- To view, visit https://review.coreboot.org/c/coreboot/+/48120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd38670a7486363795fe502c3abee79c39036cf8 Gerrit-Change-Number: 48120 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit April 2022