Change in coreboot[master]: [WIP]soc/intel/xeon_sp: Cache cbmem and compress postcar

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48120 )

Change subject: [WIP]soc/intel/xeon_sp: Cache cbmem and compress postcar
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[WIP]soc/intel/xeon_sp: Cache cbmem and compress postcar

Tested on ocp/deltalake.

Change-Id: Ibd38670a7486363795fe502c3abee79c39036cf8
Signed-off-by: Arthur Heymans 
---
M src/drivers/intel/fsp2_0/memory_init.c
M src/soc/intel/xeon_sp/Kconfig
M src/soc/intel/xeon_sp/Makefile.inc
3 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/48120/1

diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index 27e34fe..f330462 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -18,6 +18,7 @@
 #include <string.h>
 #include <symbols.h>
 #include <timestamp.h>
+#include <cpu/x86/mtrr.h>
 #include <security/vboot/vboot_common.h>
 #include <security/tpm/tspi.h>
 #include <vb2_api.h>
@@ -76,6 +77,8 @@
    	(uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY))
    	die("Failed to accommodate FSP reserved memory request!\n");

+	setup_romstage_wb_cbmem_cache(128  * MiB);
+
    save_memory_training_data(s3wake, fsp_version);

/* Create romstage handof information */
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index 2028a5e..894dac1 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -66,6 +66,8 @@
    select HAVE_SMI_HANDLER
    select X86_SMM_LOADER_VERSION2
    select REG_SCRIPT
+	select X86_CLFLUSH_CAR
+	select ROMSTAGE_CBMEM_CACHED

config MAINBOARD_USES_FSP2_0
      bool
diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc
index cfda7d5..a3ee5af 100644
--- a/src/soc/intel/xeon_sp/Makefile.inc
+++ b/src/soc/intel/xeon_sp/Makefile.inc
@@ -8,6 +8,7 @@
 bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c
 romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c memmap.c
 romstage-y += ../../../cpu/intel/car/romstage.c
+subdirs-y += ../../../cpu/x86/cache
 ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c ramstage.c chip_common.c
 ramstage-y += memmap.c pch.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c