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I'd like you to reexamine a change. Please visit
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Change subject: cpu/x86/smm_module_loader: Add a convenient ss_top
......................................................................
cpu/x86/smm_module_loader: Add a convenient ss_top
We don't want to keep track of the real smm size all the time.
As a bonus now ss_start is now really the start of the save state
instead of top - MAX(stub_size, save state size).
Change-Id: I0981022e6c0df110d4a342ff06b1a3332911e2b7
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/x86/smm/smm_module_loader.c
1 file changed, 7 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/63477/9
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Hello build bot (Jenkins), Edward O'Callaghan,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#9).
Change subject: cpu/x86/smm_module_loader.c: Rewrite setup
......................................................................
cpu/x86/smm_module_loader.c: Rewrite setup
This code is much easier to read of one does not have to keep track of
mutable variables.
This also fixes the alignment code on the TSEG smihandler setup code.
It was aligning the code upwards instead of downwards which would case
it to encroach a part of the save state.
Change-Id: I310a232ced2ab15064bff99a39a26f745239f6b9
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/x86/smm/smm_module_loader.c
1 file changed, 126 insertions(+), 173 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/63475/9
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63476 )
Change subject: cpu/x86/smm: Drop 'entry' struct element
......................................................................
Patch Set 8: Code-Review+2
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Change subject: util/amdfwtool: Maintain one copy of PSP Level2 entries
......................................................................
Patch Set 2:
(1 comment)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/63509/comment/6cd13d06_c9eb0d6d
PS2, Line 1855: /* B is same as above directories for A */
: /* Skip creating pspdir2_b here to save flash space. Related
: * biosdir2_b will be skipped automatically. */
looks like this comment is wrong, so it would be good to fix this too
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Change subject: mb/google/brya: Reset XHCI controller while preparing for S5
......................................................................
Patch Set 4:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63552/comment/af74f763_53043c45
PS3, Line 13: resume
> `poweron`
Ack
https://review.coreboot.org/c/coreboot/+/63552/comment/1e2eec03_a6a4ed6d
PS3, Line 15: resume
> `poweron`
Ack
https://review.coreboot.org/c/coreboot/+/63552/comment/c8877b8b_e336e486
PS3, Line 31: resuming
> `powering on`
Ack
https://review.coreboot.org/c/coreboot/+/63552/comment/fbf2ea21_d5fe5b66
PS3, Line 33: Upon resume
> `During poweron`
Ack
https://review.coreboot.org/c/coreboot/+/63552/comment/19c6268f_ef81b0b8
PS3, Line 35: PMC tries to send the IPC command, finally, results into timeout.
> `which results in a timeout. […]
Ack
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Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Sridhar Siricilla, Nick Vaccaro, Eric Lai,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya: Reset XHCI controller while preparing for S5
......................................................................
mb/google/brya: Reset XHCI controller while preparing for S5
This patch calls into `xhci_host_reset()` function to perform XHCI
controller reset.
Without this patch the PMC IPC timeout issue is seen while sending the
USB-C (0xA7) command during poweron from S5 (S5->S4->S3->S0).
On Brya variants, poweron from S5 state results in PMC error while
sending PMC IPC (0xA7) to USB-C active ports, log here:
localhost ~ # cbmem -c | grep ERROR
[ERROR] Â PMC IPC timeout after 1000 ms
[ERROR] Â PMC IPC command 0x200a7 failed
[ERROR] Â pmc_send_ipc_cmd failed
[ERROR] Â Failed to setup port:0 to initial state
[ERROR] Â PMC IPC timeout after 1000 ms
[ERROR] Â PMC IPC command 0x200a7 failed
[ERROR] Â pmc_send_ipc_cmd failed
[ERROR] Â Failed to setup port:1 to initial state
[ERROR] Â PMC IPC timeout after 1000 ms
[ERROR] Â PMC IPC command 0x20a0 failed
This problem is not seen while powering on from G3 (G3->S5->S4->S3->S0).
During poweron the state of USB ports are not the same between S5 and G3
and it appears that the active USB port still is in U3 (suspend) while
PMC tries to send the IPC command, which results in a timeout.
This patch utilises the S5 SMI handler to reset the XHCI controller
using `xhci_host_reset()` prior entering into the S5, it helps to
restore the port state to active hence, no PMC timeout is seen with
this code change.
BUG=b:227289581
TEST=No PMC timeout is observed while sending USB-C PMC command (0xA7)
during resume from S5.
Total Time: 1,045,855
localhost ~ # cbmem -c | grep ERROR
No PMC timeout error is observed with this CL.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ibf06a64f055a0cee3659b410652082f31e18e149
---
M src/mainboard/google/brya/smihandler.c
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/63552/4
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63593 )
Change subject: mb/google/nipperkin: Disable PSPP for WLAN
......................................................................
Patch Set 3: Code-Review+2
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Change subject: mb/google/nipperkin: Disable PSPP for WLAN
......................................................................
Patch Set 3:
(3 comments)
File src/mainboard/google/guybrush/variants/nipperkin/variant.c:
https://review.coreboot.org/c/coreboot/+/63593/comment/f326bdce_86c81773
PS1, Line 16: Disable
> Can you add a b/ explaining why?
Done.
https://review.coreboot.org/c/coreboot/+/63593/comment/937a73cb_59fcaa89
PS1, Line 17: memset(dxio_descriptors[WLAN].port_params, 0,
> should this only be done for board_version >= 3 or for all board revisions? […]
We do not fully understand the root cause of the failure, so I'm hesitant to apply the change to older board versions without more testing, especially since older board versions disable L1SS.
I'm not convinced loop is better here, but I'm open to arguments.
https://review.coreboot.org/c/coreboot/+/63593/comment/2302e8fa_2816d467
PS1, Line 18: sizeof(dxio_descriptors[WLAN].port_params));
> Do we also need it for Dewatt since it is not far behind?
TBD after testing. DeWatt uses a different WiFi card.
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