coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/skyrim/var/skyrim: Add supported memory parts
by Jon Murphy (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Raul Rangel, Karthik Ramasubramanian. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63599 ) Change subject: mb/google/skyrim/var/skyrim: Add supported memory parts ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63599 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id87e79f5d6187d57d74487841c09aa309f1450b4 Gerrit-Change-Number: 63599 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 23:47:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/skyrim: Inject SPDs into APCB
by Jon Murphy (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Raul Rangel, Karthik Ramasubramanian. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63600 ) Change subject: mb/google/skyrim: Inject SPDs into APCB ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b3f6f248d54681c6f55c00660d1f2988ae906ba Gerrit-Change-Number: 63600 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 23:47:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton_ns: enable Denverton to use common systemagent code
by Angel Pons (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Jeff Daly, Mariusz Szafrański, Suresh Bellampalli, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61015 ) Change subject: soc/intel/denverton_ns: enable Denverton to use common systemagent code ...................................................................... Patch Set 10: Code-Review+1 (11 comments) File src/soc/intel/denverton_ns/chip.h: https://review.coreboot.org/c/coreboot/+/61015/comment/2fe64739_6a53b7c5 PS10, Line 67: uint32_t Why `uint32_t`? `bool` should suffice File src/soc/intel/denverton_ns/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/61015/comment/0b8a5fbc_92228737 PS10, Line 15: /* no DMI for DNV */ : #define DMI_BASE_ADDRESS 0 : #define DMI_BASE_SIZE 0 : : /* no EP windows for DNV */ : #define EP_BASE_ADDRESS 0 : #define EP_BASE_SIZE 0 : : /* no EDRAM for DNV */ : #define EDRAM_BASE_ADDRESS 0 : #define EDDRAM_BASE_SIZE 0 : : /* no GDXC for DNV */ : #define GDXC_BASE_ADDRESS 0 : #define GDXC_BASE_SIZE 0 : : /* no iGFX for DNV */ : #define GFXVT_BASE_ADDRESS 0 : #define GFXVT_BASE_SIZE 0 Does common code need these defines? If it doesn't, I would drop them. https://review.coreboot.org/c/coreboot/+/61015/comment/2c8abb9e_48bfcff6 PS10, Line 53: #define MCH_BASE_ADDRESS 0xfed10000 : #define MCH_BASE_SIZE 0x8000 Same as lines 12-13 https://review.coreboot.org/c/coreboot/+/61015/comment/85835471_e2693850 PS10, Line 56: #define HPET_BASE_ADDRESS 0xfed00000 This is now defined in a central location, src/arch/x86/include/arch/hpet.h https://review.coreboot.org/c/coreboot/+/61015/comment/c9bb586c_54f1754a PS10, Line 67: #define DEFAULT_HPET_ADDR CONFIG_HPET_ADDRESS The Kconfig was removed, I'd drop this. File src/soc/intel/denverton_ns/include/soc/nvs.h: PS10: Most of the NVS values only make sense on "client" platforms. Also, you would need to update the definition in the .asl file accordingly File src/soc/intel/denverton_ns/include/soc/systemagent.h: https://review.coreboot.org/c/coreboot/+/61015/comment/935dc307_def975f2 PS10, Line 25: #if 0 : #define TOUUD_LO 0xa8 /* Top of Upper Usable DRAM - Low */ : #define MASK_TOUUD_LO 0xFFF00000 : #define TOUUD_HI 0xac /* Top of Upper Usable DRAM - High */ : #define MASK_TOUUD_HI 0x0000007F : #define TOUUD TOUUD_LO /* Top of Upper Usable DRAM */ : #define MASK_TOUUD 0x7FFFF00000 : #endif Remove? https://review.coreboot.org/c/coreboot/+/61015/comment/7ef606bd_7966b3cb PS10, Line 55: /* DNV has different offsets than other SoCs */ : #ifdef MCH_PKG_POWER_LIMIT_LO : #undef MCH_PKG_POWER_LIMIT_LO : #define MCH_PKG_POWER_LIMIT_LO 0x70a8 : #undef MCH_PKG_POWER_LIMIT_HI : #define MCH_PKG_POWER_LIMIT_HI 0x70ac : #undef MCH_DDR_POWER_LIMIT_LO : #define MCH_DDR_POWER_LIMIT_LO 0x7040 : #undef MCH_DDR_POWER_LIMIT_HI : #define MCH_DDR_POWER_LIMIT_HI 0x7048 : #endif These defines are only used in `src/soc/intel/common/block/power_limit/power_limit.c`. The code is guarded by `SOC_INTEL_COMMON_BLOCK_POWER_LIMIT`. https://review.coreboot.org/c/coreboot/+/61015/comment/8e488b22_48208cf7 PS10, Line 69: static const struct sa_mmio_descriptor soc_vtd_mmio_descriptor = { : VTDBAR, : VTD_BASE_ADDRESS, : VTD_BASE_SIZE, : "VTDBAR" : }; This declaration should be inside a C file (e.g. denverton_ns/systemagent.c), not a header. File src/soc/intel/denverton_ns/systemagent.c: https://review.coreboot.org/c/coreboot/+/61015/comment/f3164259_1b7a2619 PS10, Line 64: /* Enable BIOS Reset CPl */ This is quite redundant, no? https://review.coreboot.org/c/coreboot/+/61015/comment/1ea16b22_7d71d6e1 PS10, Line 68: BGSM Weird that DNV-NS has BGSM but doesn't have an iGPU. -- To view, visit https://review.coreboot.org/c/coreboot/+/61015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39df1f0889c1c4ac6f2b3c25ccb7817e4492f446 Gerrit-Change-Number: 61015 Gerrit-PatchSet: 10 Gerrit-Owner: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 12 Apr 2022 23:45:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/amdfwtool: Maintain one copy of PSP Level2 entries
by Karthik Ramasubramanian (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Bao Zheng, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63509 ) Change subject: util/amdfwtool: Maintain one copy of PSP Level2 entries ...................................................................... Patch Set 3: (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/63509/comment/bb2d99f0_d241df28 PS2, Line 1855: /* B is same as above directories for A */ : /* Skip creating pspdir2_b here to save flash space. Related : * biosdir2_b will be skipped automatically. */ > looks like this comment is wrong, so it would be good to fix this too Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06eef8e14b9c14db1d02b621c2f7207188d86326 Gerrit-Change-Number: 63509 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Avinash Alevoor Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-CC: Mohan Viswanathan Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 12 Apr 2022 23:42:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: util/amdfwtool: Maintain one copy of PSP Level2 entries
by Karthik Ramasubramanian (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Bao Zheng, Karthik Ramasubramanian. Hello build bot (Jenkins), Bao Zheng, Raul Rangel, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63509 to look at the new patch set (#3). Change subject: util/amdfwtool: Maintain one copy of PSP Level2 entries ...................................................................... util/amdfwtool: Maintain one copy of PSP Level2 entries AMDFWtool maintains 2 copies of PSP Level2 entries - one in primary slot A (Type 0x48) and another in backup slot B (Type 0x4A). On boards which use VBOOT with 2 RW firmware slots, maintaining 2 copies of PSP Level2 entries in each FW slot is redundant and space-consuming. Introduce option to maintain only one copy of PSP Level2 entries and point to it from both slots A & B. BUG=None TEST=Build and boot to OS in Skyrim. Ensure that only one copy is added to each FW slot. This achieved a space saving of 1.5 MB in each FW slot. Before: apu/amdfw 0x415fc0 raw 3043328 none After: apu/amdfw 0x415fc0 raw 1556480 none Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I06eef8e14b9c14db1d02b621c2f7207188d86326 --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 2 files changed, 20 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/63509/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06eef8e14b9c14db1d02b621c2f7207188d86326 Gerrit-Change-Number: 63509 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Avinash Alevoor Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-CC: Mohan Viswanathan Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: device/i2c_bus: Add detect function pointer in i2c_bus_ops
by Julius Werner (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Subrata Banik, Matt DeVillier, Tim Wawrzynczak, Karthik Ramasubramanian. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63209 ) Change subject: device/i2c_bus: Add detect function pointer in i2c_bus_ops ...................................................................... Patch Set 3: (1 comment) File src/include/device/i2c_bus.h: https://review.coreboot.org/c/coreboot/+/63209/comment/d57cc860_34b64376 PS3, Line 14: bool (*detect)(struct device *dev, unsigned int addr); > I think what Julius might have been getting at is should we just use the i2c_simple interface instea […] I meant we shouldn't have a separate detect() function pointer here. That still requires every driver to implement it even if they all just implement it by forwarding to their transfer() implementation. I'm saying we should tie those together at the generic level so that each individual driver doesn't have to worry about it. I'm not saying necessarily that you need to use the i2c_simple interface instead, although that's one option (and it the detect is generally useful it's probably a good idea to at least offer it for the i2c_simple interface as well). But you can still have a detect specifically for the bus_operations interface but just writing a helper function like this: bool i2c_dev_detect(struct device *dev, unsigned int addr) { struct i2c_msg seg = { .flags = 0, .slave = addr, .buf = NULL, .len = 0 }; return dev->ops->ops_i2c_bus->transfer(dev, &seg, 1) == 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/63209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8ddfb187eabec966c253b6cc8526491c99151fc Gerrit-Change-Number: 63209 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 23:38:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/skyrim: Inject SPDs into APCB
by Robert Zieba (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Raul Rangel, Jon Murphy, Karthik Ramasubramanian. Robert Zieba has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63600 ) Change subject: mb/google/skyrim: Inject SPDs into APCB ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/mainboard/google/skyrim/Makefile.inc: https://review.coreboot.org/c/coreboot/+/63600/comment/ad8cccc8_7ba421ef PS1, Line 31: --spd_magic '2311130E' If possible you should mention where this value is coming from. -- To view, visit https://review.coreboot.org/c/coreboot/+/63600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b3f6f248d54681c6f55c00660d1f2988ae906ba Gerrit-Change-Number: 63600 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 23:34:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/apcb/apcb_v3_edit.py: Edit APCB based on different SPD magic
by Robert Zieba (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Raul Rangel, Jon Murphy, Rob Barnes, Karthik Ramasubramanian. Robert Zieba has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63598 ) Change subject: util/apcb/apcb_v3_edit.py: Edit APCB based on different SPD magic ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e96c89e4e5ce8e0567a17bf7685b69080fa1708 Gerrit-Change-Number: 63598 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 23:32:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/skyrim/var/skyrim: Add supported memory parts
by Robert Zieba (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Raul Rangel, Jon Murphy, Karthik Ramasubramanian. Robert Zieba has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63599 ) Change subject: mb/google/skyrim/var/skyrim: Add supported memory parts ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63599 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id87e79f5d6187d57d74487841c09aa309f1450b4 Gerrit-Change-Number: 63599 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 23:31:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton_ns: enable Denverton to use common SoC SPI code
by Angel Pons (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Jeff Daly, Suresh Bellampalli, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61014 ) Change subject: soc/intel/denverton_ns: enable Denverton to use common SoC SPI code ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1d57c6b348adb934785b0e2bec4e856f0bf8d77 Gerrit-Change-Number: 61014 Gerrit-PatchSet: 10 Gerrit-Owner: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 12 Apr 2022 23:30:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2022