coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

1 participants
5879 discussions

Change in coreboot[master]: device/i2c_bus: Add detect function pointer in i2c_bus_ops
by Tim Wawrzynczak (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Subrata Banik, Matt DeVillier, Julius Werner, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63209 ) Change subject: device/i2c_bus: Add detect function pointer in i2c_bus_ops ...................................................................... Patch Set 3: (1 comment) File src/include/device/i2c_bus.h: https://review.coreboot.org/c/coreboot/+/63209/comment/254d6e22_5064199c PS3, Line 14: bool (*detect)(struct device *dev, unsigned int addr); I think what Julius might have been getting at is should we just use the i2c_simple interface instead? e.g. ``` static inline int i2c_write_detect(unsigned int bus, uint8_t addr) { struct i2c_msg seg; seg.flags = 0; seg.slave = addr; seg.buf = NULL; seg.len = 0; return i2c_transfer(bus, &seg, 1); } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/63209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8ddfb187eabec966c253b6cc8526491c99151fc Gerrit-Change-Number: 63209 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 22:46:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/i2c/dw_i2c: Adjust to handle 0-byte transfers
by Tim Wawrzynczak (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Matt DeVillier. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63561 ) Change subject: drivers/i2c/dw_i2c: Adjust to handle 0-byte transfers ...................................................................... Patch Set 1: (1 comment) File src/drivers/i2c/designware/dw_i2c.c: https://review.coreboot.org/c/coreboot/+/63561/comment/a89977ac_938c5a95 PS1, Line 377: if (segments->len == 0) This implies (count == 1) as well right? should it be checked? -- To view, visit https://review.coreboot.org/c/coreboot/+/63561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I518e849f4c476c264a1464886b1853af66c0b29d Gerrit-Change-Number: 63561 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 22:44:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: register generic LPC resources
by 9elements QA (Code Review) 13 Apr '22

13 Apr '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63341 ) Change subject: soc/intel/common: register generic LPC resources ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/100645 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/100644 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/100643 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/100642 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/100641 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/100640 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/100639 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/100638 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/100637 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/100636 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/100635 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/100634 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/100633 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/100632 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/100631 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/100630 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/63341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f45b38498390016f841ab1d70c8438496dc857e Gerrit-Change-Number: 63341 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 22:41:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Update amd_blobs submodule to upstream master
by Martin Roth (Code Review) 13 Apr '22

13 Apr '22

Martin Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/60817 ) Change subject: Update amd_blobs submodule to upstream master ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/60817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I392c6abc4c3a44ba41fd75a3bfb6817482e90fb8 Gerrit-Change-Number: 60817 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: lib/hardwaremain.c: Move creating ACPI structs to bootstate hooks
by Arthur Heymans (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Lance Zhao, Tim Wawrzynczak, Angel Pons, Kyösti Mälkki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63414 ) Change subject: lib/hardwaremain.c: Move creating ACPI structs to bootstate hooks ...................................................................... Patch Set 3: (1 comment) File src/vendorcode/google/chromeos/gnvs.c: https://review.coreboot.org/c/coreboot/+/63414/comment/703cc0bd_81bda88b PS3, Line 61: BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, chromeos_init_chromeos_acpi, NULL); > I think I agree with you, I don't see any links/dependency between them any longer now that they are in separate CBMEM entries. They don't depend on each other so that's fine. -- To view, visit https://review.coreboot.org/c/coreboot/+/63414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I613b927b9a193fc076ffb1b2a40c617965ce2645 Gerrit-Change-Number: 63414 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 22:30:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: implement ioc driver
by Wonkyu Kim (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Jamie Ryu, Subrata Banik, Ethan Tsao, Ravishankar Sarawadi, Paul Menzel, Tim Wawrzynczak, Angel Pons, Nick Vaccaro. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63198 ) Change subject: soc/intel/common: implement ioc driver ...................................................................... Patch Set 13: (11 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63198/comment/d7ee9402_af86a5b0 PS11, Line 11: https://github.com/otcshare/CCG-MTL-Generic-PSS/blob/master/ > IMO, starting with MTL, the GPMR access registers are migrated to IOC (I/O cache) instead DMI over PCR in previous generation, hence, added the required support in IA common code so that the SoC can select the required interface while programming the GPMR register DMI can be still used using PCH case. MTL-S still using PCH while MTL-M&P are not using PCH. IOC is used for die to die communication while DMI is used for PCH interface. > @will, don't refer which is not in public in commit msg, you can explain the design change in SoC, you don't need to refer to UEFI BIOS code. >I'll remove this in commit message. As there is no external document which has all offsets for IOC, I provided as reference. https://review.coreboot.org/c/coreboot/+/63198/comment/840da6b4_63fe3729 PS11, Line 14: TEST=Build and boot to OS for TGL and MTL > On what boards exactly? TGL RVP and MTL PSS(pre-Silicon system). Will add info in commit message. File src/soc/intel/common/block/gpmr/gpmr.c: https://review.coreboot.org/c/coreboot/+/63198/comment/fc474b55_fb048557 PS12, Line 27: uint32_t data32; : : data32 = gpmr_read32(offset); : data32 |= ordata; : gpmr_write32(offset, data32); > you mean ioc_or32? Ack File src/soc/intel/common/block/ioc/Kconfig: https://review.coreboot.org/c/coreboot/+/63198/comment/9283a5e1_ccb71ed1 PS5, Line 1: SOC_INTEL_COMMON_BLOCK_IOC > > Do we have KConfig for this? […] use SOC_INTEL_COMMON_BLOCK_SA File src/soc/intel/common/block/ioc/Kconfig: https://review.coreboot.org/c/coreboot/+/63198/comment/d26996ba_7afa103b PS11, Line 4: Intel Processor common IO Cache (IOC) > Please elaborate, what it does, and since what generation it’s available. Ack https://review.coreboot.org/c/coreboot/+/63198/comment/860c756c_4de9ab42 PS11, Line 9: ioc > IOC Ack https://review.coreboot.org/c/coreboot/+/63198/comment/eaef2bf2_554d0fe6 PS11, Line 9: ioc register offset override > Please elaborate, what the default is, and when it should be changed. Will remove this for now as there is one version of SOC to support IOC and add later if new SOC has different offsets. File src/soc/intel/common/block/ioc/ioc.c: https://review.coreboot.org/c/coreboot/+/63198/comment/b8186eeb_f4127aa8 PS5, Line 9: MCH_BASE_ADDRESS > > MCHBAR should be enabled very early (in bootblock) […] I think it'll be safe to add. I'll add condition check and print out error message. File src/soc/intel/common/block/ioc/ioc.c: https://review.coreboot.org/c/coreboot/+/63198/comment/90441961_3b0f9482 PS12, Line 15: read32 > > Ack […] Done File src/soc/intel/common/pch/lockdown/lockdown.c: https://review.coreboot.org/c/coreboot/+/63198/comment/e70f2494_e87742b3 PS11, Line 31: #if !CONFIG(SOC_INTEL_COMMON_BLOCK_IOC) : gpmr_or32(GPMR_DMICTL, GPMR_DMICTL_SRLOCK); : #endif > Please use C code and not the preprocessor. Ack File src/soc/intel/common/pch/lockdown/lockdown.c: https://review.coreboot.org/c/coreboot/+/63198/comment/70db5bc1_de57517f PS12, Line 32: GPMR_DMICTL > > Yes, With IOC interface, there is no CTL register and it does not need to do it. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I768027c2ca78310c03845f70f17df19dc8cd0982 Gerrit-Change-Number: 63198 Gerrit-PatchSet: 13 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 22:26:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: implement ioc driver
by Wonkyu Kim (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Jamie Ryu, Wonkyu Kim, Ethan Tsao, Ravishankar Sarawadi, Paul Menzel, Tim Wawrzynczak, Angel Pons, Nick Vaccaro. Hello build bot (Jenkins), Jamie Ryu, Subrata Banik, Ethan Tsao, Ravishankar Sarawadi, Nick Vaccaro, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63198 to look at the new patch set (#13). Change subject: soc/intel/common: implement ioc driver ...................................................................... soc/intel/common: implement ioc driver DMI is replaced to IOC(I/O Cache) in new SOC like MTL which does not use PCH. Reference: 643504 MTL FAS section 7.5.2 TEST=Build and boot to OS for TGL RVP and MTL PSS Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I768027c2ca78310c03845f70f17df19dc8cd0982 --- M src/soc/intel/common/block/gpmr/gpmr.c M src/soc/intel/common/block/include/intelblocks/gpmr.h A src/soc/intel/common/block/include/intelblocks/ioc.h A src/soc/intel/common/block/include/intelblocks/ioc_gpmr.h A src/soc/intel/common/block/ioc/Kconfig A src/soc/intel/common/block/ioc/Makefile.inc A src/soc/intel/common/block/ioc/ioc.c M src/soc/intel/common/pch/lockdown/lockdown.c 8 files changed, 113 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/63198/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/63198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I768027c2ca78310c03845f70f17df19dc8cd0982 Gerrit-Change-Number: 63198 Gerrit-PatchSet: 13 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: cpu/x86/smm: Refactor creating a stub/save state map
by Arthur Heymans (Code Review) 13 Apr '22

13 Apr '22

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63474 ) Change subject: cpu/x86/smm: Refactor creating a stub/save state map ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63474/comment/da392fbb_a065e982 PS2, Line 9: This code was very hard to read so rewrite in a mostly pure functional : way. > fix English! Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a455ba45a1c92533a8ecfd1aeecf34b4a63e409 Gerrit-Change-Number: 63474 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 12 Apr 2022 22:22:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [VERY WIP]tests/cpu/x86/smm: Add unit tests
by Arthur Heymans (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Jakub Czapiga. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63560 ) Change subject: [VERY WIP]tests/cpu/x86/smm: Add unit tests ...................................................................... Patch Set 5: Code-Review-2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7462fa6155b8f8085256a027692cbead0ca3f08e Gerrit-Change-Number: 63560 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 22:22:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/x86/mp_init.c: Drop 'real' vs 'used' save state
by Arthur Heymans (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63479 to look at the new patch set (#10). Change subject: cpu/x86/mp_init.c: Drop 'real' vs 'used' save state ...................................................................... cpu/x86/mp_init.c: Drop 'real' vs 'used' save state Now that the save state size is handled properly inside the smm_loader there is no reason to make that distinction in the mp_init code anymore. Change-Id: Ia0002a33b6d0f792d8d78cf625fd7e830e3e50fc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/mp_init.c M src/cpu/x86/smm/smm_module_loader.c M src/include/cpu/x86/smm.h 3 files changed, 13 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/63479/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/63479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0002a33b6d0f792d8d78cf625fd7e830e3e50fc Gerrit-Change-Number: 63479 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2022