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Change subject: nb/amd/common: Move RAM calcualtion to common code
......................................................................
Patch Set 5:
(3 comments)
File src/northbridge/amd/common/ram_calc.c:
https://review.coreboot.org/c/coreboot/+/61682/comment/1c8c89f8_0427fca4
PS5, Line 28: >
> Should this be >= ?
No, this is correct, and comment in line #25 is wrong. Updated
https://review.coreboot.org/c/coreboot/+/61682/comment/5fe7b627_f3ac4c1f
PS5, Line 42:
> nit: double spaces.
Done
https://review.coreboot.org/c/coreboot/+/61682/comment/5d632be4_6274f1d0
PS5, Line 50: *limitk += 1; /* round up last byte for northbridge resource calculation convenience */
: *limitk /= KiB; /* Normalize to KiB */
> I think you need /= KiB first and then += 1.
Done
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Change subject: nb/amd/common: Move RAM calcualtion to common code
......................................................................
nb/amd/common: Move RAM calcualtion to common code
This patch addresses post-merge comments from CB:52922. This change
unifies the code used by AMD northbridges, and changes the type of
basek, sizek, limitk to u64.
TEST=Boot PC Engines apu1 and see that RAM resources do not change.
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: I3d222f6cbd26fe78d968d2883984f25e8b62ab5c
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/northbridge/amd/agesa/family14/Makefile.inc
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/Makefile.inc
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/Makefile.inc
M src/northbridge/amd/agesa/family16kb/northbridge.c
A src/northbridge/amd/common/ram_calc.c
M src/northbridge/amd/nb_common.h
M src/northbridge/amd/pi/00730F01/Makefile.inc
M src/northbridge/amd/pi/00730F01/northbridge.c
10 files changed, 99 insertions(+), 137 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/61682/6
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Change subject: soc/intel/common: Add support to control CSE firmware update
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62715/comment/d7f48ee6_b706f4e6
PS4, Line 9: The patch adds support to control CSE Lite firmware update dynamically.
> Please elaborate, what “dynamically” means.
Dynamic in the sense - after coreboot flashed on the system, developer can update 0xF00 byte to control the CSE firmware update feature on the next boot. Hence I used" dynamic" word.
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Change subject: mb/google/brask/variants/moli: update overridetree for moli
......................................................................
Patch Set 17:
(1 comment)
File src/mainboard/google/brya/variants/moli/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/63080/comment/0e07d146_4cecfafc
PS7, Line 8: option STORAGE_NVME 0
: option STORAGE_EMMC 1
> Ok, […]
Reopen this thread. I still don't get the answer in the b/220039297. Could you please disclose more details to the b/220039297 about how the factory proceed the FW_CONFIG?
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Change subject: arch/x86/postcar_loader: Correct off-by-one of MTRR end address in log
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63541/comment/fa9d3f00_54b82f66
PS2, Line 12: wrong
> @Werner Thanks!
>
> @Subrata Yes, I understand the motivation behind this change and I agree it's reasonable, but it doesn't correct or fix anything. Originally, the start was inclusive and the end was exclusive, and this change makes both inclusive. I am requesting two things:
>
> 1. Update the commit message so that it doesn't say this commit fixes/corrects something. I think "to be consistent with how resource allocator code prints ranges" is a better reason.
> 2. Also update other files that print MTRR ranges, for the sake of consistency.
I agree with both the suggestions @Angel.
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Change subject: soc/intel/denverton_ns: enable Denverton to use common SoC XHCI code
......................................................................
Patch Set 11:
(1 comment)
Patchset:
PS11:
a new patch series is being prepared to address this (and the remaining patch series issues, if any)
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Change subject: nb/amd/agesa/family14/northbridge.c: Report missing resources
......................................................................
Patch Set 12:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52935/comment/802057cf_8dc11bf1
PS9, Line 9: Not all resources were being reported, add them.
> Which ones exactly?
Added the list of added resources to the commit message
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59807
to look at the new patch set (#18).
Change subject: nb/amd/agesa/family14: Enable PARALLEL_MP
......................................................................
nb/amd/agesa/family14: Enable PARALLEL_MP
Disable LEGACY_SMP_INIT and enable PARALLEL_MP.
TEST=Boot Debian 11 on PC Engines apu1
Boot time reduced by ~3ms on average.
Inspired by CB:59693
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
Change-Id: I39a0779bdf115eebe31290591152b920acde773e
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/cpu/amd/agesa/family14/model_14_init.c
M src/northbridge/amd/agesa/family14/Kconfig
M src/northbridge/amd/agesa/family14/northbridge.c
3 files changed, 20 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/59807/18
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Michał Kopeć has uploaded a new patch set (#17) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/52781 )
Change subject: cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution
......................................................................
cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution
Create the correct MTRR solution based on the physical address space
provided by RESOURCE_ALLOCATOR_V4. Previously CPU initialization did not
account for lost C6 DRAM storage MTRR during postcar frame creation.
The BSP on 2GB has been stripped from UC MTRR covering C6 DRAM and
overlapping with usable DRAM WB MTRR. However this UC MTRR remained on
APs which caused inconsistent MTRRs warning in Linux. Use generic MTRR
function to create correct MTRR solution that propagates to APs. This
also fixes the inconsistent MTRRs warning.
TEST=boot Debian with Linux 4.14 on apu1 2GB
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: If706f8851ed0b1d45729e81175d82abb1d9193be
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/cpu/amd/agesa/family14/model_14_init.c
1 file changed, 16 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/52781/17
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Michał Kopeć has uploaded a new patch set (#13) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/52780 )
Change subject: northbridge/amd/agesa/family14: enable RESOURCE_ALLOCATOR_V4
......................................................................
northbridge/amd/agesa/family14: enable RESOURCE_ALLOCATOR_V4
TEST=boot Debian with Linux 4.14 on apu1 2GB
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: Ia01c5e238d53f719bb0d15e106517b99432a0c31
---
M src/northbridge/amd/agesa/family14/Kconfig
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